DE3129755C2 - Method for manufacturing an I → 2 → L semiconductor circuit arrangement - Google Patents

Abstract

A semiconductor device according to the invention has semiconductor island regions (13) of a first conductivity type which are dielectrically separated from one another. In each island zone (13), a first and a second sink zone (15, 16) of a second conductivity type opposite to the first conductivity type are formed. The first sink zone (16), the island zone (13) and the second sink zone (15) form a lateral transistor. At least one semiconductor zone (17) of the first conductivity type is formed in the first sink zone (16). This semiconductor zone (17), the first sink zone (16) and the island zone (13) form a vertical transistor. On a section or on the surface of the island zone (13), a first insulating layer (19) is provided which covers at least the transition or the barrier layer between the semiconductor zone (17) and the first sink zone (16) and extends over the first sink zone (16) extends. A polycrystalline silicon layer (18) doped with a foreign atom of the first conductivity type is designed in such a way that it covers the semiconductor zone (17) and part of the first insulating layer (19).

Description

characterized,
that after process step a) and before process step b) a second insulating layer (19, 19a, 19b) is formed which covers at least the surface of the collector zone (16),
that the second insulating layer (19, 19a, 196; is selectively etched to form exposed and non-exposed areas of the collector zone,
that the polycrystalline silicon layer (18) is formed in process step b) so that it also covers part of the surface of the second insulating layer and

that after process step d) the exposed part of the second insulating layer (19, 19a, \ 9b) is etched using the first insulating layer (22) as a mask so that the collector zone (16) is partially exposed.

2. The method according to claim 1, characterized in that the second insulating layer (19a,) made of silicon nitride will be produced.

3. The method according to claim 1, characterized in that the second insulating layer (19) is made of a silicon oxide layer ( 19b) and a silicon nitride layer (19a, 19a) formed on the latter.

The invention relates to a method for producing an I ² L semiconductor circuit arrangement according to the preamble of claim 1.

Such a method is known from IEDM 1979, Technical Digest, pp. 201-204.

This reference shows that a gate delay of 0.9 ns could be achieved. This I ² L construction uses a recessed oxide layer to reduce sidewall capacitance. Top collectors of inverse npn transistors are formed by arsenic insulation from a polycrystalline silicon layer formed directly on an epkaxial layer. The surface and the side walls of this arsenic-doped polycrystalline silicon layer are oxidized, whereupon it is etched in such a way that the oxidized layers remain on the side walls or surfaces of this silicon layer. In this way, the base contact holes are automatically aligned with the edges of the collectors

This method relies on the fact that the Rate of oxidation of polycrystalline! Silicon doped with a large amount of foreign atoms, is much larger than that of an epitaxial silicon layer. Namely, if the doped polycrystalline If the silicon layer is oxidized, a comparatively thick one forms on its surface and its side faces Oxide layer while only a very thin oxide layer arises from this on the epitaxial layer Even after the thin oxide layer has been etched on the epitaxial layer, the reason remains the thick oxide layer on the side surfaces of the doped polycrystalline silicon layer back so that the base contact hole with Self-alignment can be formed between the side surfaces.

If, however, (cf. IEDM 1979, Technical Digest, pp. 201-204), as can be seen from the partial sectional view of FIG. 1, an epitaxial layer 1 for forming a collector 2 on the top is doped with arsenic, the arsenic diffuses at the same time / citig also in a sideways direction. When an oxide layer 4 is etched, its parts located on the side surfaces of a polycrystalline silicon layer 3 are therefore also etched away. In this case, the transition or the barrier layer of the collector 2 on the top and the epitaxial layer (base) 1 can easily be exposed. If a metal layer 5 is then formed, the collector and base can be short-circuited against one another. Even if the impurity diffusion into the collector is shallow, it is difficult to form an oxide layer of sufficient thickness on the side surfaces of the polycrystalline silicon layer in the vicinity of the interface between this silicon layer and the epitaxial layer. The collector-base barrier layer can thus be exposed when the oxide layer is etched, whereby a short circuit is introduced. Although the previous I ² L circuits have excellent operating properties, they have the disadvantage that a collector-base short-circuit can occur.

The object of the invention is to provide a method for producing a PL semiconductor circuit arrangement in FIG To create the type mentioned above, in which the advantages of the semiconductor circuit arrangement described are obtained without the risk of a short circuit between the collector and the base being accepted got to.

This task is characterized by the characteristics of the Part of claim 1 solved.

In the following, the invention is explained in more detail in comparison to the prior art with reference to the drawing. Show it:
F i g. 1 is a partial sectional view of a short-circuited part of a collector-base barrier layer in a circuit arrangement according to the prior art. 2 is a partial sectional view of a semiconductor circuit arrangement;

3A to 3F are sectional views for illustration purposes successive process steps in a process for the production of the semiconductor shell arrangement according to FIG. 2,

F i g. 4 a view of the arrangement according to FIG. 31 '

Figures 5 and 6 are sectional views of other embodiments.

Fig. 1 has already been explained at the beginning. In the Figures are denoted by corresponding parts with the same reference numerals.

Figure 2 illustrates an I ² L semiconductor sound arrangement. This semiconductor circuit arrangement has an n ⁺ -type semiconductor substrate 11 and an epitaxial n-type layer 13 formed thereon. This epitaxial layer 13 is separated from adjacent epitaxial layers by defining an island zone by a sunk oxide layer 12 in each case. In this island zone 13, p-type zones are separated from one another

15 and 16 formed on these zones IS and 16 as well an insulating layer 14 is formed on the exposed part of the epitaxial layer 13

16 and the epitaxial layer 13 form a pnp Laleral transistor, in the case of the zone 15 the emitter or injector, the epitaxial layer 13 the base and the zone 16 form the actual collector.

In the p-type collector region 16, there are n-type regions 17 educated. The n-type zone 17, the p-type collector zone 16 and the epitaxial layer 13 form an "inverted" npn vertical transistor in which the n-type zone 17 is the collector, the p-type collector zone 16 is the Base and the epitaxial layer 13 form the emitter.

A (second) insulating layer 19 surrounding the n-type zone 17 is formed immediately below the edge of the doped polycrystalline silicon layer 18, ie from the p-type collector zone 16, in such a way that it at least forms the transition or the barrier layer of the top-side n-type collector zone 17 is covered with the p-type collector zone 16 and extends over a distance W on the p-type collector zone 16. This extension W of the insulating layer 19 is selected to be so large that the barrier layer between the top-side p-type collector 17 and the p-type collector zone 16 is not exposed when the doped polycrystalline silicon layer 18 is used to selectively leave parts of the same as well to form base contact holes 20 gcät / .t. This extension W must therefore be determined taking into account the mask accuracy and the lateral distance. In practice, this extension can be W2 to 3 μίτι. Due to the presence of this insulating layer 19, the collector-base barrier layer of the npn vertical transistor is not exposed and, when a metal layer 21 is formed, a short circuit between the collector and the base is thus prevented.

The doped polycrystalline silicon layer 18 also serves as a collector connection. On the surface and on the side surfaces of the remaining patterns of these Silicon layer 18, a first insulating layer 22 is also provided, which is opposite to silicon layer 18 the metal layer 21 is insulated.

The following is a method of making semiconductor circuitry using that described Structure initially based on FIG. 3A to 3F and 4 and then with reference to FIG. 5 and 6 explained.

First, according to FIG. 3A shows the epitaxial silicon layer 13 with a thickness of 0.5 to 1.5 μπι and a π type impurity concentration of 1 χ ΙΟ ¹⁵ to ^r ) χ 10 ¹⁶ CMi 'on an η + -type semiconductor substrate, ζ. Β. an η 'silicon substrate 11 is formed. Then, in order to define island zones, the oxide layers 12, for example thickly recessed, are formed by etching and oxidation with a mask.

Then according to FIG. 3B on the surface of each island zone a strip-shaped, e.g. B. about 0.4 µm thick oxide insulating layer 14 is formed. Using this oxide layer 14 as a mask, p-type impurities such as boron are diffused in from the surface of the island region 13 that is exposed to the outside around p-type regions 15 and 16. The diffusion depth can be, for example, 0.6 μm, and the sheet resistance of zones 15 and 16 can be 250 Ω / D or Ω / cm ^2. In this diffusion process, the exposed surface In the next method step illustrated in FIG 3B is formed by chemical vapor deposition (CVD) on the entire surface of the device without removing the silicon oxide layer 19fe R zones 16 are selectively etched using a photo-etching process to form collector contact holes 23. Then according to FIG. 3D on the entire surface of the arrangement the, for example, approximately 0.4 μm thick polycrystalline silicon layer 18, which is doped with n-type foreign atoms, such as phosphorus or arsenic, ^{in a high concentration of, for example, 19} to 10 ²¹ cm ^J. This doped, polycrystalline silicon layer 18 can be formed by direct deposition of doped polycrystalline silicon in an atmosphere containing n-type foreign atoms using the chemical vapor deposition method; optionally, undoped polycrystalline silicon can be deposited by the chemical vapor deposition process and then doped with predetermined n-type impurities using an ion implantation process. This silicon layer 18 can be produced more uniformly and more quickly in the manner described last, because undoped polycrystalline silicon can be deposited more quickly.

In the next process step, the doped polycrystalline silicon layer 18 is selectively etched away, the parts of this silicon layer remaining under which collectors are to be formed and which are partly located on the silicon nitride layers 19a, so that holes 24 are formed through which the silicon nitride layers 19a after exposed outside. The collector zones 17 are then formed in that the foreign atoms contained in the doped polycrystalline silicon layer 18 are ^{diffused in by heating to approximately 800 to 1000 °} C. in an oxygen atmosphere or in (water) vapor. Simultaneously with this, thick silicon oxide layers 22 with a thickness of e.g. B. 0.2 μπι to 0.3 μιτι formed. During this process, the silicon nitride layers 19a exposed to the outside are not oxidized.

In the next method step according to FIG. 3F, using the silicon oxide layers 22 as Mask etched the exposed silicon nitride layers 19a by reactive ion etching or plasma etching, while the exposed silicon oxide layers 196 using the remaining silicon nitride layer 19a be etched as a mask. Since the silicon oxide layers 22 are sufficiently thick (e.g. 4 to 6 times) than that Silicon oxide layers 196, they become during the etching process

not worn away. In this way, the base vias 20 become self-aligned educated. In other words, the base vias 20 are made without the need for a Mask adjustment molded. For a better understanding of the invention, Fig. 4 illustrates the arrangement according to FIG. 3F schematically in top view.

Finally, a metal layer, such as an aluminum layer (the aluminum layer 21 shown in FIG. 2), is formed on the surface of the structure shown in FIG. 3F. After this aluminum layer 21 has been shaped in a predetermined pattern, the I ² L semiconductor circuit arrangement shown in FIG. 2 is obtained.

In the arrangement described, a short circuit between the collector and the base of the npn vertical transistor can essentially be prevented by the silicon nitride layers 19a even if the silicon oxide layers 196 are not provided. However, if the silicon nitride layers are formed directly on silicon, crystal dislocation may occur at their interface. For this reason, the silicon oxide layers 196 are preferably formed in order to keep this crystal dislocation as small as possible.

The silicon oxide layers 22 produced by thermal oxidation of the polycrystalline silicon layer tend to form pinholes, with an occasional short circuit between the metal layers 21 and the polycrystalline silicon layer 18 can occur. To avoid this phenomenon, after production of the structure according to Fi g. 3D according to the chemical vapor deposition process according to FIG. 5 a silicon oxide layer 50 are formed on the polycrystalline silicon layer 18, whereupon the desired semiconductor circuit arrangement after the reference to FIG. 3E and 3F described method produced or completed can be. After the foreign atoms have diffused in to produce the collectors, the Oxide layer 50 is heated so that it has a density which is that of a thermally oxidized layer is comparable.

Furthermore, as shown in FIG. 6, thin polycrystalline silicon layers 60 containing p-type impurities, e.g. B. Boron. Contain a concentration of IxIO ¹⁹ to 1 χ 10 ²⁰ cm- ¹ , in a thickness of z. B. 0.2 μπι to 03 μπι be formed on the parts of the sink zones 16 exposed to the outside through the base contact holes 20, after which the aluminum layer 21 can be formed and patterned on this arrangement. In this way, a separation of the Aiuminiumschicht 21 can be prevented 19a due to the overhanging arrangement during etching of the silicon oxide layers 19 £> after etching the silicon nitride layers. Furthermore, by diffusing in the p-type impurities from the polycrystalline silicon layer 60, the collector-base barrier layer of the npn vertical transistor is displaced further inward. In addition, the base contact resistance can be effectively reduced by forming the layer 60.

For this purpose 4 sheets of drawings

Claims (1)

Patent claims: 1. A method for producing an I ² L semiconductor circuit arrangement with the following method steps: a) in a dielectrically isolated semiconductor island zone of a first conductivity type, an emitter and a collector zone of a second, the first conduction type opposite conduction type formed so that a lateral transistor is formed by the emitter zone, the collector zone and the island zone, b) a polycrystalline silicon layer containing dopants of the first conductivity type is so designed so that it at least partially covers the exposed surface of the collector zone, c) a semiconductor zone of the first conductivity type is formed in the collector zone by outdiffusion the dopants from the polycrystalline silicon layer formed and d) a first insulating layer is placed on the surface and the side faces of the polycrystalline silicon layer educated,