DE2219696C3 - Method for producing a monolithically integrated semiconductor device - Google Patents

Description

55

The invention relates to a method for producing a monolithically integrated semiconductor arrangement, in which doping material producing the opposite conductivity type diffuses selectively at predetermined surface locations of a semiconductor substrate of one conduction type and, after an epitaxial semiconductor layer of one conduction type has been applied to the substrate, the diffused doping material to form redoped insulation material. ^{h5 is} outdiffused up to the surface of the epitaxial layer and in which field effect transistors with an insulated gate which are complementary to one another are produced inside and outside the insulation regions thus formed.

The manufacture of integrated circuits that contain both bipolar transistors in the same semiconductor body as well as field effect transistors, has long been known and many proposals in this direction have already been done

For example, US Pat. No. 3,293,087 describes a method for producing bipolar and junction field effect transistors in the same semiconductor substrate. While isolation wells are produced by Umdotieren of parts of a layer applied to the substrate the epitaxial semiconductor layer of the same to the substrate conductivity type for isolating the semiconductor circuit elements from each other by allowed to two dopants of different diffusion rate and initial concentration in spatially ^plane: diffuse nanderliegenden areas. The faster diffusing dopant creates the walls of the insulating tubs and the slower diffusing their bottom.

From US Patent 34 40 503 it is known for the production of field effect transistors with isolated Gate to selectively redop an epitaxial semiconductor layer by outdiffusion in order to enter the redoped Areas field effect transistors of the one conductivity type and outside the redoped areas in addition to produce complementary field effect transistors each with optimal electrical properties. Wanted to if you also produce bipolar transistors in the redoped areas, these could be because of the for them unfavorable doping concentration can only be produced with mediocre electrical properties.

US Pat. No. 3,481,801 describes a method for insulating semiconductor circuit elements, which manages without a special insulation diffusion. The transistors are doing this in areas an epitaxial semiconductor layer of the conductivity type corresponding to the substrate, which is formed by outdiffusion be redeployed. The areas of the epitaxial layer that have not been redoped act as an insulation area.

Finally, it is from the French laid-open specification 20 17 125 in a method of the above known, within isolation areas redoped by outdiffusion, either bipolar or To produce field effect transistors with an insulated gate, with the formation of field effect transistors arranged outside the isolation areas field effect transistors of the complementary type will.

The known processes for the production of bipolar and field effect transistors in the same Semiconductor substrates represent a compromise between optimally designed methods to, on the one hand, the to produce bipolar transistors and, on the other hand, the field effect transistors with the highest possible quality, and between simplified processes in which the transistors formed are not those in one Have individual production achievable quality. One of the major difficulties with these procedures lies in that the required doping concentration of the substrate for bipolar transistors is at least around is an order of magnitude different from that of the substrate for field effect transistors.

In a method for producing the collector zone of a self-isolating bipolar transistor in a monolithic semiconductor arrangement has also been proposed to use two doping

Substances of different initial concentration and diffusion rate in an epitaxial semiconductor layer of the conductivity type corresponding to the substrate to diffuse out until the more rapidly diffusing Dopant has reached the top surface of the epitaxial layer, whereas the Dopant with the lower diffusion rate is a highly doped buried layer of the Forms substrate of opposite conductivity type, see older registration P 20 55 162.6-33. ι ο

It is therefore the object of the present invention to provide bipolar transistors and transistors that are complementary to one another Field effect transistors with insulated gate in the same monolithic substrate and still with optimal Properties to produce. Process steps are to be used that already existed during the Manufacture of bipolar or field effect transistors are known and are therefore well mastered.

The above-mentioned object is in the initially mentioned method for producing a monolithic integrated semiconductor arrangement according to the invention achieved in that at the same time bipolar transistors are formed in the isolation areas and, for this purpose, two dopants as doping material different diffusion velocities are used, their initial concentrations and diffusion coefficients be chosen so that a both for the formation of the bipolar transistors as well vertical doping profile suitable for the field effect transistors generated within the isolation areas arises.

The doping concentrations required for both types of transistor for field effect transistors lying outside the isolation areas are essentially independent of one another, since the basic doping of the epitaxial layer is carried out in such a way that it has an optimal value for the production of field effect transistors and the doping concentrations in the Isolation areas can be controlled as they are needed for the formation of bipolar transistors. As a result of the outward diffusion of the dopants, a course of the doping concentration is obtained in the isolation regions which increases from a relatively low value on the surface of the epitaxial layer to a relatively high value in the lower part of the epitaxial layer. This course is controlled by a suitable choice of the initial concentrations and the diffusion coefficients of the two out-diffusing dopants in such a way that optimal doping concentrations arise in an isolation area for both the formation of a bipolar and a field effect transistor. The doping concentration on the surface of the epitaxial layer is preferably about 10 ¹⁶ atoms per cm ¹ both inside and outside the isolation regions. This concentration is particularly suitable for substrates in which field effect transistors of the P- and N-channel type are produced. By Ausdiffu- fc> o sion of the two or doping impurities can be further achieved that a bipolar transistor is formed in the isolation regions in a depth at which subsequently the Koilektorzone, a preferred doping concentration of 10 "Ato ^h '> men / cm ³ occurs.

The invention is described in more detail below with reference to an embodiment shown in the figures. It shows

F i g. 1 to 6 simplified sectional views of the individual steps of the claimed method corresponding semiconductor structure,

F i g. 7 shows the course of the doping concentrations in the in Fi g. 1 illustrated substrate and

8 shows the course of the doping concentrations of an NPN transistor formed in an isolation area.

1 shows a P-type silicon substrate 1 cut in the [100] plane with a doping concentration of at most 10 ¹⁵ atoms / cm ³ . The substrate, which has a resistance of about 10 to 20 ohm-cm, is initially coated with a layer 2 of silicon dioxide. A window 3 is etched out of the layer 2 in a known manner and a subcollector-like area 4 is diffused through the window 3 into the substrate 1 at the point at which an insulation area is to be formed later. Two such areas 4 and 5 are shown in FIG. 1 shown. Each of the areas 4 and 5 contains two contaminants, e.g. B. arsenic and phosphorus, which have different diffusion rates and concentrations and which both cause a conductivity opposite to the P substrate 1. Typical curves of the concentrations for arsenic and phosphorus after their penetration into the substrate 1 are shown in FIG. Areas 4 and 5 are formed, for example, by capsule diffusion at 1100 ° C. for 60 minutes. The diffusion results in a sheet resistance of 7 Ohm / D and a transition depth of 1.1 μίτι when using a mixture of 1.5 g of silicon doped with 2% arsenic and 1.5 g of silicon doped with 10 ¹⁹ atoms / cm ^{3 of} phosphorus as a source. The powder is prepared from separately stored arsenic-doped silicon and phosphorus-doped silicon immediately before the capsule is sealed.

Next, layer 2 of silicon dioxide is removed from the substrate! removed and a 3 μίτι thick P-conductive epitaxial semiconductor layer 6 with a resistance of 2.0 ohm · cm deposited on the substrate, as shown in FIG. 2 shows. At the end of the epitaxial deposition, the impurities phosphorus and arsenic have diffused somewhat into the layer 6. The more slowly diffusing arsenic is located in the area 13 delimited by a dashed line, while the faster diffusing phosphorus is located in the area 14 delimited by a solid line. The oxide layer 15 of FIG. 3 is formed on the surface of the epitaxial layer 6, and the arsenic and phosphorus impurities are diffused out until the phosphorus has passed through the layer 6 to the surface thereof. Now, in the layer 6 on the P-conductive substrate 1, the insulation areas 16 and 19 are formed from N-conductive material. The region 16 has an N + zone 17 with a high doping concentration, ie with about 10 ²⁰ atoms / cm ³ arsenic and phosphorus, and an N zone 18 with a lower concentration that decreases towards the top, ie with about 10 ¹⁸ atoms / cm ³ in the vicinity of zone 17 and with about 10 ¹⁶ Atcmen / cm ³ on the surface, which contains out-diffused phosphorus. Various circuit elements can now be formed within the isolation areas 16 and 19. A bipolar transistor can e.g. B. be produced by successively diffusing base and emitter zones into such an area.

In the present embodiment, where N-conductors

If isolation regions are formed in a P-type epitaxial layer on a P ~ substrate, an NPN transistor and a P-channel field effect transistor are formed in these regions, and an N-channel field effect transistor is formed in the epitaxial layer between the isolation regions. The resulting integrated structure shows that each isolation area is formed by diffusion of the impurities upwards from the boundary layer between the epitaxial layer and the substrate. This outdiffusion creates a self-insulating area which has a doping concentration decreasing upwards, ie which changes from a high doping (N ⁺ ) in the lower part to a lower doping (N) in the upper part. The doping concentration in the lower part is suitable for sub-collector and collector areas of an N PN transistor, whereas the doping concentration in the upper part, which can be orders of magnitude smaller, is suitable for the optimal production of field effect transistors. Typical doping concentrations of arsenic and phosphorus as well as the basic doping concentrations in an isolation area are shown in FIG. 8 shown. The dashed curves 9 and 10 represent the arsenic and phosphorus concentration when the out-diffusion is still incomplete; curves 11 and 12 show the end dopings. The straight lines 38 and 39 indicate the P-substrate doping and the P-doping of the epitaxial layer.

An NPN transistor is now formed in the isolation area 16, a P-channel field effect transistor in the area 19 and an N-channel field effect transistor in the epitaxial layer 6 between the areas 16 and 19, as shown in FIG. 4, 5 and 6 show. The way in which the base and emitter zones of the bipolar transistor and the source and drain zones of the field effect transistors are formed is essential for the simplicity of the method. With the usual diffusion, e.g. B. a vapor phase diffusion, or ion implantation, the source and drain zone of the P-channel field effect transistor are introduced simultaneously with the base zone of the NPN transistor. Source and drain zone of the N-channel field effect transistor, however, are simultaneously with the emitter zone of the N PN- Transistor made. The windows 20, 21, 22 and 23 in the oxide layer 15 of FIG. 4 simultaneously create a P diffusion for the base zone of the bipolar transistor, the substrate contact zone of the N-channel field effect transistor and the source and drain zone of the P-channel -Field effect transistor introduced. A suitable impurity for diffusion is boron. In the exemplary embodiment! Generates a capsule diffusion with a source with 7.5 · 10 "atoms of boron / cm ³ at a temperature of 1000 ° C for a diffusion time of 60 minutes, a sheet resistance of 169 Ohm / D and a base transition depth of 0.6 μητ.

The P ⁺ diffusion is followed by oxidation at 907 ° C in oxygen, water vapor and oxygen for 5.45 and 5 minutes respectively up to an oxide thickness of 280 nm. The sheet resistance of the boron diffusion increases to 449 Ohm / Π and the base transition depth 0.65 μm. By photolithographic treatment, windows 24 to 28 are exposed in the oxide layer for the emitter zone and the collector contact zone of the bipolar transistor, the source and drain zone of the N-channel field effect transistor and the substrate contact zone of the P-channel field effect transistor. A ^ diffusion simultaneously creates the emitter zone 29 and the collector contact zone 30 of the NPN transistor in the isolation area 16, the substrate contact zone 31 for the P-channel field effect transistor in the isolation area 19 and the source zone 32 and drain zone 33 of the N-channel field effect transistor in the epitaxial layer between the regions 16 and 19. The N + diffusion is preferably carried out as a capsule diffusion at a temperature of 1000 ° C. for 60 minutes with a silicon source doped with 1.55% arsenic. This creates a sheet resistance of 20 Ohm / G and a transition depth of 0.275 μΐη. Oxidation at 970 ° C. using oxygen, water vapor and oxygen for 5, 20 and 5 minutes respectively produces an oxide thickness of 300 nm and increases the sheet resistance to 30 Ohm / D and the

! 5 transition depth to 0.375 μm,

The N-channel field effect transistor and the P-channel field effect transistor are constructed in a known manner. The oxide is over the active areas of the N- and of the P-channel is removed and new layers 34 and 35 are applied to a desired thickness. That new oxide is charge stabilized, e.g. B. by applying a layer of phosphosilicate glass and then Heat. Finally, the control electrodes 36 and 37 of the field effect transistors and the necessary metal contacts formed, such as F i g. 6 shows.

Arsenic is used to form the N + regions 29 to 33

to other interfering substances causing an N line, such as B. phosphorus, because arsenic doping of the emitter improves the high-frequency behavior of an NPN transistor. In addition, arsenic diffuses over a much shorter distance than phosphorus to achieve a given resistance value in the substrate and thus allows the source and drain diffusion of a field effect transistor to be arranged closer to one another. This reduction in size enables a substantial increase in the density of shading elements on the die. In addition, if arsenic is used instead of phosphorus, the properties of the transistors remain essentially unaffected by the subsequent three high-temperature processing cycles required to complete the field effect transistors, i.e. the growth of the oxide under the control electrodes at 97O ⁰ C, the deposition of the phosphosilicate glass at 900 ° C and then annealing at 1050 ⁰ C. the base width of a bipolar transistor would be very difficult to control in the use of phosphorus as a dopant for the emitter zone and for the source and drain regions. Arsenic as a slower diffusing dopant allows better control of the base width.

In principle, the basic doping of the substrate and the epitaxial layer can reduce the initial concentrations of the subsequently introduced interfering substances in the substrate, e.g. B. phosphorus and arsenic, the junction depth, etc. can be changed, depending on the type of transistors to be formed in the corresponding isolation areas. It has been found that at doping concentrations greater than about 10 ²¹

wi atoms / cm ³ in the substrate, the arsenic spreads laterally along the interface between the epitaxial layer and the substrate during the growth of the epitaxial layer

•; Distance between adjacent isolation areas increased and in the worst case even such areas

- can short-circuit. The easiest way to avoid this problem is that the surface

concentration of arsenic is kept below 10 ²¹ atoms / cm ³ . An increased basic doping at the beginning of the epitaxial growth is also advantageous, since this compensates for a lateral outdiffusion.

For this purpose 2 sheets of drawings

Claims (5)

Patent claims: 1. A method for producing a monolithically integrated semiconductor device, in which on predetermined surface locations of a semiconductor substrate of the one conductivity type selectively the opposite conductivity type generating dopant diffused and after application an epitaxial semiconductor layer of the one Ό conductivity type on the substrate that diffused Doping material for the formation of redoped isolation areas up to the surface of the epitaxial Layer is diluted and in the case of the inside and outside of the isolation areas thus formed Complementary field effect transistors with insulated gate are generated, characterized in that simultaneously bipolar transistors in the isolation areas are formed and two dopants with different diffusion speeds are used as doping materials are used, the initial concentrations and diffusion coefficients of which are chosen so that a both for the Formation of the bipolar transistors as well as the field effect transistors generated within the isolation areas suitable vertical doping profile arises. 2. The method according to claim 1, characterized in that the base zones of the bipolar transistors and the source and drain zones of the field effect transistors formed in isolation regions (19) can be produced in one process step. 3. The method according to claim 1 or 2, characterized in that the emitter zones (29) of the bipolar transistors and the source (32) and drain zones (33) of the outside of the isolation areas (16, 19) formed field effect transistors can be produced in one process step. 4. The method according to any one of claims 1 to 3, characterized in that the initial concentration of the dopant with the lower diffusion rate is higher than the initial concentration of the dopant with the greater diffusion rate. 5. The method according to any one of claims 1 to 4, characterized in that as dopants Arsenic and phosphorus are used. 50