DE2219696A1 - Procedure for creating isolation areas - Google Patents

Description

Boeblingen, April 18, 1972 bm-we

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504

Official file number: New registration File number of the applicant: FI 971 001 Additional registration to registration P 20 55 162.6

Procedure for creating isolation areas '

The invention relates to a method for forming isolation regions in a monolithic semiconductor device having a semiconductor substrate of the one conductivity type in which two impurities with different diffusion rates of the other conductivity type into the substrate via desired surface locations are introduced and a layer of one conductivity type is epitaxially formed on the substrate, the epitaxial Layer and the substrate are exposed to a treatment in which the impurity with the higher diffusion rate through the epitaxial layer diffuses through to its surface, and thereby isolation areas in the epitaxial layer arise, according to patent application P 20 55 162.6.

The manufacture of integrated circuits in the same semiconductor body contain both bipolar transistors and field effect transistors has long been known and many proposals in this direction have already been made. So far, such proposals have concerned either a compromise between optimally designed Method to on the one hand the bipolar transistors and on the other hand the field effect transistors with the highest possible Quality production and between simplified processes in which the transistors formed are not those in a single production possess achievable quality. One of the major difficulties with this method is that the required

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Doping concentration of the substrate for bipolar transistors at least one order of magnitude different from that of the substrate for field effect transistors.

It is therefore the object of the present invention to provide bipolar and field effect transistors with the same monolithic substrate and nevertheless to achieve doping concentrations that are essentially independent of one another for both. This should Process steps are applied that are already in the production are known in each case from bipolar or field effect transistors and are therefore well mastered. This task is carried out with the initially mentioned method for the formation of isolation areas solved according to the invention in that within isolation areas bipolar transistors and formed within isolation areas and / or outside of these field effect transistors will.

The doping concentrations required for both types of transistors in the case of field effect transistors lying outside the isolation areas are essentially independent of one another, since the basic doping the epitaxial layer is designed so that it has an optimal value for the production of field effect transistors and because the doping concentrations in the isolation areas are controlled by the out-diffusion of two impurities as needed for the formation of bipolar transistors. Through the diffusion of the contaminants, one obtains in the isolation areas a course of the doping concentration, which from a relatively low value on the surface of the epitaxial layer rises to a relatively high value in the lower part of the epitaxial layer. This course can e.g. can be controlled by suitable choice of the initial concentrations of the two out-diffusing impurities in such a way that optimal doping concentrations in an isolation area both for the formation of a bipolar and a field effect transistor develop. The doping concentration on the surface of the epitaxial layer is both within also outside the isolation areas, preferably about 10 atoms

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per cm ³ . This concentration is particularly suitable for substrates in which field effect transistors of the P- and N-channel type are produced. As a result of the diffusion of the two impurities, it can also be achieved that a preferred doping concentration is achieved in the insulation areas at a depth at which the collector of a bipolar transistor is subsequently formed

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of 10 atoms / cm occurs.

The invention is illustrated below with reference to one in the figures Embodiment described in more detail.

Show it:

Figs. 1 to 6 simplified sectional views of the individual

Steps of the claimed method corresponding semiconductor structure,

7 shows the course of the doping concentrations in

the substrate shown in Fig. 1 and

8 shows the course of the doping concentrations of a

NPN transistor formed in an isolation area.

1 shows a P ~ -silicon substrate 1 cut in the [100] plane with a doping concentration of at most 10 atoms / cm. The substrate, which has a resistance of about 10 to 20 ohm χ cm, is initially coated with a layer 2 of silicon dioxide. A window 3 is etched out of the layer 2 in a known manner and a subcollector-like area 4 is diffused through the window 3 into the substrate 1 at the point at which an insulation area is to be formed later. Two such areas 4 and 5 are shown in FIG. Each of the areas 4 and 5 contains two impurities, for example arsenic and phosphorus, which have different diffusion speeds and concentrations and which both cause a conductivity opposite to that of the P ~ substrate 1. Typical courses of the ^v

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Concentrations for arsenic and phosphorus after their penetration into the substrate 1 are shown in FIG. The regions 4 and 5 are for example formed by a diffusion capsule at 1100 ⁰ C for 60 minutes. The diffusion gives a sheet resistance of 7 ohms / a and a junction depth of 1.1 µm when using a mixture of 1.5 g of silicon doped with 2% arsenic

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and 1.5 g of silicon doped with 10 atoms / cm of phosphorus as a source. The powder is made from separately stored silicon doped with arsenic and immediately before the capsule is sealed prepared with silicon doped with phosphorus.

Next, the layer 2 of silicon dioxide is removed from the substrate 1 and a 3 µm thick P-type epitaxial layer 6 with a resistance of 2.0 ohm χ cm is grown, as FIG. 2 shows. At the end of the epitaxial deposition, the impurities phosphorus and arsenic have diffused somewhat into the layer 6. The more slowly diffusing arsenic is located in the area 13 delimited by a dashed line, while the faster diffusing phosphorus is located in the area 14 delimited by a solid line. The oxide layer 15 of FIG. 3 is then formed on the surface of the epitaxial layer 6 and the arsenic and phosphorus impurities are diffused out until the phosphorus has passed through the layer 6 to its surface. Now, in the layer 6 on the P ~ -conducting substrate 1, the insulation areas 16 and 19 are formed from N-conductive material. The region 16 has an N ⁺ zone 17 with a high doping concentration, ie with approximately 10 atoms / cm of arsenic and phosphorus, and an N-zone 1.8 with a lower concentration that decreases towards the top, ie with approximately 10 atoms / cm in the vicinity of zone 17 and with about 10 atoms / cm on the surface, which contains out-diffused phosphorus. Various circuit elements can now be formed within the insulation areas 16 and 19. A bipolar transistor can be produced, for example, by successively diffusing the base and emitter into such an area.

In the present exemplary embodiment, where N-conductive insulation areas are in a P-conductive epitaxial layer on a! '"Substrate

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are formed, an NPN transistor and a P-channel field effect transistor in these areas and an N-channel field effect transistor formed in the epitaxial layer between the isolation regions. The resulting integrated structure shows that each isolation area by diffusion of the impurities upwards out of the boundary layer between the epitaxial layer and Substrate is formed. This outward diffusion creates a self-insulating one Area which has an upwardly decreasing doping concentration, i.e. which differs from a high doping (N) in the lower part changed to a lower doping (N) in the upper part. The doping concentration in the lower part is suitable for sub-collector and collector areas of an NPN transistor, whereas the doping concentration in the upper part, which can be orders of magnitude smaller, is suitable for the optimal production of field effect transistors. Typical doping concentrations of arsenic and phosphorus as well as the basic doping concentrations in an isolation area are shown in FIG. The dashed curves 9 and 10 represent the arsenic and phosphorus concentrations represents when the outdiffusion is still incomplete; curves 11 and 12 show the end dopings. The straight lines 38 and 39 indicate the P substrate doping and the P doping of the epitaxial layer.

An NPN transistor is now formed in isolation area 16, a P-channel field effect transistor in area 19 and an N-channel field effect transistor in the epitaxial layer 6 between the areas 16 and 19, as shown in FIGS. 4, 5 and 6 show. Essential for the Simplicity of the process is the way in which the base and emitter of the bipolar transistor as well as the source and drain of the Field effect transistors are formed. With the usual diffusion, e.g. a vapor phase diffusion, or ion implantation source and sink of the P-channel field effect transistor become simultaneously introduced with the base of the NPN transistor. The source and sink of the N-channel field effect transistor, on the other hand, are simultaneously with the emitter of the NPN transistor. Through the Windows 20, 21, 22 and 23 in the oxide layer 15 of FIG

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at the same time a P diffusion introduced for the base region of the bipolar transistor, the substrate contact of the N-channel field effect transistor and the source and drain of the P-channel field effect transistor. A suitable impurity for diffusion is boron. In the, embodiment generates a capsule diffusion to a source of 7.5 χ 10 atoms boron / cm at a temperature of 1000 ⁰ C for a diffusion time of 60 minutes, a surface resistance of 169 ohms / a and a Base junction depth of 0.6 µm.

The P diffusion is followed by an oxidation at 907 C in oxygen, Water vapor and oxygen for 5, 45 and 5 minutes respectively up to an oxide thickness of 2800 Å. The sheet resistance of boron diffusion This increases to 449 Ohm / n and the base transition depth to 0.65 pm. By photolithographic treatment Windows 24 to 28 exposed in the oxide layer for the emitter area and the collector contact area of the bipolar transistor, the source and drain area of the N-channel field effect transistor and. the substrate contact area of the P-channel field effect transistor. An N diffusion simultaneously creates the emitter 29 and the collector contact 30 of the NPN transistor in the isolation area 16, the substrate contact 31 for the P-channel field effect transistor in the Isolation area 19 and source 32 and drain 33 of the N-channel field effect transistor in the epitaxial layer between regions 16 and 19. The N diffusion is preferably used as Capsule diffusion carried out at a temperature of 1000 C for 60 minutes with a silicon source doped with 1.55% arsenic. This results in a sheet resistance of 20 Ohm / q and creates a transition depth of 0.275 pm. An oxidation at 970 C using oxygen, water vapor and oxygen for 5, 20 and 5 minutes, respectively, creates an oxide thickness of 3000 Ä * and increases the sheet resistance to 30 Ohm / a and the Transition depth to 0.375 pm.

The N-channel field effect transistor and the P-channel field effect transistor are constructed in a known manner. The oxide is removed and new over the active areas of the N and P channels

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Layers 34 and 35 are grown to a desired thickness. The new oxide is charge-stabilized, e.g. by applying a layer of phosphosilicate glass and then heating it. Finally, the control electrodes 36 and 37 of the field effect transistors and the necessary metal contacts are formed, as shown in FIG. 6 shows.

To form the N ⁺ regions 29 to 33, arsenic is preferred over other interfering substances causing an N conduction, such as phosphorus, because arsenic doping of the emitter improves the high-frequency behavior of an NPN transistor. In addition, arsenic diffuses a much shorter distance than phosphorus to achieve a given resistance value in the substrate, thus allowing the. Source and drain diffusion of a field effect transistor to be arranged closer to one another. This reduction in size enables a substantial increase in component density on the die. In addition, if arsenic is used instead of phosphorus, the properties of the transistors remain essentially unaffected by the subsequent three high-temperature processing cycles required to complete the field-effect transistors, i.e. the growth of the oxide under the control electrodes at 970 ^° C., the deposition of the phosphosilicate glass at 900 ⁰ C and the subsequent annealing at 1050 ° C. The base width of a bipolar transistor would be very difficult to control when using phosphorus as a dopant for the emitter and for the source and drain. Arsenic as the slower diffusing dopant allows better control of the base width.

In principle, the basic doping of the substrate and the epitaxial layer, the initial concentrations of the subsequently introduced impurities in the substrate, e.g. phosphorus and arsenic, the transition depth, etc. can be changed, depending on the type of transistors to be formed in the corresponding insulation areas. It was found that with doping concentrations of more than about 10 atoms / cm ³ in the substrate, a lateral spread of the arsenic along the interface between the ^1st

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epitaxial layer and the substrate takes place during the growth of the epitaxial layer. One such spread is undesirable because it increases the required distance between adjacent isolation areas and, in the worst case, such Can even short-circuit areas. The easiest way to avoid this problem is to reduce the surface concentration

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of arsenic is kept below 10 atoms / cm. An increased basic doping at the beginning of the epitaxial growth is also advantageous, since this compensates for a lateral outdiffusion.

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Claims (1)

PATENT CLAIMS A method of forming isolation regions in a monolithic semiconductor device having a semiconductor substrate of the one conductivity type in which two impurities with different diffusion rates of the other conductivity type into the substrate via desired surface locations and a layer of one conductivity type is epitaxially formed on the substrate is, wherein the epitaxial layer and the substrate one Treatment are exposed in which the impurity with the higher diffusion rate through the epitaxial Layer diffused through to its surface and thereby isolation areas in the epitaxial layer arise, according to patent application P 20 55 162.6, characterized in that within isolation areas (16) bipolar transistors and within isolation areas. (19) and / or are formed outside of these field effect transistors. Method according to Claim 1, characterized in that the base regions of the bipolar transistors and the source and drain regions of those formed in isolation regions (19) Field effect transistors are produced in one process step. Method according to Claim 1 or 2, characterized in that the emitter regions (29) of the bipolar transistors and the source (32) and drain regions (33) of the field effect transistors formed outside the isolation regions (16, 19) can be produced in one process step. Method according to one of Claims 1 to 3, characterized in that that the concentration of the impurity with the lower diffusion rate after introduction into the substrate (1) is higher than the concentration of the ι 971 0O ₁ 209847/1066 Contaminants with the greater diffusion rate. 5. The method according to any one of claims 1 to .4, characterized in that that arsenic and phosphorus are used as impurities. 209847/1066 FI 971 001 Blank page