GB1358612A - Monolithic semiconductor device - Google Patents

Monolithic semiconductor device

Info

Publication number
GB1358612A
GB1358612A GB1090072A GB1090072A GB1358612A GB 1358612 A GB1358612 A GB 1358612A GB 1090072 A GB1090072 A GB 1090072A GB 1090072 A GB1090072 A GB 1090072A GB 1358612 A GB1358612 A GB 1358612A
Authority
GB
United Kingdom
Prior art keywords
diffusion
regions
bipolar transistor
type
ohm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1090072A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1358612A publication Critical patent/GB1358612A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology
    • H01L21/8249Bipolar and MOS technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

1358612 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 9 March 1972 [28 April 1971] 10900/72 Heading H1K A monolithic semi-conductor device is made by introducing two donor (acceptor) impurities with different diffusion rates into one or more areas of a surface of a P(N)-type wafer then epitaxially depositing P(N)-type material over the surface and heating to form regions of N(P)- type extending to new surface by out-diffusion of the faster diffusing impurity, and finally introducing impurities from the surface to form a bipolar transistor within the or one of the thus formed regions and a field effect transistor outside the regions or in another of them. There are FETs in both positions in the Fig. 6 embodiment which is made on a 100 orientated 10-20 ohm cm. P-type silicon wafer into which the donors phosphorus and arsenic are introduced by capsule diffusion before deposition of a 2 ohm cm. P-type silicon layer. After out-diffusion is completed boron is diffused in through oxide masking to form the base and the source and drain regions of the bipolar transistor 16 and P channel FET 19 respectively, and then after remasking arsenic is diffused in to form the bipolar transistor emitter and the source and drain of the N channel FET. Finally the oxide is removed from the gate sites and replaced by a thinner layer covered with phosphosilicate glass to form a charge stabilized gate insulation and electrodes provided in conventional matter. Details are given of the diffusion and masking steps. Specification 1,306,817 is referred to.
GB1090072A 1971-04-28 1972-03-09 Monolithic semiconductor device Expired GB1358612A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13816171A 1971-04-28 1971-04-28

Publications (1)

Publication Number Publication Date
GB1358612A true GB1358612A (en) 1974-07-03

Family

ID=22480723

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1090072A Expired GB1358612A (en) 1971-04-28 1972-03-09 Monolithic semiconductor device

Country Status (12)

Country Link
JP (1) JPS5037507B1 (en)
AU (1) AU459156B2 (en)
CA (1) CA966231A (en)
CH (1) CH536029A (en)
DE (1) DE2219696C3 (en)
ES (2) ES402165A1 (en)
FR (1) FR2134360B1 (en)
GB (1) GB1358612A (en)
IT (1) IT947674B (en)
NL (1) NL7204804A (en)
SE (1) SE384949B (en)
ZA (1) ZA721782B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2608267A1 (en) * 1976-02-28 1977-09-08 Itt Ind Gmbh Deutsche METHOD OF MANUFACTURING A MONOLITHIC INTEGRATED CIRCUIT
JPS5851561A (en) * 1981-09-24 1983-03-26 Hitachi Ltd Semiconductor integrated circuit device
JPS58225663A (en) * 1982-06-23 1983-12-27 Toshiba Corp Manufacture of semiconductor device
JPS5955052A (en) * 1982-09-24 1984-03-29 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS59177960A (en) * 1983-03-28 1984-10-08 Hitachi Ltd Semiconductor device and manufacture thereof
IT1214808B (en) * 1984-12-20 1990-01-18 Ates Componenti Elettron TICO AND SEMICONDUCTOR PROCESS FOR THE FORMATION OF A BURIED LAYER AND OF A COLLECTOR REGION IN A MONOLI DEVICE
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
KR890004420B1 (en) * 1986-11-04 1989-11-03 삼성반도체통신 주식회사 Manufacturing method of bicmos device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293087A (en) * 1963-03-05 1966-12-20 Fairchild Camera Instr Co Method of making isolated epitaxial field-effect device
US3481801A (en) * 1966-10-10 1969-12-02 Frances Hugle Isolation technique for integrated circuits
US3479233A (en) * 1967-01-16 1969-11-18 Ibm Method for simultaneously forming a buried layer and surface connection in semiconductor devices
US3440503A (en) * 1967-05-31 1969-04-22 Westinghouse Electric Corp Integrated complementary mos-type transistor structure and method of making same
GB1280022A (en) * 1968-08-30 1972-07-05 Mullard Ltd Improvements in and relating to semiconductor devices

Also Published As

Publication number Publication date
SE384949B (en) 1976-05-24
ES402165A1 (en) 1975-03-16
AU4164272A (en) 1973-12-20
CH536029A (en) 1973-04-15
AU459156B2 (en) 1975-03-20
NL7204804A (en) 1972-10-31
ZA721782B (en) 1973-10-31
JPS5037507B1 (en) 1975-12-03
ES402164A1 (en) 1975-03-01
IT947674B (en) 1973-05-30
FR2134360A1 (en) 1972-12-08
CA966231A (en) 1975-04-15
FR2134360B1 (en) 1974-06-28
DE2219696B2 (en) 1978-04-06
DE2219696A1 (en) 1972-11-16
DE2219696C3 (en) 1982-02-18

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee