JPH03259528A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03259528A
JPH03259528A JP5831390A JP5831390A JPH03259528A JP H03259528 A JPH03259528 A JP H03259528A JP 5831390 A JP5831390 A JP 5831390A JP 5831390 A JP5831390 A JP 5831390A JP H03259528 A JPH03259528 A JP H03259528A
Authority
JP
Japan
Prior art keywords
resist
photoresist
substrate
si3n4 film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5831390A
Other languages
Japanese (ja)
Inventor
Hidetoshi Furukawa
秀利 古川
Toshiyuki Ueda
利之 上田
Yoshiro Oishi
芳郎 大石
Kunihiko Kanazawa
邦彦 金澤
Masahiro Nishiuma
西馬 正博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP5831390A priority Critical patent/JPH03259528A/en
Publication of JPH03259528A publication Critical patent/JPH03259528A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent dimensional spread at lower side, and form an excellent pattern on an Si3N4 film and an Si substrate, by stacking the Si3N4 film and a resist mask on the Si substrate, performing heat treatment after the surface is modified by exposure to plasma gas, and turning the resist aperture section into a curve type. CONSTITUTION:On a semi-insulative GaAs substrate 1, an Si3N4 film 2 and a photoresist mask 3 are stacked by a plasma CVD method. By plasma etching using CF4, an aperture is formed in the Si3N4 film 2, and the resist 3 (PMMA) is modified; the aperture section of the resist 3 is worked into a curve type by heat treatment at 170 deg.C in N2 for about 30 minutes; by wet etching, the GaAs substrate 1 in the aperture part of the resist 3 and the Si3N4 film 2 is scrapped off and covered with Ti 4. Since the mutual adhesion of the substrate 1, the Si3N4, and the PMMA resist is excellent, the permeation of etching liquid into the interface can be prevented, and accurate wet etching completely equal to an upper pattern can be realized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.

従来の技術 半導体基板上に、部分的に基板と連結した上層膜を形成
する方法として、従来、第2図(a)〜(C)の工程順
断面図で示すような工程が知られている。
BACKGROUND ART As a method for forming an upper layer film partially connected to a semiconductor substrate on a semiconductor substrate, the steps shown in the step-by-step cross-sectional views of FIGS. 2(a) to 2(C) are conventionally known. .

第2図(a)に示すように、半導体基板5上に部分的に
基板まで貫通する開孔部を持つフォトレジストパターン
6を形成し、上層部がフォトレジスト6の開孔部の端部
で切れることを防ぐため、第2図(b)に示すように、
前記フォトレジスト6の開孔部の断面形状を曲線状に加
工し、場合により、開孔部下に露出した半導体基板を、
エツチングにより表面処理した後、第2図(C)に示す
ように、前記の形状加工を施したフォトレジストパター
ン6の上から、導電体膜あるいは誘電体膜でなる上層7
を形成するというものがある。
As shown in FIG. 2(a), a photoresist pattern 6 having an opening that partially penetrates the substrate is formed on a semiconductor substrate 5, and the upper layer is formed at the end of the opening of the photoresist 6. To prevent it from breaking, as shown in Figure 2 (b),
The cross-sectional shape of the opening of the photoresist 6 is processed into a curved shape, and in some cases, the semiconductor substrate exposed under the opening is
After surface treatment by etching, as shown in FIG.
There is something called forming.

発明が解決しようとする課題 しかし、従来、第2図(b)のように7オトレジストパ
ターン6の開孔部断面形状を、熱処理等により加工した
場合、半導体基板5とフォトレジスト6との密着性が悪
いため、加工後の基板側の開孔部寸法へ゛が、加工前の
寸法Aよりも広がってしまうという課題が存在する。ま
た、同じく半導体基板5とフォトレジストパターン6の
密着性の悪さから、上層膜7を形成する前に、フォトレ
ジストパターン6をマスクとし、半導体基板5をウェッ
トエツチング処理した場合、開孔部から、半導体基板5
とフォトレジスト6の界面に、エツチング液が浸透して
しまい、正常なパターン加工ができないという課題が存
在した。
Problem to be Solved by the Invention However, conventionally, when the cross-sectional shape of the opening of the seven photoresist patterns 6 is processed by heat treatment or the like as shown in FIG. 2(b), the close contact between the semiconductor substrate 5 and the photoresist 6 is Because of the poor properties, there is a problem in that the dimension of the opening on the substrate side after processing becomes wider than the dimension A before processing. Similarly, due to the poor adhesion between the semiconductor substrate 5 and the photoresist pattern 6, if the semiconductor substrate 5 is subjected to wet etching using the photoresist pattern 6 as a mask before forming the upper layer film 7, the etching may occur from the opening. semiconductor substrate 5
There was a problem in that the etching solution penetrated into the interface between the photoresist 6 and the photoresist 6, making it impossible to perform normal pattern processing.

課題を解決するための手段 上記の課題を解決するために、本発明の製造方法では、
先ず半導体基板上にシリコン窒化膜を堆積し、このシリ
コン窒化膜上に、部分的に開孔部を持つフォトレジスト
パターンを形成する。次に、このフォトレジストの形成
された半導体基板を、プラズマガスにさらした後に加熱
処理することにより、フォトレジスト開孔部の断面形状
を曲線状に加工し、その上から7オトレジストの加工形
状に沿って、誘電体膜あるいは導電体膜を形成する。
Means for Solving the Problems In order to solve the above problems, in the manufacturing method of the present invention,
First, a silicon nitride film is deposited on a semiconductor substrate, and a photoresist pattern having partial openings is formed on the silicon nitride film. Next, the semiconductor substrate on which this photoresist has been formed is exposed to plasma gas and then heat-treated to process the cross-sectional shape of the photoresist opening into a curved shape. A dielectric film or a conductive film is formed along the line.

作用 上記の製造方法を用いた場合、フォトレジストパターン
と下層(シリコン窒化膜〉及び半導体基板と上層(シリ
コン窒化膜〉との密着性が、半導体基板上に直接フォト
レジストパターンを形成する場合より良くなるというこ
と、及びフォトレジストを、加熱処理する前に、プラズ
マガスにさらすことにより、フォトレジストの表面改質
が行われるということの相乗効果により、続く、加熱処
理に伴うフォトレジスト開孔部断面下側の寸法の広がり
が防止される。同様に、シリコン窒化膜とフォトレジス
ト、半導体基板の密着性が良いため、フォトレジストパ
ターンをマスクとし、下のシリコン窒化膜及び半導体基
板のエツチングを行った場合も、各層界面へのエツチン
グ液の浸透が防がれ、良好なパターン加工が実現できる
Effect When the above manufacturing method is used, the adhesion between the photoresist pattern and the lower layer (silicon nitride film) and between the semiconductor substrate and the upper layer (silicon nitride film) is better than when the photoresist pattern is formed directly on the semiconductor substrate. Due to the synergistic effect that the surface of the photoresist is modified by exposing it to plasma gas before heat treatment, the cross section of the photoresist opening accompanying the subsequent heat treatment is This prevents the bottom dimension from expanding. Similarly, since the silicon nitride film, photoresist, and semiconductor substrate have good adhesion, the underlying silicon nitride film and semiconductor substrate were etched using the photoresist pattern as a mask. In this case, the etching solution is prevented from penetrating into the interfaces of each layer, and good pattern processing can be achieved.

実施例 第1図(a)〜(e)は、本発明の一実施例を示す工程
順断面図で、この図にしたがい、半導体基板上に、誘電
体膜を挟み、部分的に基板とつながった導電体膜を形成
する工程を詳細に説明する。先ず、第1図(a)に示す
ように、半絶縁性GaAs基板1上に、ブラズ7CVD
(Chemical Vapour ロepositi
on)法により、シリコン窒化膜2を800A堆積する
。次に、第1図(b)に示すように、電子線描画用フォ
トレジストPMMA3によるパターン加工グを行う。次
に、RI E(Reactive Ion Etchi
ng)法により、CF4ガスによるプラズマで、露出し
ている部分のシリコン窒化膜2のエツチング及び、PM
MAレジスト3の改質を同時に行う。更に、窒素雰囲気
中で170℃、30分間の加熱処理を行うことにより、
第1図(C)に示すように、PMMAレジスト3の開孔
部の断面形状を曲線状に加工する。次に第1図(d)に
示すように、ウェットエツチングにより、レジスト3及
びシリコン窒化膜2の開孔部に露出した半絶縁性GaA
s基板1の表面を削る。次に、第1図(e)に示すよう
に、前記の形状加工を施したシリコン窒化膜2及びPM
MAレジスト3の形成された半絶縁性GaAs基板1の
上から、金属チタン層4を形成する。
Embodiment FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention in the order of steps. The process of forming the conductive film will be described in detail. First, as shown in FIG. 1(a), BLAZ 7CVD
(Chemical Vapor
A silicon nitride film 2 is deposited to a thickness of 800 Å using the on method. Next, as shown in FIG. 1(b), pattern processing is performed using an electron beam drawing photoresist PMMA3. Next, RI E (Reactive Ion Etchi)
ng) method, the exposed portion of the silicon nitride film 2 is etched with plasma using CF4 gas, and the PM
The MA resist 3 is modified at the same time. Furthermore, by performing heat treatment at 170°C for 30 minutes in a nitrogen atmosphere,
As shown in FIG. 1(C), the cross-sectional shape of the opening of the PMMA resist 3 is processed into a curved shape. Next, as shown in FIG. 1(d), the semi-insulating GaA exposed in the openings of the resist 3 and silicon nitride film 2 is etched by wet etching.
The surface of the s-substrate 1 is scraped. Next, as shown in FIG. 1(e), the silicon nitride film 2 and PM
A metal titanium layer 4 is formed on the semi-insulating GaAs substrate 1 on which the MA resist 3 is formed.

なお、本実施例では、基板として半絶縁性GaAs基板
、フォトレジストの下地誘電体膜として、プラズマCV
D法によるシリコン窒化膜を用いたが、基板はこれに限
らず、また、シリコン窒化膜の厚みや堆積法もこれに限
ったものではない。
In this example, the substrate is a semi-insulating GaAs substrate, and the underlying dielectric film of the photoresist is plasma CVD.
Although a silicon nitride film formed by the D method is used, the substrate is not limited to this, and the thickness of the silicon nitride film and the deposition method are also not limited to this.

さらに、形状加工を施すフォトレジストも、本実施例の
電子線直接描画用PMMAに限ったものでない。本実施
例ではフォトレジストの形状加工のための表面改質と、
下地のシリコン窒化膜の部分的エツチングとを、RIE
法により、CF4ガスのプラズマで同時に行ったが、エ
ツチング方法及びエツチングガスはこれに限ったもので
なく、また、両者を個別に行っても良い。
Further, the photoresist to be shaped is not limited to the electron beam direct writing PMMA of this embodiment. In this example, surface modification for shape processing of photoresist,
RIE partially etches the underlying silicon nitride film.
The etching method and etching gas are not limited to this, and both may be performed separately.

本実施例では、フォトレジストの形状加工のための熱処
理を窒素雰囲気中で170℃、30分間行ったが、雰囲
気はこれに限らず、又処理温度及び時間は、レジストの
種類や得たい曲線形状により変化する。本実施例では、
開孔部下のシリコン窒化膜及び更にその下の半導体基板
のエツチングを行ったが、フォトレジスト開孔部下地の
表面処理は、これに限ったものではない。本実施例では
、上層として金属チタン膜を用いたが、他の導電体ある
いは誘電体でも良く、本実施例の物質に限ったものでは
ない。
In this example, the heat treatment for shaping the photoresist was performed at 170°C for 30 minutes in a nitrogen atmosphere, but the atmosphere is not limited to this, and the processing temperature and time may vary depending on the type of resist and the desired curve shape. Varies depending on In this example,
Although the silicon nitride film under the opening and the semiconductor substrate further below it were etched, the surface treatment under the photoresist opening is not limited to this. In this example, a metallic titanium film is used as the upper layer, but other conductive or dielectric materials may be used, and the material is not limited to the material used in this example.

発明の効果 以上のように本発明は、先ず半導体基板上に、下地とし
てシリコン窒化膜の堆積を行い、この誘電体膜上に部分
的に開孔部を持つフォトレジストパターンを形威し、そ
のレジストパターンをプラズマガスにさらして表面改質
した後に加熱処理を施すことにより、開孔部下側の寸法
を広げることなく、フォトレジスト開孔部断面形状を曲
線状に加工することを可能とし、シリコン窒化膜とフォ
トレジスト及び半導体基板との密着性の良さから、ウェ
ットエツチングを行う場合に、エツチング液の界面への
浸透を防ぎ、上部パターン通りの正常なウェットエツチ
ングを可能とするもので、その実用的効果は大なるもの
がある。
Effects of the Invention As described above, the present invention first deposits a silicon nitride film as a base on a semiconductor substrate, forms a photoresist pattern with partial openings on this dielectric film, and By exposing the resist pattern to plasma gas to modify its surface and then applying heat treatment, it is possible to process the cross-sectional shape of the photoresist opening into a curved shape without increasing the dimension below the opening, and it is possible to process the cross-sectional shape of the photoresist opening into a curved shape. Because of the good adhesion between the nitride film, photoresist, and semiconductor substrate, it prevents the etching solution from penetrating the interface during wet etching, allowing normal wet etching to follow the upper pattern. The effects are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体装置の製造方法を説明するため
の工程順断面図、第2図は従来の製造方法を説明するた
めの工程順断面図である。 1・・・・・・半絶縁性GaAs基板、2・・・・・・
シリコン窒化膜、3・・・・・・フォトレジスト(PM
MA)、41.。 ・・・チタン、5・・・・・・半導体基板、6・・・・
・・フォトレジスト、7・・・・・・誘電体膜あるいは
導電体膜。
FIG. 1 is a step-by-step sectional view for explaining a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a step-by-step sectional view for explaining a conventional manufacturing method. 1... Semi-insulating GaAs substrate, 2...
Silicon nitride film, 3... Photoresist (PM
MA), 41. . ...Titanium, 5...Semiconductor substrate, 6...
...Photoresist, 7...Dielectric film or conductive film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に誘電体膜を堆積する工程と、前記誘電体
膜上に、部分的に開孔部を持つフォトレジストパターン
を形成する工程と、前記フォトレジストパターンをプラ
ズマガスにさらし、続いて、加熱処理を行い、前記フォ
トレジスト開孔部の断面形状を、曲線状に加工する工程
と、前記フォトレジストの加工形状に沿って、導電体あ
るいは誘電体を形成する工程とからなる半導体装置の製
造方法。
Depositing a dielectric film on a semiconductor substrate, forming a photoresist pattern partially having openings on the dielectric film, exposing the photoresist pattern to plasma gas, and then Manufacturing a semiconductor device comprising the steps of performing heat treatment to process the cross-sectional shape of the photoresist opening into a curved shape, and forming a conductor or dielectric material along the processed shape of the photoresist. Method.
JP5831390A 1990-03-09 1990-03-09 Manufacture of semiconductor device Pending JPH03259528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5831390A JPH03259528A (en) 1990-03-09 1990-03-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5831390A JPH03259528A (en) 1990-03-09 1990-03-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03259528A true JPH03259528A (en) 1991-11-19

Family

ID=13080766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5831390A Pending JPH03259528A (en) 1990-03-09 1990-03-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03259528A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372677A (en) * 1991-12-18 1994-12-13 Kawasaki Steel Corporation Method of manufacturing semiconductor devices
KR100416694B1 (en) * 1995-12-16 2004-05-27 주식회사 하이닉스반도체 A method for wet etching of Si3N4 in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372677A (en) * 1991-12-18 1994-12-13 Kawasaki Steel Corporation Method of manufacturing semiconductor devices
KR100416694B1 (en) * 1995-12-16 2004-05-27 주식회사 하이닉스반도체 A method for wet etching of Si3N4 in semiconductor device

Similar Documents

Publication Publication Date Title
US10381232B2 (en) Techniques for manipulating patterned features using ions
DE69712080T2 (en) MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE
US5126288A (en) Fine processing method using oblique metal deposition
EP0076215B1 (en) Lift-off shadow mask
US4757033A (en) Semiconductor device manufacturing by sequential ion and wet etchings prior to lift-off metallization
US5190892A (en) Method for forming pattern using lift-off
US3767492A (en) Semiconductor masking
US6133145A (en) Method to increase the etch rate selectivity between metal and photoresist via use of a plasma treatment
JPH03259528A (en) Manufacture of semiconductor device
JPH0117253B2 (en)
KR960013140B1 (en) Fabricating method of semiconductor device
JPH0282535A (en) Manufacture of electrode for transistor gate
JPH0464459B2 (en)
KR0131986B1 (en) Fabricating method of micropattern
JPH0249426A (en) Pattern formation
JPH03297150A (en) Manufacture of semiconductor device
JPH03227528A (en) Manufacture of semiconductor device
JPS62200732A (en) Manufacture of semiconductor device
JPH03268332A (en) Manufacture of semiconductor device
JPH0290615A (en) Manufacture of semiconductor device
JPS5893330A (en) Manufacture of semiconductor device
JPS61224425A (en) Pattern formation of semiconductor device
JPH0410629A (en) Manufacture of semiconductor device
JPH0364933A (en) Manufacture of semiconductor device
JPH01283971A (en) Formation of electrode pattern