JPS61224425A - Pattern formation of semiconductor device - Google Patents
Pattern formation of semiconductor deviceInfo
- Publication number
- JPS61224425A JPS61224425A JP6591685A JP6591685A JPS61224425A JP S61224425 A JPS61224425 A JP S61224425A JP 6591685 A JP6591685 A JP 6591685A JP 6591685 A JP6591685 A JP 6591685A JP S61224425 A JPS61224425 A JP S61224425A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- pattern
- semiconductor substrate
- photoresist layer
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置のパターン形成方法に係り、特に半
導体装置の配線用パターンの形成にリフトオフ法を用い
たパターン形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pattern forming method for a semiconductor device, and particularly to a pattern forming method using a lift-off method to form a wiring pattern for a semiconductor device.
半導体集積回路などの、半導体装置において、集積度、
電気的特性等の向上のために素子の寸法の微細化が活発
に進められており、すでにそのパターン寸法はサブミク
ロンの領域に達している。このようなパターン形成に際
しては、マスク上のパターンを忠実に半導体基板に転写
することが緊要であり、ウェットエツチング法、ドライ
エツチング法、およびリフトオフ法などが広くパターン
形成に利用されている。In semiconductor devices such as semiconductor integrated circuits, the degree of integration,
In order to improve electrical characteristics and the like, miniaturization of device dimensions is actively underway, and pattern dimensions have already reached the submicron range. In forming such a pattern, it is essential to faithfully transfer the pattern on the mask onto the semiconductor substrate, and wet etching, dry etching, lift-off, and the like are widely used for pattern formation.
上記ウェットエツチング法は、サイドエツチング量が多
く、また、サイドエツチング量を再現性良く制御するこ
とが困難であるため、パターンを精度良く形成すること
に問題があり、また、被エツチング材料とフォトレジス
ト間の密着不良が原因で生ずるエツチング溶液の被エツ
チング材料とフォトレジスト界面への異常な浸み込みが
しばしば起きる等の欠点がある。また、ドライエツチン
グ法は、ウェットエツチング法と比較してサイドエツチ
ング量が少いこと、および被エツチング材料とフォトレ
ジスト間の密着性があまり問題とならない等の利点を有
するが、エツチング時の温度上昇によりフォトレジスト
が硬化し、あるいはドライエツチング時に半導体に損傷
を与える等の問題点がある。さらにtt、、フォトレジ
ストが垂直に切れていないときにはドライエツチング中
にレジスト寸法が膜減りによって次第に縮小するという
問題点もある。このように上記両エツチング法はともに
サブミクロンのパターン形成に必らずしも有効な手段と
はいえない。The above wet etching method involves a large amount of side etching, and it is difficult to control the amount of side etching with good reproducibility, so there is a problem in forming patterns with high precision. There are drawbacks such as abnormal penetration of the etching solution into the interface between the material to be etched and the photoresist, which is often caused by poor adhesion between the etching material and the photoresist. Additionally, the dry etching method has advantages over the wet etching method, such as a smaller amount of side etching and less problems with adhesion between the material to be etched and the photoresist. This causes problems such as hardening of the photoresist or damage to the semiconductor during dry etching. Furthermore, when the photoresist is not cut vertically, there is a problem that the resist dimension gradually decreases due to film thinning during dry etching. In this way, both of the above etching methods cannot necessarily be said to be effective means for forming submicron patterns.
上記に対し、リフトオフ法はフォトレジストの開ロバタ
ーンを忠実に金属パターンとして半導体基板上に転写で
きるという長所があるために、サブミクロン以下の金属
パターン形成に際して広く利用されている。これは第2
図に示すように、半導体基板100上のフォトレジスト
層101をパターニングして単に金属層102を被着し
ただけでは、フォトレジスト層上に被着した金属層部1
02aと半導体基板上に被着した金属層部102bが矢
印の先端で示す部分で連なってしまい、フォトレジスト
層を除去することによってこの上面に被着している金属
層部102aのみを除去して行なうリフトオフが達成で
きない。リフトオフを施すには両金属層102a。In contrast to the above, the lift-off method has the advantage of being able to faithfully transfer an open pattern of a photoresist as a metal pattern onto a semiconductor substrate, and is therefore widely used in forming sub-micron metal patterns. This is the second
As shown in the figure, if the photoresist layer 101 on the semiconductor substrate 100 is simply patterned and the metal layer 102 is simply deposited, the metal layer portion 1 deposited on the photoresist layer 1
02a and the metal layer portion 102b deposited on the semiconductor substrate are connected at the part indicated by the tip of the arrow, and by removing the photoresist layer, only the metal layer portion 102a deposited on the top surface is removed. Liftoff cannot be achieved. Both metal layers 102a are subjected to lift-off.
102bが空間的に分離されている必要がある。102b must be spatially separated.
そこで一般には第3図に示すように、半導体基板100
とフォトレジスト層101の間にリフトオフ用のスペー
サ層103を設け、フォトレジスト層101に開口を施
したのち、スペーサ層103をエツチングする際のサイ
ドエツチングを利用し、フォトレジスト層101上の金
属層102aと半導体基板100上の金属層102bと
の接触を防止している。Therefore, generally, as shown in FIG.
A spacer layer 103 for lift-off is provided between the photoresist layer 101 and the photoresist layer 101, and after making an opening in the photoresist layer 101, the metal layer on the photoresist layer 101 is etched using side etching when etching the spacer layer 103. This prevents contact between the metal layer 102a and the metal layer 102b on the semiconductor substrate 100.
上記従来のりフトオフ法ではリフトオフ後にスヘーサ層
103が半導体基板100上に残留してしまうため、ス
ペーサ層の種類や厚さによっては素子の電気的特性、ま
たは後工程へ悪影響を及ぼすことがあるとともに、前記
スペーサ層のサイドエッチ ゛ング量の制御が難かし
く、半導体装置の製造において歩留りを低下させる要因
になるという欠点がある。In the conventional lift-off method described above, the spacer layer 103 remains on the semiconductor substrate 100 after lift-off, so depending on the type and thickness of the spacer layer, it may adversely affect the electrical characteristics of the device or post-processing. There is a drawback that it is difficult to control the side etching amount of the spacer layer, which causes a decrease in yield in the manufacture of semiconductor devices.
一
本発明は上記の欠点を除去するもので、半導体基板上に
微細なパターンを形成するりフトオフ法を改良する。One aspect of the present invention is to eliminate the above-mentioned drawbacks and improve the lift-off method for forming fine patterns on a semiconductor substrate.
本発明の半導体装置のパターン形成方法は、半導体基板
上に、ここに配設予定の金属層の層厚よりも厚く薄膜を
形成し、ついでフォトレジスト層を全面に被着したのち
これに前記薄膜の幅よりも細い開孔を形成し、前記フォ
トレジスト層をマスクにして薄膜を除去したのち金属層
を形成し、ついでフォトレジスト層上の金属層を該フォ
トレジスト層とともに除去して薄膜の除去された位置に
金属のパターンを形成することを特徴とするものである
。In the method for forming a pattern of a semiconductor device of the present invention, a thin film is formed on a semiconductor substrate to be thicker than a metal layer to be provided thereon, and then a photoresist layer is deposited on the entire surface, and then the thin film is coated on the semiconductor substrate. forming an opening narrower than the width of the photoresist layer, removing the thin film using the photoresist layer as a mask, forming a metal layer, and then removing the metal layer on the photoresist layer together with the photoresist layer to remove the thin film. The feature is that a metal pattern is formed at the location where the metal is placed.
以下1本発明の一つの実施例を図面を参照して説明する
。An embodiment of the present invention will be described below with reference to the drawings.
一実施例のパターン形成方法を第1図(a)〜(e)に
工程順に示す。図中、従来と変わらない部分には同じ符
号をつけて示し、説明を省略する。A pattern forming method according to an embodiment is shown in FIGS. 1(a) to 1(e) in order of steps. In the figure, parts that are the same as in the prior art are designated by the same reference numerals, and explanations thereof will be omitted.
半導体基板100上に例えば二酸化シリコンの薄膜1を
被着する(図a)。この薄膜は、のちに形成される配線
または電極用のパターンの金属層よすも厚く形成する。A thin film 1 of silicon dioxide, for example, is deposited on a semiconductor substrate 100 (FIG. a). This thin film is formed to be thicker than the metal layer of the wiring or electrode pattern that will be formed later.
次に、半導体基板100上に形成が予定される金属層の
パターンの位置に一致させ、かつその幅よりもやや広く
薄膜パターンlaを残すようにウェットエツチングを施
したのち、全面にフォトレジスト層2を被着する(図b
)。Next, wet etching is performed so as to match the position of the metal layer pattern to be formed on the semiconductor substrate 100 and leave a thin film pattern la slightly wider than the width thereof, and then a photoresist layer 2 is applied to the entire surface. (Figure b)
).
次に、薄膜パターン形成上のフォトレジスト層2に上記
薄膜パターン1aの幅よりも細い所定の開孔2aを設け
、薄膜パターン1aを完全に除去する(図c)、このよ
うにして形成された断面形状が凸型の空洞2bは、半導
体基板100と接する部分で広く、上部で狭いもので、
リフトオフに適した形状である。Next, a predetermined opening 2a that is narrower than the width of the thin film pattern 1a is provided in the photoresist layer 2 on which the thin film pattern is formed, and the thin film pattern 1a is completely removed (Figure c). The cavity 2b having a convex cross-sectional shape is wide at the part in contact with the semiconductor substrate 100 and narrow at the upper part.
The shape is suitable for lift-off.
次に、全面に金属層3を例えば蒸着によって被着する。A metal layer 3 is then applied over the entire surface, for example by vapor deposition.
この金属層3はフォトレジスト層上の金属層3bと、フ
ォトレジスト層の開孔2aによってこの下方の半導体基
板100上に被着したパターン状金属層2aになる(1
!Id)。This metal layer 3 becomes a patterned metal layer 2a deposited on the semiconductor substrate 100 below by means of a metal layer 3b on the photoresist layer and an opening 2a in the photoresist layer (1
! Id).
次に、フォトレジスト層2を除去することによってこの
上に被着されているフォトレジスト層上の金属1iJ3
bも共に除去され、半導体基板上にはここに被着された
所定パターン形状の金属層3aが得られる(図e)。Next, by removing the photoresist layer 2, the metal 1iJ3 on the photoresist layer deposited thereon is removed.
b is also removed, and a metal layer 3a having a predetermined pattern is deposited on the semiconductor substrate (FIG. e).
上記実施例は半導体基板にパターニングを行なうものを
示したが、半導体基板上の窒化シリコンなどの電気絶縁
層、または他の配線パターンがすでに形成されている場
合についても全く同様に有効である。また、薄膜として
SiO2膜を例示したが、他の電気絶縁層、または金属
膜等でもよいことはいうまでもない。Although the above embodiments have been described in which patterning is performed on a semiconductor substrate, the present invention is equally effective in cases where an electrical insulating layer such as silicon nitride or other wiring pattern has already been formed on the semiconductor substrate. Further, although the SiO2 film is exemplified as the thin film, it goes without saying that other electrical insulating layers, metal films, etc. may also be used.
以上述べたように本発明によれば、選択的に形成された
薄膜が金属層を蒸着する前に除去されているので、従来
のように薄膜が半導体基板上にあるために起きる素子の
電気的特性、製造工程への悪影響を防止できる顕著な利
点がある。また、最初に所定の寸法の薄膜を形成しりフ
トオフ時には薄膜を完全に除去しているので、薄膜とフ
ォトレジストとの密着不良に基づく液の浸み込みによっ
て起きるサイドエツチング量の不安定性を解決すること
かできる利点もある。このように、本発明によるリフト
オフ法ではサブミクロンのパターンの形成が安定に再現
性良くできるので、半導体装置の製造歩留りを大幅に向
上させることができる。As described above, according to the present invention, the selectively formed thin film is removed before the metal layer is deposited, so that the electrical problems of the device, which occur when the thin film is on the semiconductor substrate as in the conventional method, are removed. It has the remarkable advantage of preventing adverse effects on properties and manufacturing processes. In addition, since a thin film of predetermined dimensions is first formed and the thin film is completely removed during lift-off, it solves the instability of the amount of side etching caused by liquid seepage due to poor adhesion between the thin film and photoresist. There is also the advantage of being able to do so. As described above, with the lift-off method according to the present invention, submicron patterns can be formed stably and with good reproducibility, so that the manufacturing yield of semiconductor devices can be significantly improved.
第1図(a)〜(e)は本発明の1実施例のパターン形
成方法を工程順に示すいずれも断面図、第2図および第
3図はいずれも夫々が従来のりフトオフ法を説明するた
めの断面図である。
1−−−−一 薄膜FIGS. 1(a) to (e) are cross-sectional views showing a pattern forming method according to an embodiment of the present invention in the order of steps, and FIGS. 2 and 3 are for explaining the conventional lift-off method. FIG. 1-----1 Thin film
Claims (1)
レジスト層を全面に被着したのちこれに前記薄膜の幅よ
りも細い開孔を形成し、前記フォトレジスト層をマスク
にして薄膜を除去したのち金属層を形成し、ついでフォ
トレジスト層上の金属層を該フォトレジスト層とともに
除去して前記薄膜の除去された位置に金属のパターンを
形成することを特徴とする半導体装置のパターン形成方
法。A thin film was selectively formed on a semiconductor substrate, a photoresist layer was then deposited on the entire surface, an opening was formed therein that was narrower than the width of the thin film, and the thin film was removed using the photoresist layer as a mask. 1. A method for forming a pattern of a semiconductor device, comprising: later forming a metal layer, then removing the metal layer on the photoresist layer together with the photoresist layer, and forming a metal pattern at the location where the thin film has been removed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6591685A JPS61224425A (en) | 1985-03-29 | 1985-03-29 | Pattern formation of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6591685A JPS61224425A (en) | 1985-03-29 | 1985-03-29 | Pattern formation of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61224425A true JPS61224425A (en) | 1986-10-06 |
Family
ID=13300772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6591685A Pending JPS61224425A (en) | 1985-03-29 | 1985-03-29 | Pattern formation of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61224425A (en) |
-
1985
- 1985-03-29 JP JP6591685A patent/JPS61224425A/en active Pending
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