KR940008117A - 엠이에스에프이티 (mesfet)의 티(t) 게이트 제조방법 - Google Patents

엠이에스에프이티 (mesfet)의 티(t) 게이트 제조방법 Download PDF

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KR940008117A
KR940008117A KR1019920015907A KR920015907A KR940008117A KR 940008117 A KR940008117 A KR 940008117A KR 1019920015907 A KR1019920015907 A KR 1019920015907A KR 920015907 A KR920015907 A KR 920015907A KR 940008117 A KR940008117 A KR 940008117A
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photoresist
oxide film
oxide
etching
gate
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KR1019920015907A
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KR950005489B1 (ko
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이원상
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이헌조
주식회사 금성사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045—Field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 단층의 포토레지스터와 산화막층을 이용하여 T게이트를 제조할 수 있도록 함으로서 생산공정이 단순하므로 생산성을 향상시킬 수 있고 전자비임 리소그래피와 같은 고가의 장비를 사용하지 않아도 되므로 생산 원가를 절감할 수 있게 한것에 목적을 두것이다.
상기와 같은 목적을 가진 본 발명은 GaAs웨이퍼(1)위에 포토레지스터(2)를 D에칭시키는 포토레지스터 에칭공정과, 상기 포토레지스터위에 산화막 절연층을 디포지션(deposition)하는 산화막 절연층 디포지션공정과, 상기 산화막과 기판의 중앙을 식각시키는 식각공정과, 상기 식각된 기판의 위치와 산화막 위에 금속전극을 증착하는 금속전극증착공정과, 상기 포토레지스터와 산화막층을 리프트오프공정을 통하여 T게이트를 제조함을 특징으로 한다.

Description

엠이에스에프이티(MESFET)의 티(T) 게이트 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도의 (가)내지(마)는 본 발명의 MESFET의 T게이트 제조공정도.

Claims (3)

  1. GaAs웨이퍼위에 포토레지스터(2)를 형성한후 하부가 드러나게 함과 함꼐 비수직적 형태로 에칭하는 포토레지스터에칭공정과, 상기 포토레지스터위에 산화막충(3)을 디포지션하여 우물형태의 형틀을 형성하는 산화막 디포지션공정과, 상기 산화막층(3)의 형틀하부만 에칭되도록 하고 하측의 GaAs웨이퍼를 리세스에칭시키는 산화막층과 GaAs웨이퍼에칭공정과. 상기 산화막층(3)과 형태내부에 게이트금속(4)을 증착시키는 게이트금속증착공정과, 상기 포토레지스터(2)와 산화막층(3)을 리프트오프시키는 리프트오트공정으로 제조함을 특징으로 하는 MESFET의 T게이트 제조방법.
  2. 제1항에 있어서, 산화막 디포지션공정을 PECVD법으로 형성하되 포토레지스터(2)가 제거된 부분과 포토레지스터(2)가 남아 있는 부분의 산화막 두꼐를 다르게 형성하여 제조함을 특징으로 하는 MESFET의 T게이트 제조방법.
  3. 제1항에 있어서, 게이트금속 중착공정은, 게이트금속이 T자 형태나 버섯형태로 형성되도록 제조함을 특징으로 하는 MESFET의 T게이트 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920015907A 1992-09-02 1992-09-02 엠이에스에프이티(mesfet)의 티(t) 게이트 제조방법 KR950005489B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920015907A KR950005489B1 (ko) 1992-09-02 1992-09-02 엠이에스에프이티(mesfet)의 티(t) 게이트 제조방법

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KR1019920015907A KR950005489B1 (ko) 1992-09-02 1992-09-02 엠이에스에프이티(mesfet)의 티(t) 게이트 제조방법

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KR940008117A true KR940008117A (ko) 1994-04-28
KR950005489B1 KR950005489B1 (ko) 1995-05-24

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KR100636597B1 (ko) 2005-12-07 2006-10-23 한국전자통신연구원 티형 게이트의 제조 방법

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