JPH07161735A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To provide a FET having a recess structure in which the gate-recess distance is well controlled. CONSTITUTION:A gate opening pattern and a gate-recess distance are formed simultaneously in a first resist pattern 6, an etching distance is made equal to the distance formed and determined by the first resist pattern 6 since a second resist pattern 7 becomes a stopper layer during the etching of an insulation film thereby the gate-recess distance of a FET having a recess structure is well controlled.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor manufacturing method, in particular,
The present invention relates to a method for manufacturing a field effect transistor having a recess structure.

[0002]

2. Description of the Related Art FIG. 19 is a process sectional view showing a method for manufacturing a conventional field effect transistor (hereinafter referred to as FET) having a two-step recess structure disclosed in Japanese Patent Laid-Open No. 4-137737. . As shown in FIG. 19A, after forming the source electrode 3 and the drain electrode 4 on the semiconductor substrate 1 having the active layer 2, the insulating film 5 is deposited. Next, as shown in FIG. 19B, a resist pattern 6 is formed, and as shown in FIG. 19C, a resist pattern 7 having a gate opening is formed on the insulating film pattern. Next, as shown in FIG. 19D, the insulating film 5 is anisotropically etched using the resist 7 as a mask. Next, in FIG.
As shown in (e), recess etching of the active layer 2 is performed using the resist 7 and the insulating film 5 as a mask. Next, in FIG.
As shown in (f), the insulating film 5 is completely removed by wet etching. Next, as shown in FIG.
The second-stage recess etching is performed using only the resist 6 as a mask. Next, as shown in FIG. 19H, the gate electrode 8 is vapor-deposited. Finally, as shown in FIG. 19I, lift-off is performed to form an FET having a two-step recess.

[0003]

[Problem to be Solved by the Invention] F having a recess structure
Since the conventional ET manufacturing method has the above-described structure, it is difficult to control the distance (L _gsr and L _gdr ) between the end of the recess and the end of the gate electrode in FIG. It was That is, for example, in the case of manufacturing a high-power FET in which the breakdown voltage is an important parameter, considering that the alignment accuracy of the stepper exposure device is about 0.1 μm, 3
There is a drawback that the breakdown voltage of V or more is changed. In order to suppress the increase in the source resistance, the distance between the recess edge on the source electrode side and the gate edge (L _{gsr in} FIG. 19) is set to the distance between the recess edge on the drain electrode side and the gate electrode edge (L in FIG. 19).
Similar problems occur when a gate structure having a structure smaller than _gdr ) (hereinafter referred to as an offset gate structure) is adopted. In order to form this offset gate structure, the technique disclosed in Japanese Patent Laid-Open No. 4-196542 uses a Ti oblique deposition process and a process of removing the resist and the insulating film of the semiconductor active layer. However, it is difficult to control the insulating film removal dimension to 0.1 μm or less, and it is the same that variations in withstand voltage and source resistance occur.

In order to solve the problem that the dimension of the insulating film removing step cannot be controlled, Japanese Unexamined Patent Publication No. 4-196542 uses a step of forming sidewalls on the source electrode and the drain electrode. However, even with this method, the controllability of the distances L _gsr and L _gdr between the gate _{recesses depends on} the alignment accuracy of the stepper exposure device, and does not reduce variations in withstand voltage and source resistance. The maximum thickness of the sidewall is about 0.5 μm, and the drain electrode and the recess edge are, for example, 1 μm or less.
There is also a problem in that the breakdown voltage cannot be set to more than μm and the breakdown voltage is reduced.

The object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a method for manufacturing a field effect transistor capable of controlling the distance between the gate electrode end and the recess end.

[0006]

According to the present invention, in a method of manufacturing a field effect transistor having a recess structure of one or more steps, a step of forming a source electrode and a drain electrode on a semiconductor active layer, and the source electrode and the drain. Forming an insulating film on the electrodes and the semiconductor active layer; forming a gate electrode opening and a recess structure on the insulating film at the same time on a first resist; and using the first resist as a mask, the insulating film Etching, a step of forming an opening pattern on the second resist to expose only the gate opening pattern on the pattern, a step of etching the insulating film to expose the semiconductor active layer,
Etching the semiconductor active layer in one or more steps using the first resist and the second resist as a mask, and forming a gate electrode by lift-off using the first resist and the second resist as a mask And are included.

[0007]

(Embodiment 1) A first embodiment of the present invention will be described with reference to process sectional views. 1 to 10 are sectional views of the manufacturing process of the present invention.

After forming the source electrode 3 and the drain electrode 4 on the semiconductor substrate 1 having the active layer 2 as shown in FIG. 1, an insulating film 5 is formed on the front surface as shown in FIG.

Next, as shown in FIG. 3, the gate opening size L
_The resist pattern 6 having _g and the inter-gate recess distances L _gdr and L _gsr is formed.

Next, as shown in FIG. 4, after dry etching the insulating film 5 using the resist pattern 6 as a mask,
As shown in FIG. 5, a second resist pattern 7 is formed to open only the gate electrode portion and cover the source electrode 3 and the drain electrode 4.

Next, as shown in FIG. 6, recess etching of the active layer 2 is performed using the insulating film 5 and the second resist pattern 7 as a mask. This etching amount is the etching depth of the final gate recess embedding depth.

Next, as shown in FIG. 7, the insulating film 5 is etched by wet etching using the first resist pattern 6 and the second resist pattern 7 as masks. At this time, since the second resist pattern 7 serves as a stopper layer when the insulating film 5 is etched, the distance L _gsr between the gate electrode and the recess edge is set by setting the etching distance to the distance defined by the first resist pattern 6. And L _gdr can be determined with good controllability.

Next, as shown in FIG. 8, the active layer 2 is anisotropically etched by using the second resist pattern as a mask.
Is etched to form a wide recess structure.

Finally, as shown in FIG. 9, after the gate electrode metal 8 is entirely vapor-deposited, as shown in FIG. 10, the first resist 6 and the second resist 7 are formed by the lift-off method.
Is entirely removed to form a gate electrode 8 to complete a FET having a two-step wide recess structure and an offset gate structure.

(Embodiment 2) FIGS. 11 to 18 are sectional views showing a manufacturing process of a second embodiment. 11 to 14 are similar to the process of FIG. However, the first resist 6 is set to 2000
The second resist pattern 7 is set to about angstrom.
It is different from the first embodiment that a resist pattern having a T-shaped gate structure is formed by inversely tapering the opening of the above.

As shown in FIG. 15, the insulating film 5 is etched using the first resist 6 and the second resist 7 as masks. At this time, determining the distance between the recesses of the gate electrode is the same as in the first embodiment.

Then, as shown in FIG. 16, the active layer 2 is etched using the second resist 7 as a mask to form a wide recess structure.

Next, as shown in FIG. 17, a gate electrode metal 8 is vapor-deposited on the entire surface.

Finally, as shown in FIG. 18, the first resist 6 and the second resist 7 are removed by a lift-off process to wide recess structure and offset T-type gate structure FE.
Complete T.

[0020]

According to the present invention, in a method of manufacturing a field effect transistor having a recess structure of one or more steps, a step of forming a source electrode and a drain electrode on a semiconductor active layer, and the source electrode, drain electrode and semiconductor active layer A step of forming an insulating film thereon, a step of simultaneously patterning a gate electrode opening and a recess structure on the first resist on the same insulating film, and a step of etching the insulating film using the first resist as a mask Forming an opening pattern on the second resist to expose only the gate opening pattern on the pattern, etching the oxide film to expose the semiconductor active layer, the first resist and the first resist, A step of etching the semiconductor active layer in one or more steps using the second resist as a mask, and the first resist and the second resist By lift-off to disk to and forming a gate electrode, it is possible to control the distance between the gate electrode end and the recess end.

In particular, an offset gate structure having different distances to the gate electrode end, the source electrode side recess end, and the drain electrode side recess end also causes instability of the alignment accuracy of the stepper exposure device and the side etching amount of the insulating film. Not affected, the distance L _gdr between the gate _{recesses is} 0.05 μm or less,
L _gsr controllability can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process of the first embodiment of the present invention.

FIG. 5 is a sectional view of a manufacturing process of the first embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process of the first embodiment of the present invention.

FIG. 7 is a sectional view of a manufacturing process according to the first embodiment of the present invention.

FIG. 8 is a manufacturing step sectional view of a first embodiment of the present invention.

FIG. 9 is a sectional view of a manufacturing process in the first embodiment of the present invention.

FIG. 10 is a sectional view of a manufacturing process according to the first embodiment of the present invention.

FIG. 11 is a manufacturing step sectional view of a second embodiment of the present invention.

FIG. 12 is a manufacturing step sectional view of a second embodiment of the present invention.

FIG. 13 is a sectional view of a manufacturing process according to the second embodiment of the present invention.

FIG. 14 is a manufacturing step sectional view of a second embodiment of the present invention.

FIG. 15 is a manufacturing step sectional view of a second embodiment of the present invention.

FIG. 16 is a sectional view of a manufacturing process according to the second embodiment of the present invention.

FIG. 17 is a sectional view of a manufacturing process according to the second embodiment of the present invention.

FIG. 18 is a sectional view of a manufacturing process according to the second embodiment of the present invention.

FIG. 19 is a sectional view of a conventional manufacturing process.

[Explanation of symbols]

1 semiconductor substrate 2 active layer 3 source electrode 4 drain electrode 5 insulating film 6 first resist 7 second resist L _gsr gate electrode / source electrode side recess edge distance L _gdr gate electrode / drain electrode side recess edge distance L _g gate Long

Claims (3)

[Claims] 1. A method of manufacturing a field effect transistor having a recess structure of one or more steps, comprising: forming a source electrode and a drain electrode on a semiconductor active layer; and insulating the source electrode, the drain electrode and the semiconductor active layer. Forming a film, patterning a gate electrode opening and a recess structure on the insulating film at the same time in a first resist, etching the insulating film using the first resist as a mask, and the pattern Forming an opening pattern on the second resist to expose only the gate opening pattern, exposing the semiconductor active layer by etching the insulating film, the first resist and the second resist Etching the semiconductor active layer in one or more steps using the mask as a mask, the first resist and the second resist. Method of manufacturing a field effect transistor which comprises a step of forming a gate electrode by a lift-off bets to mask the. 2. The method of manufacturing a field effect transistor according to claim 1, wherein the opening pattern formed on the second resist has an inverse taper shape. 3. The method of manufacturing a field effect transistor according to claim 1, wherein the step of etching the semiconductor active layer is performed in one step or two steps.