JPH0330438A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need to use a photoresist pattern as a mask when an Au-plated layer which is used as an air bridge is formed and to make it possible to form the Au-plated layer by a self-alignment by a method wherein a metal film, by which electrodes are connected to each other, is formed on a protective film, an opening part is formed in a second protective film, with which the metal film is covered, a second metal film is formed and the like. CONSTITUTION:A pair of second electrodes 12 and 14, by which a first electrode 13 on a semiconductor substrate 101 is held, and a first protective film 16 which covers the electrode 13 are formed, a first metal film 17, by which the electrodes 12 and 14 are connected to each other, is formed on the film 1 6 and the film 17 is covered with a second protective film 18. Then, an opening part is formed in the film 18 and on the regions of the electrodes 12 and 14 and a second metal film 20 is formed at a scheduled space wiring formation region, where is connected to each of the electrodes 12 and 14 through the opening part and is provided between the electrodes 12 and 14. Then, after a selective plating is applied to a second metal film 20 using the above film 17 as a cathode and a space wiring is formed, the film 18 is removed to make the film 17 expose and the film 17 is removed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, such as a space wiring (hereinafter abbreviated as an air bridge) used in an ultra-high frequency field effect transistor, etc. Regarding the formation of

(Prior Art) An explanation will be given by taking an ultra-high frequency power field effect transistor (hereinafter abbreviated as FET) as an example. In FETs, it is important to reduce the parasitic capacitance at the intersection of the source electrode and the gate feed line in order to increase the frequency, and for this reason, an air bridge structure is adopted in this area. FIG. 2 shows a part of the FET chip having an air bridge structure three-dimensionally.

Below is a FET that uses a conventional source air bridge structure.
The manufacturing process of the chip will be explained using process diagrams shown in FIGS. 3(a) to 3(i). Note that these sectional views represent the new surface of the portion indicated by the dashed line A-^ in FIG.

First, a source electrode 102, a source bonding pad 104, and a gate feed line 10 are placed on a semiconductor substrate 101.
form 3. Note that 105 is an insulating film of Sin2M (FIG. 3(a)).

Next, a silicon nitride film 106 is coated (FIG. 3(b)).

Next, as shown in FIG. 3(c), a photoresist layer 10 having openings corresponding to the source electrode 102 and the source bonding pad 104 is formed on the silicon nitride film 106.
7 will be provided.

Next, the silicon nitride film 106 is dry-etched using the photoresist layer 107 as a mask (FIG. 3(d)).
), the photoresist layer 107 is dissolved and removed.

Next, as shown in FIG. 3(e), a source bonding pad metal layer 108 is formed in the opening, and a silicon nitride film 108 is formed in the opening.
The photoresist layer 109 was patterned to cover the photoresist layer 6 (FIG. 3(f)), and then a metal film 110 was formed by full-surface vapor deposition (FIG. 3(g)).

Next, as shown in FIG. 3(h), a photoresist layer is provided as a mask for selective plating. When forming this photoresist layer, it is difficult to form the photoresist layer with high precision because of the step difference in the photoresist layer 109 which is the base.

After forming an Au plating layer 111 using the metal Btio as a cathode, the photoresist layer used as a mask during selective plating is removed, and then the metal film 110 is etched away using the All plating layer 111 as a mask.

Furthermore, by dissolving and removing the photoresist layer 109, a space 112 is formed in this portion, making it possible to realize an FET having an air bridge structure (FIG. 3(i)).
). Note that the photoresist layer 109 is dissolved and removed by
This is done by infiltrating the etching agent from an exposed portion (see FIG. 2) that is perpendicular to the air bridge.

(Problems to be Solved by the Invention) In the conventional manufacturing method described above, as shown in FIG. 3(h), when forming the Au plating layer 111 forming an air bridge,
It is difficult to form a photoresist pattern for selective plating with good positional accuracy.

This is to form a photoresist pattern on the metal film 110 having a step formed by the photoresist layer 109. Also, photo-etching on metal film (hereinafter abbreviated as PEP)
In this case, pattern defects such as residual development are likely to occur.
This causes a decrease in manufacturing yield.

The present invention has been made to solve the above-mentioned drawbacks.
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which it is not necessary to use a photoresist pattern as a mask when forming an Au plating layer serving as an air bridge, and the Au plating layer can be formed in a self-aligned manner.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a pair of second electrodes sandwiching a first electrode on a semiconductor substrate, and a first protective film covering the first electrode. a step of forming a first metal film connecting between the second electrodes on the first protective film; a step of covering the first metal film with a second protective film; forming an opening on the second electrode region in the second protective film; and a space connected to each of the second electrodes at the opening and provided between the second electrodes. a step of forming a second metal film in a region where wiring is to be formed;
a step of selectively plating a second metal film using the metal film as a cathode to form a space wiring; and a step of removing the second protective film to expose and remove the first metal film. It is something that

(Function) In the present invention, when forming the Au plating layer of the air bridge,
Only the second electrode and the second metal film in the area where the air bridge is to be formed are exposed, and the other areas are exposed.
covered with a protective film. Therefore, by using the first metal film under the second protective film as a cathode, selective plating can be applied to the second electrode and the second metal film in the area where the air bridge is to be formed in a self-aligned manner.

In addition to serving as a mask during selective plating, the second protective film also serves as an air bridge to provide air under the wiring by being dissolved and removed after increasing the height.

(Example) Hereinafter, one example of the present invention will be described with reference to the drawings.

FIGS. 1A to 1I are cross-sectional views showing, in order of steps, a method for manufacturing an FET using gallium arsenide (hereinafter referred to as GaAs) for a semiconductor substrate. Note that these cross-sectional views represent the cross section of the portion indicated by the dashed line A-A in FIG. 2.

As shown in FIG. 1(a), a GaAs semi-insulating substrate 101
Then, the source electrode 12 and the source bonding pad 1 are formed using a SiO□ film 15 (thickness: 5000 mm) formed by the normal pressure CVO method as a spacer and using a photoresist or by a foot-off method.
4 (2300 people thick) and gate feed line 13 (
6,500 people thick).

Thereafter, a silicon nitride film 16 is coated with a film thickness of 2000 mm by plasma CVD as a padding film (first
Figure (b)).

Next, a first metal film 17 (Au: 1000 people) having first openings 17a, 17b@- is formed in areas corresponding to the source electrode 12 and source bonding pad 14 by using a photoresist or by a foot-off method. (first
Figure (c)).

Next, the film 18 of Sin was formed to a thickness of 500 using the atmospheric pressure CVD method.
0 people were covered (Fig. 1(d)).

A photoresist pattern 19 having second openings 19a and 19b that are slightly larger than the first openings 17a and 17b of the first metal film 17 is formed by photoresist.
(Fig. 1(e)).

Next, using the photoresist pattern 19 as a mask, the SiO□ film 18 is etched away from the second openings 19a and 19b by chemical dry etching (hereinafter abbreviated as CDE) using a CF4 system. Using the metal wA 17 of No. 1 as a mask, the silicon nitride film 16 is removed by etching from the first openings 17a and 17b (FIG. 1(f)).

Next, after dissolving and removing the photoresist layer 19, the photoresist layer 19 is removed by using a photoresist or by a foot-off method as shown in FIG.
As shown in g), a source bonding pad metal layer 20 is formed using Au on the source electrode 12, the source bonding pad 14, and the 5in2 WI 118 in the area where the air bridge is to be formed.
/Pt/Ti (15000 people/1000 people/200
Formed by 0 people). At this time, the source bonding pad metal layer 20 is formed to be connected to the metal layer 17. Therefore, the S
Covered with an iO□ film 18, the first metal 1117 connects the source electrode 12 and the source bonding pad 14 under the Sin film 18.

Further, the 5in2 film 18 serves both as a mask during selective plating and as an interlayer insulating film of an air bridge to increase the height and is later dissolved and removed to create air between the layers.

Therefore, selective plating is applied to the source bonding pad metal layer 20 using the metal film 17 as a plating electrode (cathode) to form an Au plating layer 21 with a thickness of 2 μm (FIG. 1(h)). Here, the Au plating layer 21 is self-aligned with the source bonding pad metal layer 20.

Next, the Sin film 18 is completely dissolved and removed with NH4F to form a space 22, and then the metal film 17 is removed by etching with an etchant using the Au plating M21 as a mask, and then the metal film 17 is etched away using an etchant as shown in FIG. 1(i). A bridge structure is realized. This dissolution and removal of the Sun film 18 is achieved by the etching solution entering from the exposed portion (see FIG. 2) in the direction perpendicular to the air bridge.

In FIG. 2, 31 represents a gate electrode, 32 represents a drain electrode, and 33 represents a drain bonding pad.

In addition, although the example mentioned above took GaAsFET as an example,
The present invention can be applied to any case where a pair of divided electrodes are connected by an air bridge.

〔Effect of the invention〕

As described above, according to the present invention, when forming an Au plating layer forming an air bridge, there is no need to use a photoresist pattern as a mask, and the Au plating layer can be formed in a self-aligned manner in the area where the air bridge is to be formed. There are advantages.

[Brief explanation of drawings]

FIGS. 1(a) to (i) are cross-sectional views showing a manufacturing method according to an embodiment of the present invention in the order of steps, and FIG. 2 is a perspective view showing a part of an FET chip having an air bridge structure in three dimensions. The cross section of the part indicated by the dotted line A-^ is shown in the above-mentioned FIG. 1 and the following FIG. It is. 12... Source electrode, 13... Gate feed line, 14... Source bonding pad. 15° 18...5108 film, 17... First metal film, 19... Photoresist pattern. 17a. 17b... (first opening part of the first metal film). 19a. 19b... Second opening (of the first metal film), 20... Source bonding pad metal layer. 21...Au plating layer, 22...Space part.

Claims (1)

[Claims] forming a pair of second electrodes sandwiching the first electrode on the semiconductor substrate and a first protective film covering the first electrode; and forming a protective film on the first protective film between the second electrodes. forming a first metal film to be connected; covering the first metal film with a second protective film; and forming an opening in the second protective film over the second electrode area. a step of forming a second metal film in a planned formation region of a space wiring connected to each of the second electrodes at the opening and provided between the second electrodes; a step of selectively plating a second metal film using the metal film as a cathode to form a space wiring; and a step of removing the second protective film to expose and remove the first metal film. A method for manufacturing a semiconductor device.