JPH0231495B2 - - Google Patents
Info
- Publication number
- JPH0231495B2 JPH0231495B2 JP55130603A JP13060380A JPH0231495B2 JP H0231495 B2 JPH0231495 B2 JP H0231495B2 JP 55130603 A JP55130603 A JP 55130603A JP 13060380 A JP13060380 A JP 13060380A JP H0231495 B2 JPH0231495 B2 JP H0231495B2
- Authority
- JP
- Japan
- Prior art keywords
- insulator
- forming
- region
- base
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012212 insulator Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000004070 electrodeposition Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Description
【発明の詳細な説明】
この発明は、フオトリソ工程のマスク合せずれ
を防止するとともに雑音の発生を低減できるよう
にした半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device that can prevent mask misalignment in a photolithography process and reduce noise generation.
高速、高周波半導体素子は高速、高周波になる
につれて、増々微細素子構造が要求される。特
に、高性能、高速高周波トランジスタにおいて
は、エミツタ・ベース電極構造が微細になると同
時に、拡散深さも浅く、かつベース巾もあなり狭
くする必要がある。 As high-speed, high-frequency semiconductor devices become faster and higher in frequency, increasingly finer device structures are required. In particular, in high-performance, high-speed high-frequency transistors, it is necessary to make the emitter-base electrode structure finer, the diffusion depth shallower, and the base width considerably narrower.
しかし、従来の半導体製造工程においては、第
１図に示すように、半導体基板１に不活性ベース
拡散領域３、活性ベース拡散領域４、エミツタ拡
散領域５、コンタクト、電極６を形成するため
に、フオトリソ工程の数個のマスク合せ作業を必
要とする。このため、必然的にマスク合せのずれ
を生じるために、電極間のシヨートの発生原因と
なり、微細電極を形成することは非常に困難とな
つていた。なお、２は絶縁体である。 However, in the conventional semiconductor manufacturing process, in order to form an inactive base diffusion region 3, an active base diffusion region 4, an emitter diffusion region 5, a contact, and an electrode 6 on a semiconductor substrate 1, as shown in FIG. Requires several mask alignment operations during the photolithography process. This inevitably causes misalignment of the mask alignment, which causes shorts between the electrodes, making it extremely difficult to form fine electrodes. Note that 2 is an insulator.
一方、トランジスタの高性能、高周波化をはか
るべく、ベース巾（WB）をできるかぎり狭くす
るため、その結果、ベース抵抗（rhb′）を増大さ
せ、高周波小信号トランジスタでは雑音の源とな
つていた。 On the other hand, in order to achieve high performance and high frequency transistors, the base width (W B ) is made as narrow as possible, which results in an increase in base resistance (r hb '), which becomes a source of noise in high frequency small signal transistors. was.
また、高周波高出力トランジスタでは、ベース
抵抗（rhb′）増大にともない、出力低下の大きな
原因となつていた。 Furthermore, in high-frequency, high-output transistors, an increase in base resistance (r hb ′) has been a major cause of a decrease in output.
この発明は、上記従来の欠点を除去するために
なされたもので、半導体素子製造におけるフオト
リソ工程のマスク合せのずれを生じていたもの
を、不活性ベース領域を形成した後に、最終的に
ベースとエミツタの両電極位置となるべき位置を
絶縁体を用いて固定してしまい、従来のマスク合
せごとの位置ずれをなくすることができるととも
に、高周波トランジスタの雑音源、低出力化の原
因となつていた不用ベース抵抗を活性ベース領域
形成時に最終的にエミツタ領域となるべき部分に
絶縁体を置くことによつてエミツタ直下のベース
抵抗のみの抵抗にすることにより、特性の向上を
はかることのできる半導体装置の製造方法を提供
することを目的とする。 This invention was made in order to eliminate the above-mentioned conventional drawbacks, which caused misalignment of masks in the photolithography process in semiconductor device manufacturing. By using an insulator to fix the positions of both electrodes of the emitter, it is possible to eliminate positional deviations that occur when aligning masks, which is a source of noise in high-frequency transistors and a cause of low output. A semiconductor whose characteristics can be improved by placing an insulator in the part that will eventually become the emitter region when forming the active base region to reduce the unnecessary base resistor to only the base resistor directly under the emitter region. The purpose is to provide a method for manufacturing the device.
以下、この発明の半導体装置の製造方法の実施
例について図面に基づき説明する。第２図ａない
し第２図ｄはそれぞれこの発明の半導体装置の製
造方法の実施例を説明するための工程図であり、
半導体装置として高周波トランジスタに適用した
場合を示している。 Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. 2a to 2d are process diagrams for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention, respectively,
A case is shown in which the semiconductor device is applied to a high frequency transistor.
まず、第２図ａに示すように、半導体基板１を
用いて、絶縁体２（第１の絶縁体）、不活性ベー
ス領域３をシリコンプレーナ技術で形成した後、
不活性ベース領域３を含む素子形成領域上の絶縁
体２を物理反応または化学反応を利用して完全に
除去した後、第２の絶縁体としての薄い絶縁体７
（〜300ÅSiO2）、第３の絶縁体としての絶縁体８
（500〜1000ÅSi3N4）を全面に付着した後、第２
図ｂに示すようにベース・エミツタ電極位置
（EE、EB）および絶縁体２上の絶縁体７，８を残
して、それ以外の絶縁体７，８を除去した後、イ
オン注入（ドーズ量〜1014／cm2）または熱拡散で
第２図に示すように活性ベース領域９を形成す
る。このイオン注入または熱拡散という熱処理に
よつて、ベース・エミツタ電極位置EE、EB間
（２箇所）にも第４の絶縁体としての絶縁体２
（酸化膜）が形成される。 First, as shown in FIG. 2a, using a semiconductor substrate 1, an insulator 2 (first insulator) and an inactive base region 3 are formed by silicon planar technology.
After completely removing the insulator 2 on the element formation region including the inactive base region 3 using a physical or chemical reaction, a thin insulator 7 as a second insulator is removed.
(~300ÅSiO 2 ), insulator 8 as the third insulator
After depositing (500-1000ÅSi 3 N 4 ) on the entire surface, the second
As shown in Figure b, after removing the insulators 7 and 8 on the base and emitter electrode positions (E E , E B ) and the insulator 2, leaving the insulators 7 and 8 on the insulator 2, ion implantation (dose) is performed. 10 14 /cm 2 ) or thermal diffusion to form an active base region 9 as shown in FIG. Through this heat treatment of ion implantation or thermal diffusion, an insulator 2 as a fourth insulator is also formed between the base and emitter electrode positions E E and E B (at two locations).
(oxide film) is formed.
なお、第２図ａでは絶縁体２を素子形成領域上
から除去する際、該絶縁体２の一部を薄く残して
これを絶縁体７として利用して、該絶縁体７と絶
縁体８の２層構造からなる絶縁体パターンをベー
ス電極位置EBおよびエミツタ電極位置EEに形成
してもよい。この絶縁体パターンの形成（絶縁体
７は、上記のように絶縁体２を利用してもよい
し、利用しなくてもよい）により、最終的にエミ
ツタ電極位置およびベース電極位置となる位置が
同時に固定（決定）される。 In FIG. 2a, when the insulator 2 is removed from above the element forming area, a thin part of the insulator 2 is left and used as the insulator 7, and the insulator 7 and the insulator 8 are removed. An insulator pattern having a two-layer structure may be formed at the base electrode position E B and the emitter electrode position E E. By forming this insulator pattern (the insulator 7 may or may not use the insulator 2 as described above), the positions that will eventually become the emitter electrode position and the base electrode position are determined. Fixed (determined) at the same time.
次に、レジストを用いて、第２図ｄに示すエミ
ツタ領域１１上のみの絶縁体７，８を絶縁体２
（SiO2）と物理、化学反応速度の異なりや膜厚差
を利用して除去し、全面に多結晶シリコン１０を
CVDまたは真空蒸着などで〜2000Å付着した後、
ASなどのエミツタ不純物ソースをイオン注入
（ドーズ量1016／cm2）または熱拡散で多結晶シリ
コンに含ませた後、第２図ｄに示すエミツタ電極
位置の多結晶シリコン１０以外を除去し、900℃
前後の熱処理で残存多結晶シリコン１０からの不
純物拡散により同図のようにエミツタ領域１１を
活性ベース領域９内に形成した後、ベース電極位
置の絶縁体７，８をレジストを用いて除去し、そ
こに高融点Si−Pt系電極１２（ベース電極）を蒸
着、形成する。しかる後に、半導体基板１の下面
側にAu系電極１３を付けて完成する。 Next, using a resist, the insulators 7 and 8 only on the emitter region 11 shown in FIG. 2d are replaced with the insulator 2.
(SiO 2 ), using the difference in physical and chemical reaction rates and film thickness to remove polycrystalline silicon 10 on the entire surface.
After depositing ~2000Å by CVD or vacuum evaporation, etc.
After incorporating an emitter impurity source such as A S into the polycrystalline silicon by ion implantation (dose amount 10 16 /cm 2 ) or thermal diffusion, the polycrystalline silicon 10 other than the emitter electrode position shown in FIG. 2d is removed. ,900℃
After the emitter region 11 is formed in the active base region 9 as shown in the figure by diffusion of impurities from the remaining polycrystalline silicon 10 in the previous and subsequent heat treatments, the insulators 7 and 8 at the base electrode position are removed using a resist. A high melting point Si--Pt based electrode 12 (base electrode) is deposited thereon. Thereafter, an Au-based electrode 13 is attached to the lower surface of the semiconductor substrate 1 to complete the process.
以上説明したようにして半導体装置を形成する
ことによる第１の特徴はベースとエミツタの両電
極部を固定することにより、マスク合せごとのず
れを完全に除去して、作業能率を向上させた点で
ある。 The first feature of forming a semiconductor device as explained above is that by fixing both the base and emitter electrode parts, misalignment during mask alignment is completely eliminated and work efficiency is improved. It is.
また、第２の特徴は電極部位置固定用絶縁物を
拡散時の障害物に利用して、エミツタ直下のベー
ス領域のみを非常に狭くして、それ以外（不活性
部）はできるだけ広くして、これまでトランジス
タの雑音、出力低下の原因とされていたベース抵
抗をできるだけ必要最小限にした点である。 The second feature is that the insulator for fixing the electrode position is used as an obstacle during diffusion, making only the base area directly under the emitter extremely narrow, and making the rest (inactive area) as wide as possible. , the base resistance, which has been thought to be the cause of transistor noise and output reduction, has been minimized as much as possible.
以上詳述したように、この発明の半導体装置の
製造方法によれば、不活性ベース領域を形成した
後に最終的にベースとエミツタの両電極位置とな
るべき位置を絶縁体を用いて固定するようにした
ので、マスク合せごとの位置ずれがなくなり、作
業能率を向上できる。 As detailed above, according to the method of manufacturing a semiconductor device of the present invention, after forming an inactive base region, the positions that will ultimately become the base and emitter electrode positions are fixed using an insulator. This eliminates positional deviations during mask alignment, improving work efficiency.
また、活性ベース領域形成時に最終的にエミツ
タとなるべき部分に絶縁体を置くようにしたの
で、エミツタ直下のベース抵抗のみの抵抗とする
ことができ、それにともない雑音の発生が低減で
き、高性能半導体トランジスタ、IC、LSIの製作
に利用できるなどの効果を奏する。 In addition, since an insulator is placed in the area that will eventually become the emitter when forming the active base region, the base resistance directly below the emitter can be the only resistance, which reduces noise generation and provides high performance. It can be used to produce semiconductor transistors, ICs, and LSIs.
第１図は従来の半導体装置の製造方法を説明す
るための断面図、第２図ａないし第２図ｄはそれ
ぞれこの発明の半導体装置の製造方法の一実施例
を説明するための工程断面図である。
１……半導体基板、２，７，８……絶縁体、３
……不活性ベース領域、９……活性ベース領域、
１０……多結晶シリコン、１１……エミツタ領
域、１２……高融点Si−Pt系電極、１３……Au
系電極。
FIG. 1 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device, and FIGS. 2a to 2d are process cross-sectional views for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention. It is. 1... Semiconductor substrate, 2, 7, 8... Insulator, 3
...Inactive base region, 9...Active base region,
10... Polycrystalline silicon, 11... Emitter region, 12... High melting point Si-Pt based electrode, 13... Au
system electrode.
Claims (1)
かつ半導体基板上に第１の絶縁体を形成した後、
前記不活性ベース領域を含む素子形成領域上の不
要な第１の絶縁体を除去し、この除去領域中、ベ
ース電極形成位置およびエミツタ電極形成位置に
同時に、第２、第３の絶縁体の２層構造からなる
電極位置固定用および拡散深さ制御用の絶縁体パ
ターンを形成し、あるいは前記第１の絶縁体の不
要部分を除去する際、それを一部薄く残してこれ
を前記第２の絶縁体として利用して該第２の絶縁
体とその上の第３の絶縁体からなる２層構造の前
記絶縁体パターンを前記各位置に形成する工程
と、 その後、イオン注入または熱拡散で半導体基板
内に活性ベース領域を形成し、同時にベース電極
形成位置およびエミツタ電極形成位置の２層構造
絶縁体パターン相互間に第４の絶縁体のパターン
を形成する工程と、 その後、エミツタ電極形成位置の前記２層構造
絶縁体パターンを除去し、そこに不純物ドープの
多結晶シリコンパターンを形成し、この多結晶シ
リコンパターンからの不純物拡散により、活性ベ
ース領域内にエミツタ領域を形成する工程と、 その後、ベース電極形成位置の前記２層構造の
絶縁体パターンを除去し、そこに不活性ベース領
域に接続されるベース電極を形成する工程とを具
備してなる半導体装置の製造方法。[Claims] 1. Forming an inactive base region in a semiconductor substrate,
and after forming the first insulator on the semiconductor substrate,
The unnecessary first insulator on the element formation region including the inactive base region is removed, and in this removed region, two of the second and third insulators are simultaneously added to the base electrode formation position and the emitter electrode formation position. When an insulator pattern for fixing the electrode position and controlling the diffusion depth consisting of a layered structure is formed, or when unnecessary parts of the first insulator are removed, a part of the insulator is left thin and is then used as the second insulator. a step of forming the insulator pattern of a two-layer structure consisting of the second insulator and a third insulator thereon at each position using the second insulator as an insulator, and then forming a semiconductor by ion implantation or thermal diffusion. forming an active base region in the substrate and simultaneously forming a fourth insulator pattern between the two-layer insulator patterns at the base electrode formation position and the emitter electrode formation position; removing the two-layer structure insulator pattern, forming an impurity-doped polycrystalline silicon pattern thereon, and forming an emitter region in the active base region by impurity diffusion from the polycrystalline silicon pattern; A method for manufacturing a semiconductor device, comprising the steps of: removing the two-layer structure insulator pattern at a base electrode forming position, and forming a base electrode connected to an inactive base region therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13060380A JPS5756965A (en) | 1980-09-22 | 1980-09-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13060380A JPS5756965A (en) | 1980-09-22 | 1980-09-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5756965A JPS5756965A (en) | 1982-04-05 |
| JPH0231495B2 true JPH0231495B2 (en) | 1990-07-13 |
Family
ID=15038155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13060380A Granted JPS5756965A (en) | 1980-09-22 | 1980-09-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5756965A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0310790U (en) * | 1989-06-19 | 1991-01-31 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60108023U (en) * | 1983-12-24 | 1985-07-23 | 株式会社アドバンテスト | High precision voltage generator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010580A (en) * | 1973-05-25 | 1975-02-03 | ||
| JPS5010974A (en) * | 1973-05-25 | 1975-02-04 | ||
| JPS5167069A (en) * | 1974-12-07 | 1976-06-10 | Fujitsu Ltd | Handotaisochino seizohoho |
-
1980
- 1980-09-22 JP JP13060380A patent/JPS5756965A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010580A (en) * | 1973-05-25 | 1975-02-03 | ||
| JPS5010974A (en) * | 1973-05-25 | 1975-02-04 | ||
| JPS5167069A (en) * | 1974-12-07 | 1976-06-10 | Fujitsu Ltd | Handotaisochino seizohoho |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0310790U (en) * | 1989-06-19 | 1991-01-31 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5756965A (en) | 1982-04-05 |
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