JPS6014466A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the accuray of an emitter photoetching process as well as to contribute in the stabilization of characteristics of the titled integrated circuit when it is used as a high frequency integrated circuit and the like by a method wherein an emitter diffusion window and a collector diffusion window are simultaneously formed on a thermal oxide film by performing an etching. CONSTITUTION:After a thermal oxide film has been formed by performing a process in the same manner as before, a base diffusion window 22 and a collector contact window 23 are formed by performing a photoetching on the thermal oxide film 21. Then, resist is applied on the surface of a wafer, and a patterning is performed on the resist using a mask pattern 24. Subsequently, P type impurities are doped on a base region as shown by the arrow A using said resist as a mask, and a base diffusion layer 26 is formed. Then, the resist is removed completely, a heat treatment is performed in an oxidizing atmosphere, the desired junction depth of the base is obtained, and a thermal oxide film 25 is covered on the base diffusion window 22 and the collector contact window 23. Then, a window is provided on the thermal oxide film 25, and an emitter diffusion window 27 and a collector contact diffusion window 28 are formed. Subsequently, an already known process is performed, and the integrated circuit is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semi-conducting circuit with a high yield of electrically good semiconductor devices (Prior Art) Conventional bipolar semiconductor The method for manufacturing the device is as follows. First, as shown in FIG. 1(a).

Selective embedding and diffusion 2 in desired locations of P-type silicon substrate 1
is applied, and epitaxial growth is performed thereon to form isolation epitaxial regions 4.

Thereafter, in order to electrically isolate this epitaxial region 4, an isolation diffusion layer 3 is formed by selectively diffusing impurities having the same conductivity type as that of the P-type silicon substrate 1.

In this way, the isolation process for obtaining isolated epitaxial regions 4 for forming elements such as transistors, resistors, capacitors, etc. is completed.

Next, this isolation completed ueno k: heat rG
'.

Then, as shown in FIG. 1(a), the entire selective diffusion mask oxide film 5 for performing the subsequent pace diffusion is obtained.

Next, as shown in FIG. 1(b), the selective diffusion mask oxide film 5 is photo-etched, and the transistor paste diffusion region 6 is
After that, P is applied to this base diffusion region 6.
A type impurity is doped and heat treatment is performed in an oxidizing atmosphere to obtain a desired paste junction depth and to form a paste oxide film 7 on the upper part of the base diffusion region 6.

Next, as shown in FIG. 1(e), in order to perform emitter diffusion, the paste oxide film 7 is opened by photolithography to form a window portion 8 for emitter diffusion.

Incidentally, in this step, it is common to simultaneously open a window in the collector contact diffusion portion 9 in order to diffuse impurities.

This is to reduce the resistance of the epitaxial layer at the collector electrode extraction part by diffusing N-type impurities in this area at the same time as the emitter diffusion, and to improve the saturation characteristics of the transistor. This is done for the purpose of improving ohmic properties in alloy processing with.

Incidentally, the thickness of the oxide film to be opened is different between the emitter diffusion opening portion 8 and the collector contact diffusion portion 9.

That is, in general, the mask oxide film 5 for selective diffusion is thicker than the paste oxide film 7. Therefore, in the oxide film etching in this step, in order to open both in the same process, even after the opening of the base oxide film 7 is completed, the opening of the mask oxide film 5 for selective diffusion is completed. It was necessary to continue etching until the collector contact diffusion region 9 appeared.

As a result, it has been found that overetching occurs in the emitter diffusion fenestration portion 8, and as a result, side etching occurs in this portion, causing the emitter size to deviate or vary from the design target value.

Therefore, it is not suitable as a process for manufacturing high-speed logic operation integrated circuits or high-frequency integrated circuits that require fine emitter size.

Furthermore, since the step of the oxide film in the collector contact region is large, there is a great risk that the metal wiring film formed in a subsequent process will be cut at this step, that is, the yield will be reduced due to so-called step breakage.

(Purpose of the Invention) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and is capable of greatly improving the accuracy of the emitter photoetch process, and is also applicable to integrated circuits and high-frequency integrated circuits that require high-speed logic operation. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that can be expected to contribute to stabilizing characteristics even when used in a semiconductor integrated circuit.

(Purchase of the Invention) A method for manufacturing a semiconductor integrated circuit according to the present invention is to apply photorenost to the entire surface of an oxide film on a semiconductor wafer after opening windows to form a paste region and a collector region, and apply photorenost only to the paste region. After patterning and opening a window, doping impurities only in the paste region using the photorenost as a mask to form a paste diffusion layer, and after forming the paste diffusion window, remove the resist to form a thermal oxide film. The emitter diffusion window and the collector contact diffusion window are simultaneously formed by etching the space diffusion window and the collector contact region, and then etching the thermal oxide film.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described based on the drawings. 6. FIGS. 2(a) to 2(d) are process explanatory diagrams of one example. .

This invention performs buried diffusion in a silicon substrate, performs L-cut taxial growth, performs complete isolation diffusion to separate each element, and then thermally oxidizes the upper surface of the epitaxial layer to form a thermal oxide film. There is no difference from the conventional manufacturing method up to the point where it is formed. Therefore, Fig. 1(a)
The same parts as those in FIG. 1(c) are denoted by the same reference numerals and their explanations are omitted, and the parts different from those in FIGS. 1(a) to 1(e) will be mainly described.

After forming a thermal oxide film in the same manner as in the conventional case, the thermal oxide film 21 is then deposited as shown in FIG. 2(a).
is photoetched to open the pace diffusion window 22 and the collector contact window 23.

At this time, it is preferable to open the collector contact hole 23 to be opened to be larger than the window to be opened for later emitter diffusion.

Next, a resist is applied to the surface of this semiconductor wafer, and in order to open a window only in the paste region, a mask pattern 24 for ion implantation prepared in advance is used as shown in FIG. 2(b). Perform resist horns and turning.

The dimensions of this ion implantation mask pattern are made thicker than the above pattern, so that even if misalignment occurs during alignment, the resist pattern will not overlap with the thermal oxide film 25 (paste oxide film) patterned in the previous process. It is preferable to avoid covering the edges of the paste pattern (in short, it is sufficient that at least the collector contact region opened at the same time as the paste is covered with the resist).

Next, using this resist as a mask, the base region is doped with P-type impurities as shown by arrow A by ion implantation. As a result, a pace diffusion layer 26 is formed.

Next, as shown in FIG. 2(c), the resist is completely removed and treated with alcohol in an oxidizing atmosphere to obtain the desired bonding depth of the paste and the base diffusion window 22.
And the collector contact window 23 is surrounded by a thermal oxide film 25.

Thereafter, the thermal oxide film 25 is opened in order to selectively diffuse impurities into the emitter and collector contact regions. This forms an emitter diffusion window 27 and a collector contact diffusion window 28.

FIG. 2(d) shows the state after the above steps have been completed.

After that, the integrated circuit is completed through known steps.

As explained above, in the above embodiment, when the emitter diffusion region is opened, the collector diffusion region is also opened at the same time, but since both are oxide films of the same thickness, the heat generated during the opening of the emitter region is Because the oxide film etching and the oxide film etching at the opening in the collector region are completed at the same time,
Dimensional increases and variations due to over-etching that occur when opening the emitter region in conventional processes are eliminated.

There are two steps in the thermal oxide film around the collector contact.
Since the metal wiring layer is stepped, the level difference in the metal wiring layer located above becomes gentle, and a decrease in yield due to wiring step breakage can be prevented.

(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor integrated circuit of the present invention, the collector contact diffusion window is opened at the same time as the emitter diffusion window is opened using a thermal oxide film of the same thickness. Since both etchings are completed at the same time, the accuracy of the emitter photoetch process can be greatly improved, and by using it for integrated circuits that require high-speed logic operation and high-frequency integrated circuits, it is possible to improve the accuracy of these integrated circuits. This contributes to stabilizing the characteristics.

[Brief explanation of drawings]

1(a) to 1(e) are process explanatory diagrams of a conventional semiconductor integrated circuit manufacturing method, and FIGS. 2(a) to 2(d) are process explanatory diagrams of a semiconductor integrated circuit manufacturing method of the present invention. 1. Silicon substrate, 2. Buried diffusion layer, 3.
isolation diffusion layer, 4... epitaxial layer,
21...Mask oxide film, 22...Base diffusion window, 2
3... Collector contact window, 24... Ion implantation mask/resist cutan, 25... Thermal oxide film, 26... Pace diffusion layer, 27... Emitter diffusion window, 28... Collector contact diffusion window. Patent Applicant Oki Electric Industry Co., Ltd. Figure 1 5 Figure 2 Procedural Amendment 1939, February 28th Patent Office Commissioner Wakasugi No. 11 Daidono 1, Indication of Case 1982 Patent Application No. 1209502, Invention Name of semiconductor collection KD+ circuit manufacturing method 3, relationship with the case of the person making the amendment Patent Applicant (029) Oki'iij, Kikoo Co., Ltd. 4, Agent 5, Weight of amendment order Monthly 11, Showa eyes) 6,
The subject of the amendment is the detailed description of Il Lu's invention (f ¥1 and drawing 7)
, Contents of the amendment As shown in the attached sheet 7 Contents of the amendment 1) Meisho] Invitation - page 7, line 1 "After all...Yoshita"
is corrected to read, ``This is the collector contact diffusion window that will be fenestrated in a later process.'' 2) Figure 2 of the drawing (correct bJ to the attached sheet ifJ).

Claims (1)

[Claims] coating the entire surface with photoresist after opening a paste diffusion window and a collector contact window to form a paste region and a collector region in an oxide film on the semiconductor wafer;
There are two steps: patterning the photoresist and opening windows only in the paste region; a step of doping impurities only in the paste region using the photoresist as a mask after the window; and removing the photoresist after doping to form a thermal oxide film and opening the paste. A method of manufacturing a semi-m integrated circuit comprising the steps of covering a diffusion window and a collector contact region and etching the thermal oxide film to simultaneously form an emitter diffusion window and a collector contact diffusion window.