JPS5929136B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and in particular provides a self-alignment method for forming a semiconductor device with high precision.

In conventional bipolar high-speed logic ICs, the areas occupied by the base and emitter have been reduced in order to increase the switching speed.

However, if the occupied area is reduced, the contact hole for leading out the electrode will inevitably become smaller. In conventional photographic surgery, there is "mask misalignment" within and between masks, and it has been difficult to reduce the size of the contact hole to less than a few microns.
As a measure to overcome this restriction and reduce the emitter size required for high-speed logic ICs to several microns or less, there is a so-called washed emitter method in which the emitter diffusion hole is used as it is as a contact hole for leading out the electrode. But np
Since the impurity used for emitter diffusion of an n-transistor is generally phosphorus, when this phosphorus is diffused, it reacts with SiO2 of the insulating film to form phosphorus glass. Since phosphorus glass has a higher etching rate than SiO2, the openings for diffusion tend to expand laterally during later etching. Therefore, when forming electrodes, the base
A serious drawback was that the emitters were easily short-circuited, reducing product yield. The present invention has been made to eliminate the drawbacks of the above-mentioned conventional manufacturing methods for semiconductor devices, and provides a method for manufacturing semiconductor devices using a self-alignment method that overcomes the drawbacks of the washed emitter method.

The method of manufacturing a semiconductor device according to the present invention is achieved as follows.

That is, the first insulating film is formed on the main surface of the semiconductor substrate.
a second step of laminating a second insulating film on the insulating film and patterning it; a second step of laminating the second insulating film on the insulating film and patterning the second insulating film; using the pattern of the second insulating film as a mask; a third step of etching to provide an exposed region on the surface of the semiconductor substrate; a fourth step of diffusing impurities into the exposed region using the etched first insulating film as a mask; a fifth step of forming a film, a sixth step of performing ion etching or sputter etching on the third insulating film using the second insulating film as a mask, and a third step of removing the second insulating film.
A seventh step of leading out electrodes into the openings of the insulating coating. DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be explained below in order of steps with reference to the drawings.

Regarding Figure 1, 1a has a specific resistance of 20Ω・My P type 100
A silicon substrate, one main surface of the silicon substrate is selectively diffused with an example of antimony (Ab) to a thickness of 1.5μ (later to become an N+ buried layer) to form a diffusion layer 1b, and then a diffusion layer 1b is formed. Due to hydrogen reduction of SiCl4, the specific resistance is 0.4Ω・My N
A mold epitaxial layer 1c was formed to have a thickness of 3.5 μm, and the semiconductor substrate 1 as described above was formed. Next, a silicon oxide film 3 is formed on the main surface of the epitaxial layer 3 (first step), and boron (3) is selectively diffused at 1150+°C.3.
A P isolation layer 4 having a thickness of 5 μm is formed to isolate the elements.

Further, approximately 3 μm of phosphorus was diffused in phosphorus oxychloride (POCI) gas at 1150° C. to form an N+ layer 5. This N+ layer 5 is the collector layer and the N+ diffusion layer (buried layer) 1
Connect to b. At this point, the silicon oxide film 3' has a thickness of about 5000
It's a person. Next, a base layer 6 was formed by diffusing 1.5μ of boron at 1100°C. A silicon nitride film 7 having a thickness of about 5000λ was formed by thermal decomposition of monosilane (SiH4) and ammonia (NH,) to be laminated on the silicon oxide film 3'. Next, the photoresist film 8 deposited by well-known photolithographic techniques is patterned to correspond to the emitter region, and some openings 8' are formed (second step, FIG. 2).
. Using the photoresist pattern as a mask, the silicon 7 nitride film 7 is removed by plasma etching in Freon (CF4), and then the silicon oxide film 3 is removed and the opening 13 is removed.
' was set. At this time, the silicon oxide film 3' is 1.
Etching was performed to a wide area of 5 μm (t in FIG. 3 indicates overetching) (third step, FIG. 3). Using the silicon oxide film 3 as a mask, 1.0μ of phosphorus was diffused at 1000°C to form an emitter region 9 (fourth step, FIG. 4).
. Next, the opening 14 was thermally oxidized to form a silicon oxide film 10 having a thickness of 2000λ (fifth step, FIG. 5). Using the silicon nitride film 7 as a mask, a portion of the silicon oxide film 10 was removed by ion etching using argon gas.
At this time, the silicon oxide film 3' under the silicon nitride film is not etched (sixth step, FIG. 6). Next, contact holes for the base and collector were formed using a well-known photolithography technique. At this time, the silicon nitride film was etched by plasma etching, and the silicon oxide film was etched with NH4F.
Next, after removing the silicon nitride film using hot phosphoric acid, aluminum was deposited to form electrodes (emitter electrode 11, base electrode 12, collector electrode 13), and an IC was constructed (seventh step, seventh step). figure). Some N formed as above
When we measured the electrical characteristics of a PN transistor, we found that
Compared to the conventional washed emitter method, there was no short circuit between the emitter and base, and the product yield was significantly improved.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 1...Semiconductor substrate, 3,3'...
...Silicon oxide film (first insulating film), 7...
・Silicon nitride film (second insulating film), 10...
・Silicon oxide film (third insulating film), 11...
・Base electrode, 12... Emitter electrode, 13.
...Collector electrode.

Claims (1)

[Claims] 1. A first step of forming a first insulating film on one main surface of a semiconductor substrate, a second step of forming a second insulating film by laminating it on the insulating film and patterning it, and a second step of forming the second insulating film on one main surface of the semiconductor substrate. a third step of etching the first insulating film wider than the opening using the pattern of the film as a mask to provide an exposed portion on the surface of the semiconductor substrate; a fourth step of diffusing impurities into the exposed region of the semiconductor substrate; a fifth step of forming a third insulating film on the exposed region; and a third insulating film using the second insulating film formed in the shape of an eave as a mask. The sixth step is to perform ion etching or sputter etching on the
a seventh step of removing the second insulating film and leading out an electrode into the opening of the third insulating film.