JPS5912020B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5912020B2
JPS5912020B2 JP3906675A JP3906675A JPS5912020B2 JP S5912020 B2 JPS5912020 B2 JP S5912020B2 JP 3906675 A JP3906675 A JP 3906675A JP 3906675 A JP3906675 A JP 3906675A JP S5912020 B2 JPS5912020 B2 JP S5912020B2
Authority
JP
Japan
Prior art keywords
film
silicon nitride
thermal oxide
oxide film
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3906675A
Other languages
Japanese (ja)
Other versions
JPS51114881A (en
Inventor
敬二郎 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3906675A priority Critical patent/JPS5912020B2/en
Publication of JPS51114881A publication Critical patent/JPS51114881A/en
Publication of JPS5912020B2 publication Critical patent/JPS5912020B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は半導体装置の高速化ならびに高密度化を目的に
トランジスタ部のベース拡散領域を小さくした場合に問
題となるエミッタ端部におけるエミッタとコレクタの短
絡による不良を防ぐ方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for preventing defects due to emitter-collector shorting at the emitter end, which is a problem when the base diffusion region of a transistor part is made smaller for the purpose of increasing the speed and density of a semiconductor device. It is related to.

一定のエミッタ面積を持つトランジスタを小型5 化し
、高速化する場合、ベース領域を小さくする必要がある
In order to make a transistor with a fixed emitter area smaller and faster, it is necessary to make the base region smaller.

一般のトランジスタでは第1図aに示すようにベース領
域1の内部にエミッタ領域2は完全に入つているが、超
高速が要求されるトランジスタにおいては第1図bに示
すような構造が10取られている。この構造ではエミッ
タの2辺がベース領域の周辺に接触しているために上下
方向の余分な領域は完全になくすことができる。このよ
うな構造にするためには第2図に示すようにベース領域
1を拡散後、ベース領域よりも大15きなエミッタ・パ
ターン3を用いてホトエッチングし、ベースの外側の領
域とベース上の酸化膜の厚さの違いなどを利用して、ベ
ース上にのみエミッタ拡散用の穴が形成されるような方
法がとられている。
In a general transistor, the emitter region 2 is completely contained within the base region 1 as shown in FIG. It is being In this structure, since the two sides of the emitter are in contact with the periphery of the base region, the excess area in the vertical direction can be completely eliminated. To obtain such a structure, as shown in Figure 2, after diffusing the base region 1, photoetching is performed using an emitter pattern 3 that is 15 times larger than the base region, and the area outside the base and on the base is etched. A method is used in which a hole for emitter diffusion is formed only on the base by taking advantage of differences in the thickness of the oxide film.

20第3図は第2図のA、N断面に相当する断面図であ
る。
20. FIG. 3 is a sectional view corresponding to the A and N sections in FIG. 2.

ベース領域以外の部分を選択酸化した後。ベース層7を
拡散し、ホトレジスト膜4を用いて酸化膜5をエッチン
グし、エミッタ層8を拡散した所である。25ベース拡
散時の酸化膜5は点線で示した領域まで広がつていたの
で、酸化膜の下の横方向の拡散は点Bより始まD、大体
深さ方向の0.8倍の所まで拡散する。
After selectively oxidizing parts other than the base area. The base layer 7 is diffused, the oxide film 5 is etched using the photoresist film 4, and the emitter layer 8 is diffused. 25 During the base diffusion, the oxide film 5 had spread to the area indicated by the dotted line, so the lateral diffusion under the oxide film started from point B and reached approximately 0.8 times the depth in the depth direction. Spread.

これに対してエミッタ拡散はエミッタのホトエッチング
時に後退した点Cより始まる30ために深さ方向に比較
して端部のベース幅は狭くなク、エミッタ層8とコレク
タ層6が短絡し、不良となる可能性が非常に大きくなる
。本発明はベース領域の周辺に深い拡散層を設けてこの
欠点を解決し、特性の良好な半導体装置を35製作可能
としたものである。
On the other hand, since the emitter diffusion starts from the point C that retreated during emitter photoetching, the base width at the end is narrower than in the depth direction, resulting in a short circuit between the emitter layer 8 and the collector layer 6, resulting in failure There is a huge possibility that this will happen. The present invention solves this drawback by providing a deep diffusion layer around the base region, making it possible to manufacture 35 semiconductor devices with good characteristics.

以下において本発明を実施例によつて詳細に説明する。The present invention will be explained in detail below using examples.

第4図a−eは本発明によるトランジスタの製作工程で
ある。
FIGS. 4a to 4e show the manufacturing process of a transistor according to the present invention.

aはn形0.5Ω=、(100)面のシリコンワエーハ
9の表面に熱酸化膜10を500X形成した後モノシラ
ン(SiH,)とアンモニアけ3)の反応による窒化珪
素(Si3N,)膜11を1000Aの厚さに、さらに
その上に重ねてモノシランによるSiO2膜12を50
00Aの厚さに被着した所である。同図bは上記被膜に
ホトエツチング技術を用いて所定のパターンを形成した
所である。まず、所定のマスクを用いてホトレジスト膜
13を形成した後、この膜をマスクにしてSiO2膜1
2をエツチングする。エツチング液としては弗化水素酸
(50%)と中性弗化アンモニウム溶液(40%)を1
対6の割合で混合して用いた。続いて窒化珪素膜11を
フレオン系のガスプラズマ中で20m菖間エツチングし
た。なお.窒化珪素膜のエツチングに熱リン酸を用いた
場合にはホトレジスト膜も除去されてしまラが,プラズ
マエツチを行なつた場合にはホトレジスト膜を残すこと
が可能である。窒化珪素膜のエツチング後前記弗化水素
酸系のエツチング液でホトレジスト膜13をマスクにし
てSiO2膜12の側面のエツチングを行ない、窒化珪
素膜上にひと回ヤ小さなSiO2膜を形成する。具体的
には上記エツチング液を用いて4分間エツチングし、窒
化珪素膜より2μm小さくする。なおこのエツチングに
おいて窒化珪素膜11の上の熱酸化膜10も同時にエツ
チングされるが、エツチ速度が遅い(χ1000X/=
)ために横方向への広がDは非常に小さい。同図cはホ
トレジスト膜13を除去した後25℃の水酸化カリワム
溶液(40%)中でシリコン表面を0.7μmの深さに
エツチングし、1000℃で16時間、水蒸気を含んだ
酸素中で酸化して1.8μmの熱酸化膜14を形成した
所である。
a is n-type 0.5Ω=, after forming a thermal oxide film 10 at 500× on the surface of the (100) plane silicon wafer 9, a silicon nitride (Si3N,) film is formed by the reaction of monosilane (SiH, ) and ammonia 3). 11 to a thickness of 1000A, and on top of that a SiO2 film 12 made of monosilane with a thickness of 50A.
This is the area where the coating was applied to a thickness of 00A. Figure b shows a predetermined pattern formed on the film using photoetching technology. First, a photoresist film 13 is formed using a predetermined mask, and then the SiO2 film 13 is formed using this film as a mask.
Etch 2. As an etching solution, one part hydrofluoric acid (50%) and one part neutral ammonium fluoride solution (40%) were used.
They were mixed at a ratio of 6:1. Subsequently, the silicon nitride film 11 was etched with a spacing of 20 m in Freon gas plasma. In addition. When hot phosphoric acid is used to etch the silicon nitride film, the photoresist film is also removed, but when plasma etching is performed, it is possible to leave the photoresist film. After etching the silicon nitride film, the side surfaces of the SiO2 film 12 are etched using the hydrofluoric acid-based etching solution using the photoresist film 13 as a mask, thereby forming a small SiO2 film once on the silicon nitride film. Specifically, it is etched for 4 minutes using the above etching solution to make it 2 μm smaller than the silicon nitride film. Note that during this etching, the thermal oxide film 10 on the silicon nitride film 11 is also etched at the same time, but the etching speed is slow (χ1000X/=
), the lateral spread D is very small. In Figure c, after removing the photoresist film 13, the silicon surface was etched to a depth of 0.7 μm in a potassium hydroxide solution (40%) at 25°C, and then etched in oxygen containing water vapor at 1000°C for 16 hours. This is the area where a thermal oxide film 14 of 1.8 μm was formed by oxidation.

酸化後、酸化のマスクとして用いた窒化珪素膜11をS
iO2膜12をマスクにしてエツチングするとパターン
の周辺で窒化珪素膜が露出している領域のみ除去するこ
とができる。次にその下の熱酸化膜10をエツチングし
.ボロンの拡散層15を形成すると同図dの形になる。
第4図eはSlO2膜12、窒化珪素膜11.熱酸化膜
10を除去し.一般的な方法でペース層16とエミツタ
層17をポロンおよびリンの拡散によつて形成した所で
ある。
After oxidation, the silicon nitride film 11 used as an oxidation mask is
By etching using the iO2 film 12 as a mask, only the exposed area of the silicon nitride film around the pattern can be removed. Next, the thermal oxide film 10 underneath is etched. When the boron diffusion layer 15 is formed, the shape becomes as shown in the figure d.
FIG. 4e shows the SlO2 film 12, the silicon nitride film 11. The thermal oxide film 10 is removed. The paste layer 16 and emitter layer 17 are formed by diffusion of poron and phosphorus using a conventional method.

このあと図には示していないが電極を形成すると深い拡
散層15によつて周辺を保護されたトランジスタを形成
することができる。なお、ここでは説明を簡単にするた
めに単体のトランジスタの場合を述べたが.集積回路(
工C)や大規模集積回路(LSI)にも本発明を適用で
きることは言ラまでもない。
After this, although not shown in the figure, by forming electrodes, a transistor whose periphery is protected by the deep diffusion layer 15 can be formed. Note that here, to simplify the explanation, we have described the case of a single transistor. Integrated circuit (
It goes without saying that the present invention can also be applied to engineering C) and large-scale integrated circuits (LSI).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来法によるトランジスタの平面図.第2図、
第3図は従来法の問題点を説明するための平面図および
断面図.第4図a−eは本発明を説明するための断面図
である。
Figure 1 is a plan view of a conventional transistor. Figure 2,
Figure 3 is a plan view and a cross-sectional view to explain the problems of the conventional method. FIGS. 4a-4e are cross-sectional views for explaining the present invention.

Claims (1)

【特許請求の範囲】 1 下記工程を含む半導体装置の製造方法(1)シリコ
ン基板の表面上に、熱酸化膜、窒化珪素膜およびSiO
_2膜を積層して被着する工程。 (2)所望の形状を有するマスクを用いて、上記SiO
_2膜と上記窒化珪素膜の露出された部分を除去する工
程。(3)上記熱酸化膜の露出部分を除去するとともに
、上記SiO_2膜をサイドエッチする工程。 (4)上記窒化珪素膜を用いて上記シリコン基板の表面
を酸化して厚い熱酸化膜を形成する工程。(5)上記S
iO_2膜をマスクに用いて、上記窒化珪素膜と上記熱
酸化膜の露出部分を除去して上記シリコン基板の表面を
露出させた後、露出された部分からシリコン基板内に不
純物を導入して深い拡散層を形成する工程。(6)上記
SiO_2膜、上記窒化珪素膜および上記熱酸化膜を除
去した後、互に導電形が異なる不純物を上記シリコン基
板の露出された部分に順次導入してベースおよびエミッ
タを形成する工程。
[Claims] 1. A method for manufacturing a semiconductor device including the following steps (1) A method for manufacturing a semiconductor device including the following steps: (1) forming a thermal oxide film, a silicon nitride film and an SiO
_2 The process of laminating and depositing films. (2) Using a mask having a desired shape, the SiO
A step of removing the exposed portions of the _2 film and the silicon nitride film. (3) A step of removing the exposed portion of the thermal oxide film and side-etching the SiO_2 film. (4) A step of oxidizing the surface of the silicon substrate using the silicon nitride film to form a thick thermal oxide film. (5) Above S
Using the iO_2 film as a mask, the exposed parts of the silicon nitride film and the thermal oxide film are removed to expose the surface of the silicon substrate, and then impurities are introduced into the silicon substrate from the exposed parts to form a deep layer. Step of forming a diffusion layer. (6) After removing the SiO_2 film, the silicon nitride film, and the thermal oxide film, a step of sequentially introducing impurities having different conductivity types into the exposed portion of the silicon substrate to form a base and an emitter.
JP3906675A 1975-04-02 1975-04-02 Manufacturing method of semiconductor device Expired JPS5912020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3906675A JPS5912020B2 (en) 1975-04-02 1975-04-02 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3906675A JPS5912020B2 (en) 1975-04-02 1975-04-02 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS51114881A JPS51114881A (en) 1976-10-08
JPS5912020B2 true JPS5912020B2 (en) 1984-03-19

Family

ID=12542744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3906675A Expired JPS5912020B2 (en) 1975-04-02 1975-04-02 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5912020B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109486A (en) * 1977-03-07 1978-09-25 Mitsubishi Electric Corp Manufacture for semiconductor element
JPS5676566A (en) * 1979-11-28 1981-06-24 Fujitsu Ltd Manufacture of semiconductor device
JPS575358A (en) * 1980-06-13 1982-01-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS575357A (en) * 1980-06-13 1982-01-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS5818962A (en) * 1981-07-27 1983-02-03 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPS51114881A (en) 1976-10-08

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