JPH01222448A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01222448A JPH01222448A JP4898288A JP4898288A JPH01222448A JP H01222448 A JPH01222448 A JP H01222448A JP 4898288 A JP4898288 A JP 4898288A JP 4898288 A JP4898288 A JP 4898288A JP H01222448 A JPH01222448 A JP H01222448A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- semiconductor device
- dry etching
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 150000003016 phosphoric acids Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に半導体装
置の配線段切れ防止のための下地平坦化に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to flattening a base for preventing wiring breaks in a semiconductor device.
従来の技術としては半導体基板上に多結晶シリコン膜を
形成し、異方性ドライエツチング装置により垂直に多結
晶シリコン膜をエツチングし、しかる後にリンけい酸ガ
ラス膜を形成し熱処理を行い、リンけい酸ガラス膜をフ
ローさせ半導体装置表面の平坦化を実現していた。Conventional technology involves forming a polycrystalline silicon film on a semiconductor substrate, vertically etching the polycrystalline silicon film using an anisotropic dry etching device, and then forming a phosphosilicate glass film and performing heat treatment to remove the phosphosilicate. Planarization of the surface of semiconductor devices was achieved by flowing an acid glass film.
上述した従来の方法においては、フローしたリンけい酸
ガラス膜上に配線用のアルミを配置すると、アルミが半
導体装置を使用中に腐食さｈてしまりという欠点がある
。その原因は水分が半導体装置へ侵入し、下部のリンけ
い酸ガラス膜中のリンと反応しリン酸が生成される。こ
のリン酸と配線用のアルミが反応しアルミは腐食される
ためである。The conventional method described above has the disadvantage that if aluminum for wiring is placed on the flowed phosphosilicate glass film, the aluminum will corrode during use of the semiconductor device. The reason for this is that moisture enters the semiconductor device and reacts with phosphorus in the phosphosilicate glass film below, producing phosphoric acid. This is because this phosphoric acid reacts with aluminum for wiring, corroding the aluminum.
上述した従来の方法に対し、本発明は半導体装置の下地
平坦化を実現するに際し、アルミを腐蝕させる原因とな
る高リン濃度のリンけい酸ガラス膜を使用しないという
相違点をもつ。The present invention differs from the above-described conventional method in that it does not use a phosphosilicate glass film with a high phosphorus concentration, which causes corrosion of aluminum, when realizing the planarization of the base of a semiconductor device.
本発明による下地平坦化を実現するための手段としては
、半導体基板上に多結晶シリコン膜を形成し、所定のパ
ターンにエツチングする工程において、等方的にドライ
エツチングを行い、しかる後に異方的にエツチングを行
うという工程を有する。As a means for achieving base planarization according to the present invention, in the step of forming a polycrystalline silicon film on a semiconductor substrate and etching it into a predetermined pattern, dry etching is performed isotropically, and then anisotropically etched. The process includes etching.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明による半導体装置の製造方法の実施例の
縦断面図である。先ず従来の方法により半導体基板４上
にゲート酸化膜３を形成し、不純物として厚さ０．６μ
のリンをドープした多結晶シリコン膜２をゲート酸化膜
３上に形成する。その上にフォトレジスト１を所定の位
置へ形成しくＡ）、等方性ドライエツチング装置により
、リンをドープされた多結晶シリコン膜２を０．３μエ
ツチングする（Ｂ）。しかる後辷異方性ドライエツチン
グ装置により残膜０．３μをエツチングする（Ｃ）。次
にフォトレジストを剥離し不純物としてＡｓをイオン注
入法で形成し熱処理を行った後ＣＶＤ法で酸化膜５を形
成する。これにより平坦な表面が形成され、以降通常の
方法に従いアルミ配線を形成し完了である（Ｄ）。FIG. 1 is a longitudinal sectional view of an embodiment of the method for manufacturing a semiconductor device according to the present invention. First, a gate oxide film 3 is formed on a semiconductor substrate 4 by a conventional method, and a 0.6 μm thick film is added as an impurity.
A polycrystalline silicon film 2 doped with phosphorus is formed on the gate oxide film 3. A photoresist 1 is formed thereon at a predetermined position (A), and the polycrystalline silicon film 2 doped with phosphorus is etched by 0.3 μm using an isotropic dry etching device (B). A remaining film of 0.3 μm is etched using a backward anisotropic dry etching device (C). Next, the photoresist is peeled off, As is formed as an impurity by ion implantation, heat treatment is performed, and then an oxide film 5 is formed by CVD. As a result, a flat surface is formed, and aluminum wiring is then formed according to the usual method (D).
以上説明したように本発明は、層間絶縁膜である酸化膜
５を形成する前に段差の原因となっている多結晶シリコ
ン膜の角を２段階エツチングにより取り除くことにより
、配線用アルミの断線を防ぐための下地平坦化を実現し
ており、従来の方法で使用していた高リン濃度のリンけ
い酸ガラスを使用による配線用アルミニウムの腐蝕を防
止できる効果がある。As explained above, the present invention prevents disconnection of aluminum for wiring by removing the corners of the polycrystalline silicon film, which are the cause of steps, by two-step etching before forming the oxide film 5, which is an interlayer insulating film. This has the effect of preventing corrosion of aluminum for wiring due to the use of phosphosilicate glass with a high phosphorus concentration, which was used in the conventional method.
第１図は本発明による半導体装置の製造方法の実施例の
縦断面図である。
１・・・・・・フォトレジスト、２・・・・・・多結晶
シリコン膜、３・・・・・・ゲート酸化膜、４・・・・
・・半導体基板、５・・・・・・酸化膜、６・・・・・
・不純物拡散層。
代理人 弁理士 内 原 音FIG. 1 is a longitudinal sectional view of an embodiment of the method for manufacturing a semiconductor device according to the present invention. 1... Photoresist, 2... Polycrystalline silicon film, 3... Gate oxide film, 4...
...Semiconductor substrate, 5... Oxide film, 6...
・Impurity diffusion layer. Agent Patent Attorney Oto Uchihara
Claims (1)
ターンにエッチングする工程において、等方的にドライ
エッチングを行い、しかる後に異方的にドライエッチン
グを行う工程を含むことを特徴とする半導体装置の製造
方法。A semiconductor device characterized in that the step of forming a polycrystalline silicon film on a semiconductor substrate and etching it into a predetermined pattern includes a step of performing isotropic dry etching and then performing anisotropic dry etching. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4898288A JPH01222448A (en) | 1988-03-01 | 1988-03-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4898288A JPH01222448A (en) | 1988-03-01 | 1988-03-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01222448A true JPH01222448A (en) | 1989-09-05 |
Family
ID=12818448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4898288A Pending JPH01222448A (en) | 1988-03-01 | 1988-03-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01222448A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4212494A1 (en) * | 1991-04-17 | 1992-10-22 | Mitsubishi Electric Corp | Producing isolated semiconductor sidewall for MOS transistor - using selective isotropic and anisotropic plasma etching of polycrystalline silicon@ and silicon@ isolating layers |
| GB2338105A (en) * | 1997-03-04 | 1999-12-08 | Lg Electronics Inc | A method of making a thin-film transistor |
| US6333518B1 (en) | 1997-08-26 | 2001-12-25 | Lg Electronics Inc. | Thin-film transistor and method of making same |
| US6340610B1 (en) | 1997-03-04 | 2002-01-22 | Lg. Philips Lcd Co., Ltd | Thin-film transistor and method of making same |
-
1988
- 1988-03-01 JP JP4898288A patent/JPH01222448A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4212494A1 (en) * | 1991-04-17 | 1992-10-22 | Mitsubishi Electric Corp | Producing isolated semiconductor sidewall for MOS transistor - using selective isotropic and anisotropic plasma etching of polycrystalline silicon@ and silicon@ isolating layers |
| US5432367A (en) * | 1991-04-17 | 1995-07-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having sidewall insulating film |
| US5541127A (en) * | 1991-04-17 | 1996-07-30 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of sidewall insulating film |
| US6340610B1 (en) | 1997-03-04 | 2002-01-22 | Lg. Philips Lcd Co., Ltd | Thin-film transistor and method of making same |
| GB2338105B (en) * | 1997-03-04 | 2000-04-12 | Lg Electronics Inc | Method of making a thin film transistor |
| GB2338105A (en) * | 1997-03-04 | 1999-12-08 | Lg Electronics Inc | A method of making a thin-film transistor |
| US6548829B2 (en) | 1997-03-04 | 2003-04-15 | Lg Lcd Inc. | Thin-film transistor |
| US6815321B2 (en) | 1997-03-04 | 2004-11-09 | Lg. Philips Lcd Co., Ltd. | Thin-film transistor and method of making same |
| US7176489B2 (en) | 1997-03-04 | 2007-02-13 | Lg. Philips Lcd. Co., Ltd. | Thin-film transistor and method of making same |
| USRE45579E1 (en) | 1997-03-04 | 2015-06-23 | Lg Display Co., Ltd. | Thin-film transistor and method of making same |
| USRE45841E1 (en) | 1997-03-04 | 2016-01-12 | Lg Display Co., Ltd. | Thin-film transistor and method of making same |
| US6333518B1 (en) | 1997-08-26 | 2001-12-25 | Lg Electronics Inc. | Thin-film transistor and method of making same |
| US6573127B2 (en) | 1997-08-26 | 2003-06-03 | Lg Electronics Inc. | Thin-film transistor and method of making same |
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