JPS5980942A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5980942A JPS5980942A JP19155982A JP19155982A JPS5980942A JP S5980942 A JPS5980942 A JP S5980942A JP 19155982 A JP19155982 A JP 19155982A JP 19155982 A JP19155982 A JP 19155982A JP S5980942 A JPS5980942 A JP S5980942A
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxide film
- thermal oxide
- groove
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法に関し、特に集積化半
導体装置の能動領域を決定する素子分離領域（フィール
ド領域）の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an element isolation region (field region) that determines the active region of an integrated semiconductor device.
従来例の構成とその問題点
半導体装置の能動領域とフィールド領域の分離は、従来
、窒化硅素膜（ｓ １３Ｎ４）をマスクとして半導体基
板の所定領域を選択的に酸化する方法がよく用いられて
いる。しかしながら、この方法では選択酸化することに
より上述のフィールド領域をなす酸化膜がＳｉ３Ｎ４膜
直下の能動領域形成予定個所にくい込む現象、いわゆる
バーズビークが発生して、素子分離領域の微細化が困難
となってくる。Conventional configuration and its problems Conventionally, the active region and field region of a semiconductor device are separated by a method of selectively oxidizing a predetermined region of a semiconductor substrate using a silicon nitride film (S13N4) as a mask. . However, in this method, selective oxidation causes the oxide film forming the above-mentioned field region to embed in the area directly under the Si3N4 film where the active region is planned to be formed, a so-called bird's beak, which makes it difficult to miniaturize the element isolation region. come.
発明の目的
本発明は、フィールド領域を拡が９に形成し素子分離領
域の微細化を図る半導体装置の製造方法を提供すること
を目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a field region is formed to have a diameter of 9 and an element isolation region is miniaturized.
発明の構成
本発明は、半導体基板の素子分離領域に相当する箇所に
所定濃度の高濃度不純物拡散領域を形成した後、この領
域内に自己整合的にＵ字形の溝を形成し、その後塗布絶
縁物によシ、前記溝を埋め込みフィールド領域を形成す
ることを特徴とするものである。これにより、フィール
ド領域がＵ字溝に限定され、微細化を達成できる。Structure of the Invention The present invention involves forming a high-concentration impurity diffusion region of a predetermined concentration in a location corresponding to an element isolation region of a semiconductor substrate, and then forming a U-shaped groove in a self-aligned manner within this region, and then coating insulation. Another feature is that the trench is buried to form a field region. Thereby, the field region is limited to the U-shaped groove, and miniaturization can be achieved.
実施例の説明 本発明の方法を実施例を基に説明する。Description of examples The method of the present invention will be explained based on examples.
第１図〜第６図に本発明を実現する製造過程断面図を示
す。1 to 6 show cross-sectional views of the manufacturing process for realizing the present invention.
まず、半導体Ｐ型基板１に、高温酸化雰囲気中で厚さ３
０００人の熱酸化膜２を形成する（第１図）。First, a semiconductor P-type substrate 1 is coated with a thickness of 3 mm in a high temperature oxidizing atmosphere.
A thermal oxide film 2 of 1,000 mm is formed (FIG. 1).
この後、所定形状のフォトレジストパターン３を形成し
、フォトレジストパターン３をマスクに、熱酸化膜２を
フレオン系ガスを用いるドライエッチ法によシ選択除去
する。続いて、フォトレジスト３と熱酸化膜２をマスク
に、不純物としてホウ素をイオン注入し、注入領域４を
形成する（第２図）。この後、フォトレジスト３を除去
し、熱処理により注入不純物の活性化を施こし、高濃度
拡散層６を形成する（第３図）。ここで、拡散層５はチ
ャ７ネルストツパーとして用いられる。その後、熱酸化
膜２をマスク熱酸化膜２をマスクにして半導体基板１を
、塩素系ガスによｐｅｏｏｏ人の深さまで異方性エツチ
ング処理を施こし、溝６を形成する（第４図）０この後
、シラノール系の塗図）。シラノール系の塗布絶縁膜７
は、シラノールまたはシラノール誘導体を含む塗布液を
被膜を形成し、ついで、クラックの発生を防ぐため１０
０℃以下の低温処理を行い、３００℃で３０分の熱処理
を施こした後、９００°Ｃの高温で完全にガラス化させ
る。その後、フッ酸系水溶液により、能動領域の塗布絶
縁膜及び熱酸化膜２を除去する。第６図は、この状態を
示し、素子分離領域が形成された図であシ、本実施例に
よる方法では、所定寸法の素子分離領域が形成されてお
り、半導体基板面も平坦化がなされる。Thereafter, a photoresist pattern 3 having a predetermined shape is formed, and using the photoresist pattern 3 as a mask, the thermal oxide film 2 is selectively removed by a dry etching method using Freon gas. Subsequently, using the photoresist 3 and the thermal oxide film 2 as a mask, boron ions are implanted as an impurity to form an implanted region 4 (FIG. 2). Thereafter, the photoresist 3 is removed, and the implanted impurities are activated by heat treatment to form a high concentration diffusion layer 6 (FIG. 3). Here, the diffusion layer 5 is used as a channel stopper. Thereafter, using the thermal oxide film 2 as a mask, the semiconductor substrate 1 is subjected to anisotropic etching treatment using chlorine-based gas to a depth of 100 cm to form a groove 6 (FIG. 4). 0 After this, silanol-based coating). Silanol-based coating insulating film 7
In this method, a coating solution containing silanol or a silanol derivative is applied to form a film, and then 10%
After performing a low temperature treatment at 0°C or lower and heat treatment at 300°C for 30 minutes, it is completely vitrified at a high temperature of 900°C. Thereafter, the applied insulating film and thermal oxide film 2 in the active area are removed using a hydrofluoric acid solution. FIG. 6 shows this state and is a diagram in which an element isolation region is formed. In the method according to this embodiment, an element isolation region of a predetermined size is formed, and the semiconductor substrate surface is also flattened. .
発明の効果
本発明の方法によれば、従来の選択酸化法で不可避であ
ったいわゆるバーズビーク現象による素子分離領域の拡
がりは全くなく、半導体基板に形成された溝により素子
分離領域の寸法が規定される。たとえば、本発明による
方法では素子分離領域の寸法変化が測定誤差内の変化で
あった。Effects of the Invention According to the method of the present invention, there is no expansion of the device isolation region due to the so-called bird's beak phenomenon, which is unavoidable in conventional selective oxidation methods, and the dimensions of the device isolation region are defined by the grooves formed in the semiconductor substrate. Ru. For example, in the method according to the present invention, the dimensional change of the element isolation region was a change within the measurement error.
第１図〜第６図は本発明に係る半導体装置の製造方法の
製造工程断面図である。
１・・・・・・半導体基板、２・・・・・・熱酸化膜、
３・・・・・・フォトレジスト、４・・・・・・塗布絶
縁膜、６・・・・・・高濃度拡散層、６・・・・・・選
択酸化膜０1 to 6 are cross-sectional views of the manufacturing process of the method for manufacturing a semiconductor device according to the present invention. 1... Semiconductor substrate, 2... Thermal oxide film,
3...Photoresist, 4...Coating insulating film, 6...High concentration diffusion layer, 6...Selective oxide film 0
Claims (1)
高濃度不純物拡散領域を形成する工程と。 前記不純物拡散領域内に溝を形成する工程と、前記溝を
塗布絶縁物にて埋め込む工程を含むことを特徴とする半
導体装置の製造方法。 （２）塗布絶縁物がシラノール、またはシラノール誘導
体を含む塗布液で回転塗布で形成されることを特徴とす
る特許請求の範囲第１項に記載の半導体装置の製造方法
。[Claims] ≦ (1) A step of selectively forming a high concentration impurity diffusion region of the same conductivity type as the substrate on the main surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the steps of: forming a groove in the impurity diffusion region; and filling the groove with a coated insulator. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the coated insulator is formed by spin coating with a coating liquid containing silanol or a silanol derivative.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19155982A JPS5980942A (en) | 1982-10-29 | 1982-10-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19155982A JPS5980942A (en) | 1982-10-29 | 1982-10-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5980942A true JPS5980942A (en) | 1984-05-10 |
Family
ID=16276681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19155982A Pending JPS5980942A (en) | 1982-10-29 | 1982-10-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5980942A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5118636A (en) * | 1987-11-11 | 1992-06-02 | Seiko Instruments Inc. | Process for forming isolation trench in ion-implanted region |
| KR100355870B1 (en) * | 1999-06-02 | 2002-10-12 | 아남반도체 주식회사 | Shallow trench isolation manufacturing method of semiconductor devices |
-
1982
- 1982-10-29 JP JP19155982A patent/JPS5980942A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5118636A (en) * | 1987-11-11 | 1992-06-02 | Seiko Instruments Inc. | Process for forming isolation trench in ion-implanted region |
| KR100355870B1 (en) * | 1999-06-02 | 2002-10-12 | 아남반도체 주식회사 | Shallow trench isolation manufacturing method of semiconductor devices |
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