JPH11186264A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve wiring in step coverage on a contact hole. SOLUTION: An interlayer insulating film 2 which contains 1 impurities such as 2.5% boron and 6.0% phosphorus is formed on a semiconductor substrate 1, and then the semiconductor substrate is thermally treated in an atmosphere of N2 gas at a temperature of 800 to 900 deg.C for 100 minutes to make the insulating film 2 flat. By this setup, impurities are discharged out through the surface of the interlayer insulating film 2, and an impurity concentration distribution is so formed as to decrease as it approaches the surface of the film 2. Then, a photoresist film 3 is applied to the interlayer insulating film 2a, and only a part of the photoresist film 3 where a contact hole is formed is removed by a photoetching technique. Then, a uniform and gentle slope is provided to the interlayer insulating film 2 by isotropic etching. Next, a contact hole 4 with a smooth inner wall is formed by anisotropic etching. Then, the photoresist film 3 is removed, and a wiring 5 is formed on the interlayer insulating film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having an interlayer insulating film and a contact hole.

[0002]

2. Description of the Related Art In forming a contact hole, a contact hole formed only by isotropic etching using a chemical solution or the like has poor dimensional accuracy, while it is formed only by anisotropic etching using a dry etch or the like. In the case of a contact hole, there is a problem that the step coverage of the wiring formed thereon is poor. Therefore, in the conventional semiconductor device manufacturing process, two-stage etching is generally used for the purpose of ensuring the dimensional accuracy of the contact hole and improving the step coverage of the wiring. The two-step etching means that in an interlayer insulating film, first, the dimension of an opening on the surface is increased by isotropic etching, and the inner wall of the opening is inclined to increase the step coverage of the wiring, and then the anisotropic etching is performed. This is a method for ensuring the dimensional accuracy of the contact hole by reactive etching.

A conventional method of manufacturing a semiconductor device is shown in FIG.
This will be described with reference to (a) to (f). FIG.
(F) is a process flow chart showing a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 3A, after an interlayer insulating film 2 containing impurities such as boron and phosphorus is formed on a semiconductor substrate 1 by normal pressure CVD or the like, (H ₂ + O ₂ ) Atmosphere and 800-900
Heat treatment is performed at a temperature of ° C. Next, as shown in FIG. 3B, after a photoresist film 3 is applied on the interlayer insulating film 2, a contact hole is formed in the applied photoresist film 3 by a photolithography technique. Remove only the parts that should be.

Next, as shown in FIG. 3C, wet etching using a chemical solution, that is, isotropic etching is performed. In the interlayer insulating film 2, the depth dimension of the etched portion is A, and the erosion dimension in the lateral direction from the periphery of the opening in the lower part of the periphery of the opening of the photoresist film 3 is B. Since the isotropic etching is performed, the portion of the interlayer insulating film 2 below the photoresist film 3 outside the periphery of the opening of the photoresist film 3 is also eroded, and A = B.

[0005] Next, as shown in FIG. 3 (d), anisotropic etching such as dry etching is performed to complete the contact hole 4. Since the anisotropic etching has been performed, only the lower part of the opening of the photoresist film 3 in the interlayer insulating film 2 is etched. Contact hole 4
A first contact portion 4a intersecting the upper surface of the interlayer insulating film 2, a second contact portion 4b intersecting the surfaces respectively formed by isotropic etching and anisotropic etching, and a semiconductor substrate 1 And the third contact portion 4c intersecting with the surface of the third contact portion 4c. Therefore, contact hole 4
The first contact portion 4a and the second contact portion 4b
Is formed by isotropic etching using a chemical solution or the like, and between the second contact portion 4b and the third contact portion 4c is formed by anisotropic etching using dry etching or the like.

Next, as shown in FIG. 3E, the photoresist film 3 is removed. Next, as shown in FIG. 3F, wirings 5 are formed using aluminum or the like on portions where the semiconductor substrate 1 and the interlayer insulating film 2 are respectively exposed.
The step coverage of the wiring 5 is affected by the cross-sectional shape of the contact hole 4.

[0007]

However, according to the above-described conventional manufacturing method, edges occur at the first contact portion 4a and the second contact portion 4b on the inner wall of the contact hole 4, respectively. As a result of investigating the cause of the occurrence of such an edge, the following knowledge was obtained. That is, since the interlayer insulating film 2 is planarized in the (H ₂ + O ₂ ) atmosphere, a dense layer is formed on the surface of the interlayer insulating film 2. For this reason, 800-900 ° C
Even when the planarization treatment is performed by heat treatment at a high temperature, impurities such as boron and phosphorus contained in the interlayer insulating film 2 are not released outside the film due to the formed layer. The concentration distribution of the impurity at the bottom and the bottom is uniform. Since the etch rate in wet etching depends on the impurity concentration and the impurity concentration is uniform, in the etching for forming the contact hole 4, the interlayer insulating film 2 is formed in the vertical direction (thickness direction) and the horizontal direction. Etching with equal dimensions, ie, isotropic etching. Therefore, the inner wall of the contact hole 4 is steeply inclined, and edges are easily generated in the first contact portion 4a and the second contact portion 4b. Due to the generated edge, the step coverage of the wiring 5 on the interlayer insulating film 2 is deteriorated, so that the reliability of the wiring 5 such as disconnection occurs.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a manufacturing method for forming a contact hole having a gentle slope and having no edge to realize a semiconductor device having good wiring step coverage. Aim.

[0009]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: releasing an impurity from the surface of an interlayer insulating film; The structure includes a step of forming a concentration distribution such that the concentration of the impurity decreases as approaching the surface.

According to this structure, by providing a difference in impurity concentration in the thickness direction of the interlayer insulating film, the etch rate of wet etching can be changed in the thickness direction.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to first to third embodiments of the present invention will be described with reference to FIGS. 1 (a) to 1 (f) and FIG. 1A to 1F are process flow charts showing a method for manufacturing a semiconductor device according to each embodiment of the present invention.

A first embodiment of the present invention will be described. First, as shown in FIG. 1A, an interlayer insulating film 2 containing impurities such as boron 2.5% and phosphorus 6.0% is formed on a semiconductor substrate 1 by normal pressure CVD or the like. After that, a heat treatment is performed for 100 minutes at a temperature of 800 to 900 ° C. in an N ₂ gas atmosphere for planarization.

The impurity concentration of the interlayer insulating film 2 subjected to such a high-temperature heat treatment was examined. FIG. 2 is an explanatory diagram showing the relationship between the depth from the surface of the interlayer insulating film 2 and the impurity concentration. As shown in FIG. 2, the distribution of the impurity concentration of the interlayer insulating film 2 was low at the surface and increased as the depth from the surface increased to reach the original value. This tendency was more pronounced in boron than in phosphorus.
It is considered that the relationship shown in FIG. 2 is the result of impurities being released from the surface of the interlayer insulating film 2 to the outside of the film by the high-temperature heat treatment.

Next, as shown in FIG. 1B, after a photoresist film 3 is applied on the interlayer insulating film 2, a contact hole in the applied photoresist film 3 is formed by photolithography. Remove only the parts that should be formed.
Next, as shown in FIG. 1 (c), for example, the capacity ratio of NH ₄
F : Wet etching, that is, isotropic etching, with a chemical solution such as buffered hydrofluoric acid with HF = 20: 1. In this case, the interlayer insulating film 2 has the impurity concentration distribution shown in FIG. 2, and the etch rate in wet etching is higher as the impurity concentration, particularly the boron concentration, is lower, and the etch rate is lower as the boron concentration is higher. Therefore, the extent of etching differs in the thickness direction and the lateral direction. Assuming that the etching depth dimension is A and the lateral erosion dimension of the interlayer insulating film 2 below the photoresist film 3 is B, A <B. Therefore, a uniform and gentle slope is formed by wet etching, that is, isotropic etching.

Next, as shown in FIG. 1D, the contact hole 4 is completed by performing anisotropic etching such as dry etching. Since the anisotropic etching has been performed, only the lower part of the opening of the photoresist film 3 in the interlayer insulating film 2 is etched. Contact hole 4
A first contact portion 4a intersecting the upper surface of the interlayer insulating film 2, a second contact portion 4b intersecting the surfaces respectively formed by isotropic etching and anisotropic etching, and a semiconductor substrate 1 And the third contact portion 4c intersecting with the surface of the third contact portion 4c. Therefore, contact hole 4
The first contact portion 4a and the second contact portion 4b
Is formed by isotropic etching using a chemical solution or the like, and between the second contact portion 4b and the third contact portion 4c is formed by anisotropic etching using dry etching or the like. In this case, since the inclination formed by the isotropic etching is uniform and gentle, the first contact portion 4a
No edge is generated between the first contact portion and the second contact portion 4b, so that the contact hole 4 having a smooth inner wall is completed.

Next, as shown in FIG. 1E, the photoresist film 3 is formed by a known method, for example, a method of sequentially performing dry etching with O ₂ plasma or the like, wet etching with fuming nitric acid, and washing with water. Remove. Next, FIG.
As shown in (f), wirings 5 are formed using aluminum or the like on portions where the semiconductor substrate 1 and the interlayer insulating film 2 are exposed. In this case, since the inner wall of the contact hole 4 has a smooth shape, there is no fear of disconnection in the wiring 5. According to the present embodiment, a good step coverage of 35 to 40% can be realized with respect to the step coverage of 25 to 30% according to the conventional technique.

In the description of this embodiment, N ₂ gas is used in the planarization of the interlayer insulating film 2. Not limited to this, the same effect can be obtained as long as the gas can activate the release of boron, such as H ₂ gas, a rare gas such as Ar gas or He gas, or an acid gas such as HCl. In consideration of the above, N ₂ gas is most preferable. The same effect can be obtained in an atmosphere of N ₂ gas, H ₂ gas, a rare gas such as Ar gas or He gas, an acid gas such as HCl, or the like, and under reduced pressure. Further, in the description of the present embodiment, the condition of the heat treatment in the flattening process of the interlayer insulating film 2 is set at 100 to 800 ° C.
Minutes. This processing condition is a condition generally used in a manufacturing process of a semiconductor device, and is not limited to this, as long as it is a temperature and a time at which boron is released. The concentration distribution of the interlayer insulating film 2 can be arbitrarily set by appropriately changing the conditions of the flattening process, that is, the type, temperature, or processing time of the gas.

A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. In the second embodiment, the flattening process is performed in a vacuum instead of performing the flattening process of the interlayer insulating film 2 in an N ₂ gas atmosphere in the first embodiment. First, as shown in FIG.
An interlayer insulating film 2 containing impurities such as boron 2.5% and phosphorus 6.0% is formed on the semiconductor substrate 1 by VD or the like. After that, in a vacuum and 80
A heat treatment is performed at a temperature of 0 to 900 ° C. for 100 minutes. By performing the heat treatment at a high temperature in a vacuum, impurities are actively released from the surface of the interlayer insulating film 2 to the outside of the film. As a result, the impurity concentration of the interlayer insulating film 2 becomes
As shown in FIG. 2, a distribution is formed such that it is low on the surface and increases as the depth increases, reaching the original value.

Hereinafter, as in the first embodiment, FIG.
As shown in (b) to (f), a contact hole 4 and a wiring 5 are sequentially formed. Since the inner wall of the contact hole 4 has a smooth shape, there is no fear of disconnection in the wiring 5.
According to the present embodiment, a good step coverage of 35 to 40% can be realized with respect to the step coverage of 25 to 30% according to the conventional technique.

In the description of the present embodiment, the flattening process of the interlayer insulating film 2 is performed in a vacuum. However, the same effect can be realized even under a reduced pressure in the atmosphere as long as the conditions for activating boron release can be achieved. it can. In the description of the present embodiment, the condition of the heat treatment in the planarization of the interlayer insulating film 2 is set to a temperature of 800 to 900 ° C. for 100 minutes. This condition is a condition generally used in a manufacturing process of a semiconductor device, and is not limited to a temperature and a time at which boron is released. The concentration distribution of the interlayer insulating film 2 can be arbitrarily set by appropriately changing the conditions of the flattening process, that is, the degree of vacuum, the temperature, or the processing time.

A method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described. First, as shown in FIG. 1A, an interlayer insulating film 2 containing impurities such as boron 2.5% and phosphorus 6.0% is formed on a semiconductor substrate 1 by normal pressure CVD or the like. After that, (H
₂ + O ₂ ) After a heat treatment for 100 minutes in an atmosphere at a temperature of 800 to 900 ° C.,
In hot water for 60 minutes.

The impurity concentration of the interlayer insulating film 2 subjected to such a high-temperature heat treatment was examined. As a result, as shown in FIG. 2, the impurity concentration of the interlayer insulating film 2 was low at the surface, and increased as the depth from the surface increased, and reached the original value. The relationship shown in FIG. 2 shows that the interlayer insulating film 2
This is considered to be the result of impurities being released from the surface of the film to the outside of the film.

Hereinafter, in the same manner as in the first embodiment, FIG.
As shown in (b) to (f), a contact hole 4 and a wiring 5 are sequentially formed. Since the inner wall of the contact hole 4 has a smooth shape, there is no fear of disconnection in the wiring 5.
According to the present embodiment, a good step coverage of 35 to 40% can be realized with respect to the step coverage of 25 to 30% according to the conventional technique.

In the description of the present embodiment, after the planarization of the interlayer insulating film 2, an immersion process is performed for 60 minutes in hot water at 100 ° C. to form an impurity concentration distribution in the interlayer insulating film 2. did. However, the present invention is not limited to this.
The same effect can be realized by performing immersion treatment using an acid such as l.

In the first to third embodiments described above, the chemical used for isotropic etching is NH ₄ F:
The explanation has been made by taking buffered hydrofluoric acid of HF = 20: 1 as an example. Not limited to this, NH ₄ F, HF, or 2
The same effect can be obtained by using a chemical solution mixed at a ratio other than 0: 1. In the isotropic etching, the shape of the contact hole can be arbitrarily set by changing conditions such as the type of the chemical solution, the concentration of the chemical solution, and the etching time. Also, regarding the method of forming the contact hole,
The two-stage etching using isotropic etching and anisotropic etching has been described as an example. However, the same effect can be obtained without being limited to the two-step etching as long as the method uses isotropic etching in the step of forming a contact hole in the interlayer insulating film containing impurities such as boron and phosphorus. Needless to say.

[0026]

According to the present invention, there is provided a step of forming a concentration distribution in an interlayer insulating film containing impurities such that the concentration of the impurities decreases as approaching the surface. As a result, in the thickness direction of the interlayer insulating film, the etch rate of wet etching is increased at the surface and decreased as the depth increases from the surface, so that a smooth contact hole can be formed. Therefore, it is possible to provide a method of manufacturing a semiconductor device in which the step coverage of wiring is improved.

[Brief description of the drawings]

FIGS. 1A to 1F are process flow charts showing a method for manufacturing a semiconductor device according to each embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a depth from a surface of an interlayer insulating film and an impurity concentration.

FIGS. 3A to 3F are process flow charts showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 interlayer insulating film 3 photoresist film 4 contact hole 4a first contact portion 4b second contact portion 4c third contact portion 5 wiring

Claims (6)

[Claims] An impurity in the interlayer insulating film is released from the surface of the interlayer insulating film to form a concentration distribution in the interlayer insulating film such that the concentration of the impurity decreases as approaching the surface. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the concentration distribution comprises: flattening the interlayer insulating film in an atmosphere comprising a gas for activating emission of the impurities. A method of manufacturing a semiconductor device, comprising a step of performing a chemical treatment. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the concentration distribution is performed in an atmosphere made of a gas for activating emission of the impurities, and the pressure is reduced. A method of manufacturing a semiconductor device, comprising a step of performing a planarization process of the interlayer insulating film in an atmosphere. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the gas is at least one kind of gas selected from N ₂ gas, H ₂ gas, rare gas and acid gas. A method for manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the concentration distribution includes the step of forming the concentration distribution of the interlayer insulating film under a reduced pressure of air or in a vacuum so as to activate the emission of the impurities. A method for manufacturing a semiconductor device, comprising a step of performing a planarization process. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the concentration distribution includes: a step of performing a planarization process on the interlayer insulating film; and after performing the planarization process. Immersing the interlayer insulating film in hot water or an acid.