JPH0329322A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To satisfactorily remove a spontaneous oxide film in a flat part and even in a stepped part by executing a microwave down-flow etching treatment by using a mixed gas of O2 and CF4 whose ratio to the O2 is 20 % or lower. CONSTITUTION:When a ratio of a flow rate of CF4 is larger in the case of a down-flow etching operation using a mixed gas of O2 and CF4, an etch rate of silicon is faster than that of SiO2; when the ratio of the flow rate of CF4 to O2 is 20 % or lower, the etch rate of SiO2 becomes faster than that os silicon. Consequently, silicon is hardly etched in a region where the ratio of the flow rate of CF4 to O2 is 20% or lower; a spontaneous oxide film 15 can be removed. By means of a down-flow system, an isotropic etching operation by a neutral active species can be executed; also the spontaneous oxide film 15 formed on the stepped surface of silicon can be removed. Thereby, the spontaneous oxide film 15 can be removed and, at the same time, a resist can be removed. As a result, the number of processes used to form an SiO2 film mask 14 can be reduced; the treatment time can be shortened; thereby, a process can be simplified and a throughput can be enhanced.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method (pretreatment method) for removing a natural oxide film formed on silicon, the present invention relates to a method for removing a natural oxide film formed on the surface of silicon [ INDUSTRIAL APPLICATION FIELD The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for removing a native oxide film formed on silicon (pretreatment method).

[Conventional technology]

? With the miniaturization of conductor devices, Sing films used as mask materials and insulating films are becoming thinner. therefore,
There is a need for an etching technique that can etch silicon with a high selectivity to Sin2, that is, a technique that can etch polycrystalline silicon, for example, without etching the underlying SiOz. This includes bromine (Brz) or hydrogen bromide (llBr)
A dry etching method for silicon using etching gas is effective.

However, Br. In dry etching using HBr or HBr, the etching speed of Sing is slow, so the silicon surface is oxidized naturally or during the wafer process, and Si
If an O1 film is formed, unless it is removed,
Silicon etching is slow to start. therefore,
It is necessary to remove the native oxide film in advance.

Conventionally proposed methods for this purpose include (1) a physical method in which SiO■ is removed by sputtering using argon (Ar) alone or by adding N2 or the like to Ar; 2) Reactive ion etching (RI) using a combination of chemical and physical methods using a gas mainly containing freon (CF4).
E) Method of removing Si02, (3) I1■
By dissociation using Sin. Among them, 0■ is reacted with H2 and destroyed as 11.0, leaving only St. (4) A method of removing 02 of SiO1 by non-oxidation treatment without oxygen at about 1000'C. Proposed.

? However, in the method (1) of sputtering with Ar, among these conventional methods, not only the natural oxide film but also other parts are sputtered with Ar ions. There is a problem that the machine may be damaged.

The dissociation method using h in (3) is effective when the SiOz film is extremely thin, but has not yet been sufficiently confirmed when the SiOz film is thick. The problem with method (4) is that it uses a high temperature of 1000''C.

In method (2), the SiO film is etched at a rate of 1000 people/mjn? However, since silicon is also etched at approximately the same etching rate, the problem is the amount of silicon etched depending on the etching time. Referring to FIG. 5, a thin S
An i02 film 52 is formed, and an SiO2 film 54 is formed to cover a polycrystalline silicon wiring layer 53 provided thereon.
Sin. Aluminum wiring 56 is connected to polycrystalline silicon wiring layer 53 through opening 55 in film 54 . Before forming the aluminum wiring 56 shown in FIG. 5(a),
), approximately 30 to 50 Sing films, called natural oxide films, formed on the surface of the polycrystalline silicon wiring layer 53 exposed at the openings 55 must be removed. If a natural oxide film is formed as shown in the same figure (C), CF. As shown by the arrow in the figure, RIE mainly uses etching from the surface at the same etching rate, so if you try to completely etch the thick part of the SiO film, polycrystalline silicon will be etched in the thin part of the SiO film. It gets etched.

Also, is there a SiO film 12 with steps on the silicon substrate?
When the polycrystalline silicon layer 13 is etched using the SiO2 film 14 as a mask, the polycrystalline silicon also has a step (FIG. 3). At this time, when a natural oxide film is formed on the polycrystalline silicon surface, the natural oxide film is thicker at the step part than at other parts when viewed from the vertical direction, so it is difficult to
．． It cannot be removed in a short time by RIE. This portion acts as a mask, and the polycrystalline silicon is not etched in the area indicated by the dotted line in the figure, resulting in short circuits between the polycrystalline silicon wirings (FIG. 4).

Furthermore, CF. When natural oxide film removal using IIBr and silicon etching using IIBr are performed in the same reaction chamber,
The remaining CF. The influence of HBr is strong, and the Sin. There is also the problem that high selectivity for ions is lost.

Therefore, Sin. Wet etching using dilute hydrofluoric acid is a method that can remove silicon with a high selectivity to silicon. However, after performing wet etching, water washing and drying processes are required, and the problem is that the natural oxide film is re-formed during these processes.

Therefore, the present invention makes it possible to remove the natural oxide film formed on the surface of silicon, maintain a high selectivity to the underlying oxide film in the subsequent silicon etching, and furthermore, It is an object of the present invention to provide a pretreatment method that can remove a natural oxide film on a silicon surface at the same time as a natural oxide film on a flat part.

? Means for Solving the Problems] The above problem is solved by using oxygen (O2) and oxygen (0
In contrast to 2), using a gas mixture containing 20% or less of Freon (CF4) as an etching gas, microwave downflow etching is performed on the sample with a natural oxide film formed on the silicon layer. The problem is solved by a method of manufacturing a semiconductor device.

? Effect] In the case of downflow etching using a mixed gas of 0■ and CF4, CF. When the flow rate is high, the etching rate of silicon is faster than that of SiOz. In addition, conventional RI
In the mixed gas of 02 and CF4 used in E, both had almost the same etching rate. However, CF. When the flow rate ratio is 20% or less relative to 02, the etching rate of Si02 becomes faster than that of silicon. This relationship is shown in FIG. In addition, the same figure shows the CF for 0■
This is a diagram showing the relationship between etching rate and selectivity (polycrystalline silicon/SiOz) at a mixing ratio of 4. In the diagram, the horizontal axis represents the ratio of CF4 and (CF4+Ot) in %, and the vertical axis represents the left side. Etching speed [on/min]
Also, the right side shows the selectivity ratio of polysilicon/siot.

Connect the square (mouth) sign! 'JB represents the etching rate of polycrystalline silicon, a line C connecting the circles (○) marks represents the etching rate of Sin2, and a line A connecting the triangles (Δ) marks represents the selectivity of polycrystalline silicon to SiO2. The processing conditions at this time are
Microwave output is 400W, pressure is I Torr, stay? The temperature was kept constant at room temperature. Therefore, CF. In a region where the ratio of the flow rate is 20% or less relative to 0, the natural oxide film can be removed without substantially etching silicon. Unlike RIE, the down-flow one-sided method allows isotropic etching using neutral active species, and it is also possible to remove a natural oxide film formed on a silicon surface with steps.

Also, CF. This effect is possible even if the amount of Br. Alternatively, silicon etching using IIBr can be performed with good reproducibility, at high speed, and with a high selectivity.

? Example〕 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

Figure 3 shows a natural oxide film (SiO
Film) 15 is shown. The mask material is SiOz film 14
It is. In the resist mask, the etching speed of the underlying oxide film l2 increases due to the influence of carbon from the resist.
This is because the selectivity with polycrystalline silicon becomes poor. Furthermore, with a resist mask, an oxide film on the surface of polycrystalline silicon can sometimes be removed due to the influence of carbon, so this time a SiOz film mask was used. Therefore, this sample was used in the examples of the present invention. The detailed structure of the sample to be processed is as follows: An SiOz film l2 with a thickness of about 4000 nm is formed on a silicon substrate 11 by thermal oxidation as an insulating film, and a polycrystalline silicon layer l3 with a thickness of about 4000 nm is formed on top of it. Chemical vapor deposition (
It was formed by a CVD method. Furthermore, on top of that, line width 1
Sin2 film mask 14 with a thickness of about 2000 pm
formed a pattern. The resist on the Sing film mask l4 used for pattern formation has already been removed by 02 plasma. The surface of the polycrystalline silicon is oxidized by being exposed to the 02 plasma, and a natural oxide film 15 is formed.

Further, FIG. 4 shows a natural oxide film formed on a silicon surface having steps. This formed SiOzJlil2 with a step on the silicon substrate 11. CVD polycrystalline silicon 13 with a thickness of about 4000 on top of it? It was formed by A natural oxide film 15 is also formed on this polycrystalline silicon surface.
is formed. The mask material was an SiO2 film 14.

A schematic cross-sectional view of an apparatus embodying the present invention is shown in FIG. The left side (a) of the figure is a down-flow etching device that removes natural oxide films, and the right side (b) of the figure is a parallel plate type RIE device that etches silicon. In the figure, 21 is a gas supply port, 22 is a microwave inlet, 23 is a sample, 24 is a monochromator, 25 is a plasma chamber, 26 is a shower head, 27 is a stage (with heater), 28 is a gas exhaust port, 29 is a N2 gas supply port, 30 is a transfer chamber, 31 is a gas exhaust port, 32 and 33 are load locks, 34 is a transfer arm, 35 is a gas supply port, 36 and 36a are insulators, 37 is a high frequency power supply, 38 is an electrostatic chuck, 39 is a He gas supply port, 40 is a direct current output (DC power) power supply, 41 is an etching chamber, 42 is a He gas exhaust port, 43 is a gas exhaust port, 4
4 is a cooling water circulation mechanism. These two devices are connected by a transfer chamber 30 that is evacuated. With this structure, sample 23 from which the natural oxide film was removed is
It is transported to the etching chamber without being exposed to the atmosphere. Furthermore, by providing load locks 32 and 33, C
Fa is in the etching chamber, or vice versa, Brt or HBr.
does not flow into the reaction chamber where pretreatment is performed.

In part (a) of the illustrated apparatus, ions and electrons generated within the plasma chamber 25 are captured by the shower head 26 and do not go to the sample 23 below. Then, the gas containing neutral active species flows downward due to the pressure difference to the sample 23.
and etching is performed.

Next, conditions for downflow etching to remove a native oxide film and conditions for silicon RIE will be shown.

(Downflow etching conditions) Microwave output: 400W Pressure: ITorr stage temperature: 20°C (RIE conditions) RF power: 300W Pressure: 0, I Torr HBr flow rate: 50sccs He gas pressure for cooling: 2Torr Chiller setting temperature: 60°C? Next, using the apparatus shown in Fig. 1 and the sample shown in Fig. 3, downflow etching was actually performed using a mixed gas of 0 and CF4 under the conditions described above, and the natural oxide film formed on the silicon surface was removed. I tried. The stage temperature was kept at 20'C, but the temperature of sample 23 was 20'C+ during etching.
(10-20°C).

? Example 1) The above-described RI
Etching was performed for 5 minutes under E conditions.

As a result, etching of polycrystalline silicon started in some cases and not in others. In the case of the etched sample, the selectivity ratio of polycrystalline silicon to the underlying SiO2 was 100.

However, numerous silicon residues were observed on the underlying Sin2 film. This is because due to the presence of the natural oxide film, if the natural oxide film remains unetched, it acts as a mask and the underlying polycrystalline silicon is not removed.

? Example 2) First, the natural oxide film of the sample shown in FIG. 3 was removed under the down flow etching conditions described above.

The mixing ratio of etching gas at this time is C to 02.
F. was set at 50%. After the native oxide film has been removed, the sample is transported in vacuum to the reaction chamber (b) in Figure I, and this time,
Polycrystalline silicon was etched under the RIE conditions described above. As a result, the polycrystalline silicon was etched in a vertical shape, but the selectivity to the underlying Sint was 17. Base Sin. Silicon residue was observed on the film.

This is because the natural oxide film was not removed properly.

If there is any silicon residue left, it may cause a short circuit, and if over-etching is performed to completely remove it, the underlying SiO2 film will also be excessively etched.

? Example 3) Next, the native oxide film was removed and the polycrystalline silicon was etched in the same manner as in Example 2, using an etching gas mixture ratio of 0 and CF4 of 20%. As a result, the polycrystalline silicon was etched vertically, and the selectivity to the underlying Si (h) was 40. No silicon residue was observed on the underlying Si film.

(Example 4) Next, the native oxide film was removed and polycrystalline silicon was etched in the same manner as in Example 2, using an etching gas mixing ratio of 10% CF4 to Ox. As a result, the polycrystalline silicon was etched vertically, and the selectivity to the underlying SiOz was 80. Base Sin. No silicon residue was observed on the film. (Example 5)? Next, the natural oxide film was removed and the polycrystalline silicon was etched in the same manner as in Example 2, using an etching gas mixture ratio of 02 to 5% CF4. As a result, the polycrystalline silicon was etched vertically, and the selectivity to the underlying Sing was 100. Base Sin. No silicon residue was observed on the film. Incidentally, the present inventor obtained similar results using CF4 of 2% and 1% relative to 0■.

? Example 6) Next, using the sample shown in FIG. 4, the mixing ratio of the etching gas was set to cp. was set at 5%, and the native oxide film was removed and polycrystalline silicon was etched in the same manner as in Example 2. As a result, the polycrystalline silicon is etched vertically,
The selectivity ratio for the underlying SiO2 was 100. No silicon residue was observed on the underlying SiO2 film. This means that in the down-flow etching described above about the equipment, etching progresses not only in the vertical direction but also in the horizontal direction, that is, isotropically, so that the etching of stepped areas is done in the same way as the etching of flat areas. This is due to a number of reasons.

? Effect of the invention] As described above, according to the present invention, 0■ and 20
CF. By performing microwave downflow etching treatment using a mixed gas with High selectivity etching can be maintained.

In the inventor's experiments, the stage temperature was set to room temperature, that is, 2
The above results were obtained by maintaining the temperature at 0°C. For example, it is known that downflow etching is used for resist ashing, but the stage temperature is 1
The temperature must be maintained between 60 and 200"C. The method of the present invention differs from such known techniques in that it can be carried out at room temperature.

Furthermore, according to the present invention, since Ot is in excess, the natural oxide film is removed and the resist is removed at the same time. Since it can be removed, the conventional process of Sing etching → resist ashing → pretreatment → silicon etching for forming a SiO film mask can be replaced with SiOz etching → pretreatment (including resist ashing) → silicon etching. This has the effect of simplifying the process by reducing the number of man-hours and processing time, which greatly improves throughput.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the device used to carry out the present invention, and FIG. 2 is a 0. Fig. 3 is a cross-sectional view of an embodiment of the present invention, and Fig. 4 is a cross-sectional view of an embodiment of the present invention. Cross-sectional view of another embodiment, FIG. 5(a)-
(C) is a cross-sectional view illustrating removal of a natural oxide film. In the figure, 1l is a silicon substrate, 12 is a silicon layer, 13 is a polycrystalline silicon layer, 14 is a Sing film, 15 is a natural oxide film, 21 is a gas supply port, 22 is a microwave inlet, 23 is a sample, 24 is a monochrome Meter 25 is a plasma chamber, 26 is a shower head, 27 is a stage (with heater), 28 is a gas exhaust port, and 29 is an N. Gas supply port, 30 is a transfer chamber, 31 is a gas exhaust port, 32 and 33 are load port vines, 34 is a transfer arm, 35 is a gas supply port, 36 and 36a are insulators, 37 is a high frequency power supply, 3B is an electrostatic A chuck, 39 is a He gas supply port, 40 is a DC power source, 41 is an etching chamber, 42 is a gas exhaust port, 43 is a gas exhaust port, and 44 is a cooling water circulation mechanism.

Claims (1)

[Claims] A natural oxide film (1) formed on the surface of a silicon layer (13).
5) In the pretreatment to remove oxygen (O_2) and Freon (CF_4), which is less than 20% of oxygen (O_2),
) is used as an etching gas to remove the natural oxide film (15) formed on the silicon layer (13).
) A method for manufacturing a semiconductor device, the method comprising performing microwave downflow etching treatment on a sample (23).