JP2003298049A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent residual dross from staying on a gate oxide film, when a semiconductor substrate is worked to form a gate electrode. <P>SOLUTION: A pattern comprising a silicon oxide film and an antireflection film thereon is formed by photoengraving. After wet etching (Wet shrinking) is performed so that a line width of the pattern of the silicon oxide film becomes a width of desired gate electrode, the antireflection film is removed. Thereby reaction products of the antireflection film and a polysilicon film, contributing to the residual dross, are removed together with the anti-reflection film, and residual dross generation is restrained. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an etching process performed when forming a gate electrode and wiring.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional etching process for forming a gate electrode. Figure 4 (a)
It is sectional drawing of the wafer before performing etching. A gate insulating film (SiO ₂ film) on the silicon substrate (not shown)
1 is formed, and on the gate insulating film 1, a polysilicon film 2 serving as a material of a gate electrode is formed. Further, a silicon oxide film (TEOS film) 3 serving as a mask at the time of processing the gate electrode is formed on the polysilicon film 2, and an antireflection film 4 for preventing reflection from a base film during photolithography is formed on the silicon oxide film (TEOS film) 3. Has been formed. A pattern of photoresist 5 is formed on the antireflection film 4.

In the conventional process, the antireflection film 4 and the silicon oxide film 3 are first etched using the pattern of the photoresist 5 as a mask. FIG. 4B is a sectional view of the wafer in a state where the photoresist 5 is removed after the etching of the silicon oxide film 3.

Next, as shown in FIG. 4C, the antireflection film 4 is removed by etching, and the silicon oxide film 3 is thinned by wet etching as shown in FIG. 4D (in this specification). , And hereinafter, this processing is referred to as Wet shrink). Then, the polysilicon film 2 of the electrode material is etched by using the silicon oxide film 3 as a mask to form a gate electrode as shown in FIG.

[0005]

In the conventional process described above, as shown in FIG. 4 (e), after the etching step, the reaction between the antireflection film 4 and the polysilicon film 2 of the electrode material on the gate oxide film 1. The problem is that a residue consisting of the product remains. This is because the presence of the residue has a great influence on the characteristics of the device. Therefore, the present invention proposes a gate electrode forming process for preventing the generation of etching residues.

[0006]

The first method of the present invention comprises:
A semiconductor device in which a gate electrode made of a polysilicon film is formed by processing a semiconductor substrate on which a polysilicon film, a silicon oxide film on the polysilicon film, and an antireflection film on the silicon oxide film are formed. The method of manufacturing, wherein a pattern comprising a silicon oxide film and an antireflection film on the silicon oxide film is formed by photolithography, and the wet process is performed so that the line width of the pattern of the silicon oxide film becomes a desired gate electrode width. The gate electrode is formed by etching, removing the antireflection film, and etching the polysilicon film using the pattern of the silicon oxide film as a mask.

A second method of the present invention is a polysilicon film,
A method of manufacturing a semiconductor device, comprising: processing a semiconductor substrate on which a silicon oxide film on the polysilicon film and an antireflection film on the silicon oxide film are formed to form a gate electrode using the polysilicon film as a material. Then, a pattern consisting of a silicon oxide film and an antireflection film on the silicon oxide film is formed by photolithography, the antireflection film is removed, and the semiconductor substrate is ashed and washed to obtain the line width of the pattern of the silicon oxide film. Is wet-etched to have a desired width of the gate electrode, and the polysilicon film is etched using the pattern of the silicon oxide film as a mask to form the gate electrode.

A third method of the present invention is a polysilicon film,
The silicon oxide film on the polysilicon film, and the silicon oxide film
A semiconductor substrate with an antireflection film on the silicon oxide film
Processed to form a gate electrode made of polysilicon film
A method of manufacturing a semiconductor device, which comprises:
Silicon oxide film and antireflection on the silicon oxide film
A pattern consisting of a film is formed, and an antireflection film is formed with C
_FourF₈, C₅F₈, C_FourF₆And C_ThreeF₆Izu in
Some gas and CF_Four, SF₆, CH_TwoF_Two, CHF _Three
And CH_ThreeD that combines any of the gases in F
Removed by etching with etching gas
The line width of the silicon oxide film pattern is
Wet etching to the width of the
The polysilicon film is etched using the oxide film pattern as a mask.
The gate electrode is formed by etching.
To collect.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a diagram showing a gate electrode forming process in the first embodiment. Figure 1
(A) is a cross-sectional view of the wafer before etching. First, using a vertical oxidation furnace, a gate insulating film (SiO ₂ film) with a thickness of 75 Å is formed on a silicon substrate (not shown).
1 is deposited. Next, a polysilicon film 2 of a gate electrode material is formed on the gate insulating film 1 by vertical low pressure CVD. The thickness of the polysilicon film 2 is about 2000 Å. Further, by vertical low pressure CVD, a silicon oxide film (TEOS film) 3 serving as a mask at the time of processing the gate electrode is formed. The thickness of the silicon oxide film 3 is about 600Å. In addition to the silicon film, the mask material
It may be a silicon nitride film. Next, using a plasma CVD device, an antireflection film (p-SiON film) having a thickness of 500 Å
4 is deposited. Further, a resist 5 is formed on the antireflection film 4.
Is applied for about 4000 Å, exposed and developed to form a resist pattern.

Next, as shown in FIG. 1B, the antireflection film 4 and the silicon oxide film 3 are etched using the resist pattern as a mask. The etching is performed using a dry etching device using plasma. In the present embodiment, the electrodes are parallel plate type and the frequency is R of 400 Hz.
An apparatus equipped with an F power supply was used. The etching gas is CHF ₃ / O ₂ / Ar, CF ₄ / O ₂ / Ar, CH.
It is preferable to use a gas containing F such as F ₃ / CF ₄ / O ₂ / Ar or C ₄ F ₈ / O ₂ / Ar. In the present embodiment, the wafer is transferred to the etching chamber of the apparatus, and CF ₄ / O ₂ / Ar = 60/20 is set in the etching chamber.
The gas is supplied at a ratio of / 800 sccm, and the exhaust gas is adjusted so that the inside of the etching chamber becomes 200 mT.
Turn on 1000 W of power. After the etching is completed, the resist 5 is removed by enzyme plasma using a dry ashing device. In this embodiment mode, the gas is O ₂ / N ₂ = 950/50 s in an ashing device using a microwave.
The resist was ashed at ccm, a pressure of 1 Torr (about 133 Pa), a microwave power of 1.5 kW, and a stage temperature of 250 ° C.

Next, as shown in FIG. 1C, the silicon oxide film 3 serving as a mask when processing the gate electrode is wet-shrinked. That is, the silicon oxide film 3 is etched using a solvent so as to have a desired gate electrode size. For example, when the wafer is placed on a hydrofluoric acid layer having a concentration of 5% for 5 minutes, a gate electrode having a width of 0.18 μm has a width of 0.14 μm.
It becomes the width of μm.

Next, as shown in FIG. 1D, the antireflection film 4 on the mask is removed. Since the antireflection film 4 is a conductive film having a resistance value of several ohms, if this film remains, a short circuit may occur when a transistor is formed. Therefore, the antireflection film 4 must be removed without fail. The antireflection film 4 is etched by using a dry etching apparatus using plasma. In this embodiment,
The apparatus used was a parallel plate type electrode and an RF power source with a frequency of 400 Hz. Also, the etching gas is CH
F ₃ / O ₂ / Ar, CF ₄ / O ₂ / Ar, CHF ₃ / C
It is preferable to use a gas containing F, such as F ₄ / O ₂ / Ar. In the present embodiment, the wafer is transferred to the etching chamber of the apparatus, and CHF ₃ / C is introduced into the etching chamber.
F ₄ / O ₂ / Ar = 10/70/13/800 sccm
Gas is supplied at a ratio of
The exhaust gas is adjusted to T and the RF power source 500W is turned on. At this time, a gas system is selected so that the polysilicon film 2 of the underlying gate electrode is not etched as much as possible. Underlying polysilicon film 2 and antireflection film 4 under the above conditions
The selection ratio of and is about 4.

Then, as shown in FIG. 1E, the polysilicon film 2 is etched to form a gate electrode. The etching gas is a gas containing at least either Cl ₂ or HBr, such as Cl ₂ , Cl ₂ / O ₂ , C.
l ₂ / HBr / O ₂ , HBr / O _{2 and the} like are used. Since the underlying gate oxide film 2 is as thin as ten and several Å, it is important to use conditions with a sufficiently high selection ratio (selection ratio 20 to 100). In this embodiment mode, Cl ₂ / HBr / O ₂ = 40/80/10 sccm is used as the etching gas.
Gas was used. As the etching apparatus, an ECR etching apparatus is used, and the pressure is 3 mTorr (about 0.4 P
a), microwave power was 500 W, and lower electrode power was 30 W.

It has been experimentally proved that in the above etching process, no residue is generated after etching the polysilicon film 2. This is supported by the following theory. The position of the residue generated in the conventional process is always near the polysilicon film which is the gate electrode. From this, the residue is the antireflection film (p-SiON) and the polysilicon film 2 which are generated during the removal of the antireflection film 4.
It is inferred that the reaction product is a fluorocarbon film deposited. It was found that this reaction product is highly likely to be anisotropically attached to the sidewall of the gate electrode in the vertical direction.

In the present embodiment, due to the Wet shrink, the boundary between the polysilicon film 2 and the silicon oxide film 3 becomes stepwise, and a corner portion is formed above the portion which will be the gate electrode. These corners are etched together in the step of removing the antireflection film 4 to have a tapered shape as shown in FIG.

That is, in the present embodiment, as in the conventional process, a reaction product is generated in the step of removing the antireflection film 4, but the side wall of the gate electrode to which the reaction product is attached prevents the reflection. Since the film 4 is simultaneously etched and removed during the process of removing the film 4, no reaction product that causes a residue remains.

As described above, by exchanging the order of the steps of Wet shrink and removal of the antireflection film, it is possible to suppress the etching residue at the time of processing the gate electrode, and to provide a highly reliable semiconductor device without electrical short circuit. Will be able to.

Embodiment 2. FIG. 2 is a diagram showing a gate electrode forming process in the second embodiment. Figure 2
(A) is a cross-sectional view of the wafer before etching. First, using a vertical oxidation furnace, a gate insulating film (SiO2 film) with a thickness of 75Å is formed on a silicon substrate (not shown).
1 is deposited. Next, a polysilicon film 2 of a gate electrode material is formed on the gate insulating film 1 by vertical low pressure CVD. The thickness of the polysilicon film 2 is about 2000 Å. Further, by vertical low pressure CVD, a silicon oxide film (TEOS film) 3 serving as a mask at the time of processing the gate electrode is formed. The thickness of the silicon oxide film 3 is about 600Å. In addition to the silicon film, the mask material
It may be a silicon nitride film. Next, using a plasma CVD device, an antireflection film (p-SiON film) having a thickness of 500 Å
4 is deposited. Further, a resist 5 is formed on the antireflection film 4.
Is applied for about 4000 Å, exposed and developed to form a resist pattern.

Next, as shown in FIG. 2B, the antireflection film 4 and the silicon oxide film 3 are etched using the resist pattern as a mask. The etching is performed using a dry etching device using plasma. In the present embodiment, the electrodes are parallel plate type and the frequency is R of 400 Hz.
An apparatus equipped with an F power supply was used. The etching gas is CHF ₃ / O ₂ / Ar, CF ₄ / O ₂ / Ar, CH.
It is preferable to use a gas containing F such as F ₃ / CF ₄ / _{O 2} / Ar and C ₄ F ₈ / O ₂ / Ar. In the present embodiment, the wafer is transferred to the etching chamber of the apparatus, and CF ₄ / O ₂ / Ar = 60/20 is set in the etching chamber.
The gas is supplied at a ratio of / 800 sccm, and the exhaust gas is adjusted so that the inside of the etching chamber becomes 200 mT.
Turn on 1000 W of power. After the etching is completed, the resist 5 is removed by enzyme plasma using a dry ashing device. In this embodiment mode, the gas is O ₂ / N ₂ = 950/50 s in an ashing device using a microwave.
The resist was ashed at ccm, a pressure of 1 Torr (about 133 Pa), a microwave power of 1.5 kW, and a stage temperature of 250 ° C.

Next, as shown in FIG. 2C, the antireflection film 4 on the mask is removed. The antireflection film 4 is etched by using a dry etching apparatus using plasma. In the present embodiment, a device having parallel plate electrodes and an RF power source with a frequency of 400 Hz is used. Also,
The etching gas is CHF ₃ / O ₂ / Ar, CF ₄ / O
₂ / _Ar, etc. _{CHF 3 / CF 4 / O 2} / Ar, it is preferable to use a gas containing F. In this embodiment,
The wafer is transferred to the etching chamber of the apparatus, and CHF ₃ / CF ₄ / O ₂ / Ar = 10/70 is fed into the etching chamber.
A gas is supplied at a ratio of / 13/800 sccm, the exhaust is adjusted so that the inside of the etching chamber is 400 mT, and an RF power source of 500 W is turned on. At this time, a gas system is selected so that the polysilicon film 2 of the underlying gate electrode is not etched as much as possible. The selection ratio between the base polysilicon film 2 and the antireflection film 4 under the above conditions is about 4.

After that, the wafer is ashed by a dry ashing device. The ashing device is a device using microwaves, the gas is O ₂ / N ₂ = 950/50 sccm, the pressure is 1 Torr (about 133 Pa), and the microwave power is 1.5.
kW and stage temperature 250 ° C.

Next, wet cleaning of the wafer is performed. Ammonia hydrogen peroxide is used for cleaning, and cleaning is performed for about 15 minutes.
By performing such ashing and cleaning, it is possible to remove the reaction product attached to the upper corner of the gate electrode.

Next, as shown in FIG. 2D, the silicon oxide film 3 serving as a mask during the processing of the gate electrode is wet-shrinked. That is, the silicon oxide film 3 is etched using a solvent so as to have a desired gate electrode size. For example, when the wafer is placed on a hydrofluoric acid layer having a concentration of 5% for 5 minutes, a gate electrode having a width of 0.18 μm has a width of 0.14 μm.
It becomes the width of μm.

Then, as shown in FIG. 2E, the polysilicon film 2 is etched to form a gate electrode. The etching gas is a gas containing at least either Cl ₂ or HBr, such as Cl ₂ , Cl ₂ / O ₂ , C.
l ₂ / HBr / O ₂ , HBr / O _{2 and the} like are used. Since the underlying gate oxide film 2 is as thin as ten and several Å, it is important to use conditions with a sufficiently high selection ratio (selection ratio 20 to 100). In this embodiment mode, Cl ₂ / HBr / O ₂ = 40/80/10 sccm is used as the etching gas.
Gas was used. As the etching apparatus, an ECR etching apparatus is used, and the pressure is 3 mTorr (about 0.4 P
a), microwave power was 500 W, and lower electrode power was 30 W.

It has been experimentally proved that no residue is generated after etching the polysilicon film 2 in the above etching process. As described above, the residue generated in the conventional process is the deposition of the reaction product fluorocarbon film of the antireflection film (p-SiON) and the polysilicon film 2 generated during the removal of the antireflection film 4, and this reaction The product is anisotropically attached to the sidewall of the gate electrode in the vertical direction. Therefore, by removing the reaction products attached on the ashing and the wet line, it is possible to suppress the residue and provide a highly reliable semiconductor device.

Embodiment 3. FIG. 3 is a diagram showing a gate electrode forming process in the third embodiment. Figure 3
(A) is a cross-sectional view of the wafer before etching. First, using a vertical oxidation furnace, a gate insulating film (SiO2 film) with a thickness of 75Å is formed on a silicon substrate (not shown).
1 is deposited. Next, a polysilicon film 2 of a gate electrode material is formed on the gate insulating film 1 by vertical low pressure CVD. The thickness of the polysilicon film 2 is about 2000 Å. Further, by vertical low pressure CVD, a silicon oxide film (TEOS film) 3 serving as a mask at the time of processing the gate electrode is formed. The thickness of the silicon oxide film 3 is about 600Å. In addition to the silicon film, the mask material
It may be a silicon nitride film. Next, using a plasma CVD device, an antireflection film (p-SiON film) having a thickness of 500 Å
4 is deposited. Further, a resist 5 is formed on the antireflection film 4.
Is applied for about 4000 Å, exposed and developed to form a resist pattern.

Next, as shown in FIG. 3B, the antireflection film 4 and the silicon oxide film 3 are etched using the resist pattern as a mask. The etching is performed using a dry etching device using plasma. In the present embodiment, the electrodes are parallel plate type and the frequency is R of 400 Hz.
An apparatus equipped with an F power supply was used. The etching gas is CHF ₃ / O ₂ / Ar, CF ₄ / O ₂ / Ar, CH.
It is preferable to use a gas containing F such as F ₃ / CF ₄ / O ₂ / Ar or C ₄ F ₈ / O ₂ / Ar. In the present embodiment, the wafer is transferred to the etching chamber of the apparatus, and CF ₄ / O ₂ / Ar = 60/20 is set in the etching chamber.
The gas is supplied at a ratio of / 800 sccm, and the exhaust gas is adjusted so that the inside of the etching chamber becomes 200 mT.
Turn on 1000 W of power. After the etching is completed, the resist 5 is removed by enzyme plasma using a dry ashing device. In this embodiment mode, the gas is O ₂ / N ₂ = 950/50 s in an ashing device using a microwave.
The resist was ashed at ccm, a pressure of 1 Torr (about 133 Pa), a microwave power of 1.5 kW, and a stage temperature of 250 ° C.

Next, as shown in FIG. 3C, the antireflection film 4 on the mask is removed. The antireflection film 4 is etched by using a dry etching apparatus using plasma. In the present embodiment, a device having parallel plate electrodes and an RF power source with a frequency of 400 Hz is used. Also,
The etching gas is C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , C
Any gas of ₃ F ₆ , CF ₄ , SF ₆ , and CH
Any one gas of ₂ F ₂ , CHF ₃ , and CH ₃ F is used. In the present embodiment, the wafer is transferred to the etching chamber of the apparatus, and C ₄ F ₈ / C is placed in the etching chamber.
HF ₃ / CF ₄ / O ₂ / Ar = 5/10/70/13 /
A gas is supplied at a ratio of 800 sccm, the exhaust is adjusted so that the inside of the etching chamber is 200 mT, and an RF power source 800 W is turned on. At this time, the selection ratio between the underlying polysilicon film 2 and the antireflection film 4 is about 20.

Next, as shown in FIG. 3D, the silicon oxide film 3 serving as a mask at the time of processing the gate electrode is wet-shrinked. That is, the silicon oxide film 3 is etched using a solvent so as to have a desired gate electrode size. For example, when the wafer is placed on a hydrofluoric acid layer having a concentration of 5% for 5 minutes, a gate electrode having a width of 0.18 μm has a width of 0.14 μm.
It becomes the width of μm.

Next, as shown in FIG. 3E, the polysilicon film 2 is etched to form a gate electrode. The etching gas is a gas containing at least either Cl ₂ or HBr, such as Cl ₂ , Cl ₂ / O ₂ , C.
l ₂ / HBr / O ₂ , HBr / O _{2 and the} like are used. Since the underlying gate oxide film 2 is as thin as ten and several Å, it is important to use conditions with a sufficiently high selection ratio (selection ratio 20 to 100). In this embodiment mode, Cl ₂ / HBr / O ₂ = 40/80/10 sccm is used as the etching gas.
Gas was used. As the etching apparatus, an ECR etching apparatus is used, and the pressure is 3 mTorr (about 0.4 P
a), microwave power was 500 W, and lower electrode power was 30 W.

In the above etching process, the antireflection film
To remove C as an etching gas _FourF₈, C₅F₈,
C_ThreeF₆, C_FourF₆By adding any of the
The selection ratio of the gate electrode to the polysilicon film is significantly improved.
Experiments have revealed that this is the case. With this gas system
Is a polysilicon film in the process of etching the antireflection film.
Even if it is etched, reaction products will be generated.
Since there is almost no, the residue can be suppressed.

By combining the process of this embodiment with the ashing and cleaning steps of the second embodiment, a semiconductor device of higher quality can be provided.

[0034]

In the first method of the present invention, the reaction product of the antireflection film and the polysilicon film generated in the step of removing the antireflection film is changed by changing the order of the Wet shrink and the step of removing the antireflection film. Since it can be removed together with the antireflection film, etching residues can be suppressed.

In the second method of the present invention, the reaction products attached by ashing and wet cleaning are removed after the step of removing the antireflection film, so that etching residues can be suppressed.

In the third method of the present invention, by devising the components of the etching gas used for removing the antireflection film, it is difficult to generate a reaction product that causes an etching residue, so that the etching residue is suppressed. can do.

By these methods, it is possible to suppress an etching residue that may cause an electrical short circuit, so that a highly reliable semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a diagram showing a gate electrode forming process according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a gate electrode forming process according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a gate electrode forming process according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a conventional gate electrode formation process.

[Explanation of symbols]

1 gate insulating film, 2 polysilicon film, 3 silicon oxide film, 4 antireflection film, 5 photoresist.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akemi Teratani             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F-term (reference) 4M104 BB01 CC05 DD43 DD64 DD65                       DD67 DD71 EE03 EE05 EE16                       GG09 HH20                 5F004 AA09 BA04 BB13 DA00 DA01                       DA15 DA16 DA18 DA30 DB00                 5F140 AA00 BE07 BF01 BF04 BG20                       BG22 BG28 BG36 BG37 BG38                       BG39

Claims (3)

[Claims] 1. A gate using the polysilicon film as a material by processing a semiconductor substrate on which a polysilicon film, a silicon oxide film on the polysilicon film, and an antireflection film on the silicon oxide film are formed. In a method of manufacturing a semiconductor device in which an electrode is formed, a pattern composed of the silicon oxide film and an antireflection film on the silicon oxide film is formed by photolithography, and a line width of the pattern of the silicon oxide film is a desired gate electrode. Fabrication of a semiconductor device characterized in that the gate electrode is formed by wet etching so as to have a width, removing the antireflection film, and etching the polysilicon film using the pattern of the silicon oxide film as a mask. Method. 2. A gate using the polysilicon film as a material by processing a semiconductor substrate on which a polysilicon film, a silicon oxide film on the polysilicon film, and an antireflection film on the silicon oxide film are formed. In a method for manufacturing a semiconductor device in which an electrode is formed, a pattern composed of the silicon oxide film and an antireflection film on the silicon oxide film is formed by photolithography, the antireflection film is removed, and the semiconductor substrate is ashed and washed. Wet etching so that the line width of the pattern of the silicon oxide film becomes a desired gate electrode width, and the gate electrode is formed by etching the polysilicon film using the pattern of the silicon oxide film as a mask. A method of manufacturing a semiconductor device, comprising: 3. A gate using the polysilicon film as a material by processing a semiconductor substrate on which a polysilicon film, a silicon oxide film on the polysilicon film, and an antireflection film on the silicon oxide film are formed. In a method for manufacturing a semiconductor device in which an electrode is formed, a pattern composed of the silicon oxide film and an antireflection film on the silicon oxide film is formed by photolithography, and the antireflection film is formed of C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ and C ₃ F ₆ gas, CF ₄ , SF ₆ ,
It is removed by etching using an etching gas that is a combination of any of CH ₂ F ₂ , CHF ₃ and CH ₃ F, and the line width of the pattern of the silicon oxide film is equal to the desired gate electrode width. To form the gate electrode by performing wet etching so that the pattern of the silicon oxide film is used as a mask to etch the polysilicon film.