JPH09270420A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH09270420A
JPH09270420A JP10374196A JP10374196A JPH09270420A JP H09270420 A JPH09270420 A JP H09270420A JP 10374196 A JP10374196 A JP 10374196A JP 10374196 A JP10374196 A JP 10374196A JP H09270420 A JPH09270420 A JP H09270420A
Authority
JP
Japan
Prior art keywords
photoresist
semiconductor device
etching
manufacturing
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10374196A
Other languages
Japanese (ja)
Inventor
Keisuke Akashi
圭介 赤司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP10374196A priority Critical patent/JPH09270420A/en
Publication of JPH09270420A publication Critical patent/JPH09270420A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To suppress generation of photoresist remnants by efficiently removing a resist deterioration layer in a manufacturing method of a semiconductor device performing dry etching of a conductive layer by using a gas containing bromine or the like. SOLUTION: At the time of performing an etching process on a conductive film 3 formed on a semiconductor substrate 1 by using gas containing bromine, a photoresist 4 is applied on the conductive film 3 so as to perform etching of the conductive film 3 while having the photoresist 4 as a mask. Thereafter, a semiconductor wafer is washed by using a diluted fluoric acid water to remove a resist deterioration layer 5 followed by performing ashing for removing the photoresist.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、導電膜をエッチ
ング加工する工程を含む半導体装置の製造方法に関し、
特にエッチングにより発生する汚染物及びフォトレジス
トを半導体装置から除去する半導体装置の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including a step of etching a conductive film,
In particular, the present invention relates to a method for manufacturing a semiconductor device in which contaminants and photoresist generated by etching are removed from the semiconductor device.

【0002】[0002]

【従来の技術】半導体装置の微細加工において、例えば
多結晶シリコン膜をゲート電極形状に加工する場合、臭
素系ガスを用いて、多結晶シリコン膜上にフォトレジス
トを塗布してこのフォトレジストをマスクとし、フォト
リソグラフィー法により多結晶シリコン膜をプラズマエ
ッチング処理する場合がある。臭素系ガスを用いたドラ
イエッチングの場合、エッチングにより、前記フォトレ
ジスト表層に臭素と炭素との化合物が発生し、その後フ
ォトレジストの除去のため酸素プラズマによるアッシン
グ処理を行っても、この化合物がマスクとなって付着物
下のフォトレジストを除去しきれずレジスト残渣が発生
しやすい。
2. Description of the Related Art In fine processing of a semiconductor device, for example, when processing a polycrystalline silicon film into a gate electrode shape, a bromine-based gas is used to coat a photoresist on the polycrystalline silicon film and mask the photoresist. In some cases, the polycrystalline silicon film is plasma-etched by the photolithography method. In the case of dry etching using a bromine-based gas, a compound of bromine and carbon is generated on the surface layer of the photoresist by the etching, and even if ashing treatment with oxygen plasma is performed to remove the photoresist, this compound is masked. As a result, the photoresist under the deposit cannot be completely removed, and a resist residue is likely to be generated.

【0003】フォトレジストを確実に除去する半導体装
置の製造方法としては、特開平4−96329号公報
に、アンモニア過酸化水素水を用いて洗浄除去する方法
が記載されている。
As a method of manufacturing a semiconductor device for surely removing a photoresist, Japanese Patent Application Laid-Open No. 4-96329 discloses a method of cleaning and removing with an ammonia hydrogen peroxide solution.

【0004】[0004]

【発明が解決しようとする課題】しかし、特開平4−9
6329号公報に記載の、アンモニア過酸化水素水を用
いて除去する方法においては、効果的な除去効果を持た
せるために長時間の洗浄を行わなければならない。この
場合、アンモニア過酸化水素水によりフォトレジストが
剥離し、この剥離したフォトレジストが洗浄槽に浮くた
め大量にパーティクルが発生してしまう。するとこのパ
ーティクルによりアンモニア過酸化水素水が汚染され洗
浄薬液として使用できなくなるので、清浄なアンモニア
過酸化水素水に取り替える必要が生じコストが増してし
まう。
However, Japanese Unexamined Patent Publication No. 4-9.
In the method of removing using ammonia hydrogen peroxide solution described in Japanese Patent No. 6329, cleaning must be performed for a long time in order to have an effective removing effect. In this case, the photoresist is stripped by the ammonia hydrogen peroxide solution, and the stripped photoresist floats in the cleaning tank, so that a large amount of particles are generated. Then, the ammonia hydrogen peroxide solution is contaminated by the particles and cannot be used as a cleaning chemical liquid, so that it is necessary to replace the ammonia hydrogen peroxide solution with clean ammonia hydrogen peroxide solution, and the cost increases.

【0005】そのため従来の製造方法においては、パー
ティクル発生を抑えるために、アッシング前には短時間
のアンモニア過酸化水素水による洗浄処理を行い、次に
アッシングを行い、次に再度アンモニア過酸化水素水洗
浄を行っていたので、工程数増加やスループット低下を
引き起こすという問題点があった。
Therefore, in the conventional manufacturing method, in order to suppress the generation of particles, a cleaning treatment with ammonia hydrogen peroxide solution for a short time is performed before ashing, then ashing is performed, and then ammonia hydrogen peroxide solution is again used. Since cleaning is performed, there is a problem in that the number of processes increases and the throughput decreases.

【0006】そこで本発明においては、フォトレジスト
表層のエッチング生成物及びフォトレジストを、少ない
工程数で確実に除去でき、高スループットの半導体装置
の製造方法を提供することを目的とする。
Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device with high throughput, which can surely remove the etching product and the photoresist on the surface layer of the photoresist with a small number of steps.

【0007】[0007]

【課題を解決するための手段】本発明は、臭素を含むガ
スを用いて半導体基板上に形成された導電膜をエッチン
グ加工する半導体装置の製造方法において、前記導電膜
上にレジストパターンを形成し、該レジストパターンを
マスクにして前記導電膜を臭素を含むガスを用いてエッ
チングする第1の工程と、前記第1の工程後、希弗酸水
を用いて前記半導体基板を洗浄する第2の工程と、前記
第1の工程後、アッシングをする第3の工程とを有す
る。
The present invention is a method for manufacturing a semiconductor device, wherein a conductive film formed on a semiconductor substrate is etched by using a gas containing bromine, and a resist pattern is formed on the conductive film. A first step of etching the conductive film with a gas containing bromine using the resist pattern as a mask, and a second step of cleaning the semiconductor substrate with dilute hydrofluoric acid water after the first step. And a third step of performing ashing after the first step.

【0008】本発明の一態様においては、前記第2の工
程後に、前記第3の工程を行う。
In one aspect of the present invention, the third step is performed after the second step.

【0009】本発明の一態様においては、前記第3の工
程後に前記第2の工程を行い、前記第2の工程後、硫酸
を用いて前記半導体基板を洗浄する第4の工程を更に有
する。
In one aspect of the present invention, the method further comprises the fourth step of performing the second step after the third step, and washing the semiconductor substrate with sulfuric acid after the second step.

【0010】本発明の一態様においては、前記希弗酸水
の弗酸濃度は、0.05〜0.3%の範囲にある。
In one aspect of the present invention, the concentration of hydrofluoric acid in the dilute hydrofluoric acid water is in the range of 0.05 to 0.3%.

【0011】本発明の一態様においては、前記第1の工
程後、CF4 とO2 とを含むガスを用いてプラズマアッ
シングを行う第5の工程と、前記第5の工程後、O2
スを用いてプラズマアッシングを行う第6の工程を更に
有する。
In one aspect of the present invention, a fifth step of performing plasma ashing using a gas containing CF 4 and O 2 after the first step, and an O 2 gas after the fifth step The method further includes a sixth step of performing plasma ashing using.

【0012】[0012]

【発明の実施の形態】以下、本発明に係る半導体装置の
製造方法の一実施の形態を図1を用いて説明する。図1
は、一実施の形態における半導体装置の製造方法を示す
工程別断面図である。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIG. FIG.
FIG. 6A is a cross-sectional view for each step showing a method for manufacturing a semiconductor device according to an embodiment.

【0013】まず、図1(a)に示すように、Si基板
1上に膜厚30Å程度以上の絶縁膜2を形成し、この上
に高濃度n型多結晶Si膜3を公知のCVD(Chemical
Vapor Deposition )法により形成し、多結晶シリコン
膜3上にフォトレジストを塗布して公知のフォトリソグ
ラフィー法にてレジストパターン4を形成し、レジスト
パターン4をマスクとして、HBrガスを用いてドライ
エッチングを行い多結晶シリコン膜3の配線を形成す
る。このドライエッチングは、例えば平行平板型プラズ
マエッチング装置にて、次に説明する3段階に分けて行
う。
First, as shown in FIG. 1A, an insulating film 2 having a film thickness of about 30 Å or more is formed on a Si substrate 1, and a high concentration n-type polycrystalline Si film 3 is formed on the insulating film 2 by a known CVD method. Chemical
Vapor Deposition) method, a photoresist is applied on the polycrystalline silicon film 3 to form a resist pattern 4 by a known photolithography method, and dry etching is performed using HBr gas using the resist pattern 4 as a mask. Then, the wiring of the polycrystalline silicon film 3 is formed. This dry etching is performed in a parallel plate type plasma etching apparatus, for example, in three stages described below.

【0014】このエッチング装置を使用する際のエッチ
ング条件は、例えば第1段階ではCF4 100ccm、
処理圧力700mTorr、RFパワー300W、第2
段階ではHBr20ccm、Cl2 200ccm、処理
圧力400mTorr、RFパワー250W、そして第
3段階ではHBr200ccm、Cl2 100ccm、
処理圧力400mTorr、RFパワー200Wであ
る。
The etching conditions when using this etching apparatus are, for example, CF 4 100 ccm in the first step,
Processing pressure 700mTorr, RF power 300W, 2nd
In the stage, HBr 20 ccm, Cl 2 200 ccm, processing pressure 400 mTorr, RF power 250 W, and in the third stage HBr 200 ccm, Cl 2 100 ccm,
The processing pressure is 400 mTorr and the RF power is 200 W.

【0015】ここで、第1段階は、HBrを用いた多結
晶シリコン膜3のドライエッチングでは対シリコン酸化
膜選択比が非常に高く多結晶シリコン膜3表面の自然酸
化膜除去が困難であるため予め自然酸化膜を除去するた
めに行うエッチングであり、第2段階はメインエッチン
グ、第3段階はオーバーエッチングである。この時、レ
ジスト表面にはC、Si、Brから成る変質層5が形成
される。なお、本実施の形態においては平行平板プラズ
マエッチング装置を用いたが、電子サイクロトロン共鳴
(ECR)プラズマ、誘導結合型(ICP)プラズマを
用いたエッチング装置にも本発明は適用できる。
Here, in the first step, the dry etching of the polycrystalline silicon film 3 using HBr has a very high selectivity ratio to the silicon oxide film and it is difficult to remove the natural oxide film on the surface of the polycrystalline silicon film 3. The etching is performed to remove the natural oxide film in advance. The second step is main etching and the third step is over-etching. At this time, an altered layer 5 made of C, Si and Br is formed on the resist surface. Although the parallel plate plasma etching apparatus is used in the present embodiment, the present invention is also applicable to an etching apparatus using electron cyclotron resonance (ECR) plasma or inductively coupled (ICP) plasma.

【0016】次に、前述のようなエッチングの終了した
半導体ウエハを、H2 O:HF=100:1、23℃に
調整した希弗酸にて洗浄する。このときの洗浄条件は例
えば以下の通りである。まず、該薬液を使用し1分間洗
浄を行い、引き続き水洗処理を5分間行った後に通常の
スピンドライヤー乾燥を行う。また、該薬液の熱酸化膜
のエッチングレートは3〜4Å/minなので絶縁膜2
の削れを心配する必要は全くない。このような希弗酸洗
浄を行うことにより、図1(b)に示すように、エッチ
ング中に形成された変質層5はほぼ除去される。
Next, the semiconductor wafer after the above-mentioned etching is washed with dilute hydrofluoric acid adjusted to H 2 O: HF = 100: 1 and 23 ° C. The cleaning conditions at this time are as follows, for example. First, the chemical solution is used for washing for 1 minute, followed by washing with water for 5 minutes and then ordinary spin dryer drying. Further, since the etching rate of the thermal oxide film of the chemical solution is 3 to 4Å / min, the insulating film 2
There is no need to worry about scraping. By performing such diluted hydrofluoric acid cleaning, as shown in FIG. 1B, the altered layer 5 formed during the etching is almost removed.

【0017】続いて、図1(c)に示すように、洗浄後
の半導体ウエハを、通常のマイクロ波プラズマアッシャ
ー(不図示)にて、次に示す2段階に分けてアッシング
する。このときの第1段階と第2段階におけるそれぞれ
のアッシング条件は例えば下記に示すとおりである。 第1段階 CF4 10ccm O2 200ccm マイクロ波パワー 800W 処理圧力 0.8Torr 処理時間 10sec 第2段階 O2 200ccm マイクロ波パワー 800W 処理圧力 0.8Torr 処理時間 60sec
Subsequently, as shown in FIG. 1C, the cleaned semiconductor wafer is ashed by a normal microwave plasma asher (not shown) in the following two stages. The respective ashing conditions in the first stage and the second stage at this time are as follows, for example. The first stage CF 4 10 ccm O 2 200 ccm microwave power 800W processing pressure 0.8Torr processing time 10sec second phase O 2 200 ccm microwave power 800W processing pressure 0.8Torr processing time 60sec

【0018】前記アッシング条件の第1段階で、希弗酸
洗浄では不完全であった変質層5の除去が完全となり、
第2段階で効率的にレジスト除去を行うことができる。
In the first step of the ashing conditions, the removal of the deteriorated layer 5 which was incomplete by the diluted hydrofluoric acid cleaning becomes complete,
The resist can be removed efficiently in the second stage.

【0019】但し、希弗酸洗浄によりレジスト除去が不
完全なのは、半導体ウエハ上でレジスト被覆面積の非常
に大きなパターンが存在するときのみであり、そのよう
なパターンがなければ、アッシングの第1段階は削除し
ても差し支えない。
However, incomplete removal of the resist by cleaning with dilute hydrofluoric acid occurs only when there is a pattern having a very large resist coating area on the semiconductor wafer. If there is no such pattern, the first step of ashing is performed. Can be deleted.

【0020】図2に本実施の形態の工程フローを示す。
SEM(走査電子顕微鏡)で観察できない大きさの有機
物が半導体ウエハ表面に残留している可能性があるた
め、後続工程が例えばLP−CVD(低圧化学的気相成
長)法による成膜工程のときは、アッシング後に硫酸過
水洗浄を行うことが望ましい。一方、後続工程がイオン
注入工程などの場合には、上記汚染は特に問題とならな
いので硫酸過水洗浄は行わなくても良い。
FIG. 2 shows a process flow of this embodiment.
Since there is a possibility that organic substances of a size that cannot be observed by SEM (scanning electron microscope) may remain on the surface of the semiconductor wafer, when the subsequent process is, for example, a film formation process by the LP-CVD (low pressure chemical vapor deposition) method. It is desirable to wash with sulfuric acid / hydrogen peroxide after ashing. On the other hand, when the subsequent step is an ion implantation step or the like, the above-mentioned contamination does not cause any particular problem, and therefore the sulfuric acid / hydrogen peroxide washing need not be performed.

【0021】本実施の形態では高濃度多結晶シリコン膜
をエッチングする場合について述べたが、臭素系のガス
でエッチング可能な膜であれば何を用いても良い。ま
た、本実施の形態においては、希弗酸洗浄後にアッシン
グを行うが、アッシング後に希弗酸洗浄を行ってもよ
い。
In the present embodiment, the case of etching the high-concentration polycrystalline silicon film has been described, but any film that can be etched with a bromine-based gas may be used. Further, in the present embodiment, the ashing is performed after the diluted hydrofluoric acid cleaning, but the diluted hydrofluoric acid cleaning may be performed after the ashing.

【0022】[0022]

【発明の効果】以上説明したように本発明においては、
半導体素子を臭素を含むガスを用いて、ドライエッチン
グする半導体装置の製造において、アッシング前に、フ
ォトレジストの剥離を引き起こすことのない薬液による
洗浄を行ってフォトレジスト表面の変質物を除去するの
で、変質物がマスクとなりアッシング時にレジスト残渣
が発生することなく、少数工程で確実にフォトレジスト
を除去することができる半導体装置の製造方法を実現で
きる。
As described above, in the present invention,
Using a gas containing bromine for the semiconductor element, in the production of a semiconductor device dry-etching, before ashing, since the degeneration of the photoresist surface is removed by cleaning with a chemical solution that does not cause peeling of the photoresist, It is possible to realize a method of manufacturing a semiconductor device in which the deteriorated substance serves as a mask and a resist residue is not generated during ashing, and the photoresist can be reliably removed in a small number of steps.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態を説明するための工程別
断面図である。
FIG. 1 is a cross-sectional view for each step for explaining an embodiment of the present invention.

【図2】本発明の一実施の形態の半導体装置の製造方法
の工程を示すフローチャートである。
FIG. 2 is a flowchart showing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 3 多結晶シリコン膜 4 フォトレジスト 5 レジスト変質層 1 Silicon substrate 3 Polycrystalline silicon film 4 Photoresist 5 Resist alteration layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 G03F 7/42 G03F 7/42 H01L 21/027 H01L 21/304 341M 21/304 341 21/30 572A ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location G03F 7/42 G03F 7/42 H01L 21/027 H01L 21/304 341M 21/304 341 21/30 572A

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 臭素を含むガスを用いて半導体基板上に
形成された導電膜をエッチング加工する半導体装置の製
造方法において、 前記導電膜上にレジストパターンを形成し、該レジスト
パターンをマスクにして前記導電膜を臭素を含むガスを
用いてエッチングする第1の工程と、 前記第1の工程後、希弗酸水を用いて前記半導体基板を
洗浄する第2の工程と、 前記第1の工程後、アッシングをする第3の工程とを有
することを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device in which a conductive film formed on a semiconductor substrate is etched by using a gas containing bromine, wherein a resist pattern is formed on the conductive film and the resist pattern is used as a mask. A first step of etching the conductive film with a gas containing bromine; a second step of cleaning the semiconductor substrate with dilute hydrofluoric acid water after the first step; and the first step. And a third step of performing ashing after that.
【請求項2】 前記第2の工程後に、前記第3の工程を
行うことを特徴とする請求項1に記載の半導体装置の製
造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the third step is performed after the second step.
【請求項3】 前記第3の工程後に前記第2の工程を行
い、 前記第2の工程後、硫酸を用いて前記半導体基板を洗浄
する第4の工程を更に有することを特徴とする請求項1
に記載の半導体装置の製造方法。
3. The method according to claim 1, further comprising a fourth step of performing the second step after the third step, and cleaning the semiconductor substrate with sulfuric acid after the second step. 1
A method of manufacturing a semiconductor device according to item 1.
【請求項4】 前記希弗酸水の弗酸濃度は、0.05〜
0.3%の範囲にあることを特徴とする請求項1に記載
の半導体装置の製造方法。
4. The concentration of hydrofluoric acid in the dilute hydrofluoric acid water is 0.05 to
The method of manufacturing a semiconductor device according to claim 1, wherein the range is 0.3%.
【請求項5】 前記第1の工程後、CF4 とO2 とを含
むガスを用いてプラズマアッシングを行う第5の工程
と、 前記第5の工程後、O2 ガスを用いてプラズマアッシン
グを行う第6の工程を更に有することを特徴とする請求
項1に記載の半導体装置の製造方法。
5. A fifth step of performing plasma ashing using a gas containing CF 4 and O 2 after the first step, and a plasma ashing using O 2 gas after the fifth step. The method for manufacturing a semiconductor device according to claim 1, further comprising a sixth step to be performed.
JP10374196A 1996-03-29 1996-03-29 Manufacture of semiconductor device Withdrawn JPH09270420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10374196A JPH09270420A (en) 1996-03-29 1996-03-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10374196A JPH09270420A (en) 1996-03-29 1996-03-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH09270420A true JPH09270420A (en) 1997-10-14

Family

ID=14362045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10374196A Withdrawn JPH09270420A (en) 1996-03-29 1996-03-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH09270420A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
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JP2001196478A (en) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp Manufacturing method of semiconductor, manufacturing method of flash memory, manufacturing method of static random access memory, and flash memory
WO2004017390A1 (en) 2002-08-14 2004-02-26 Lam Reserach Corporation Method and compositions for hardening photoresist in etching processes
JP2008085165A (en) * 2006-09-28 2008-04-10 Tokyo Electron Ltd Etching method and method of manufacturing semiconductor device

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JP2001196478A (en) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp Manufacturing method of semiconductor, manufacturing method of flash memory, manufacturing method of static random access memory, and flash memory
WO2004017390A1 (en) 2002-08-14 2004-02-26 Lam Reserach Corporation Method and compositions for hardening photoresist in etching processes
US6923920B2 (en) 2002-08-14 2005-08-02 Lam Research Corporation Method and compositions for hardening photoresist in etching processes
CN100423191C (en) * 2002-08-14 2008-10-01 兰姆研究有限公司 Method and compositions for hardening photoresist in etching processes
JP2008085165A (en) * 2006-09-28 2008-04-10 Tokyo Electron Ltd Etching method and method of manufacturing semiconductor device
TWI463563B (en) * 2006-09-28 2014-12-01 Tokyo Electron Ltd Etching method and manufacturing method of semiconductor device

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