WO2011081512A2 - Cleaning method for removing post via etch residue - Google Patents
Cleaning method for removing post via etch residue Download PDFInfo
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- WO2011081512A2 WO2011081512A2 PCT/MY2010/000252 MY2010000252W WO2011081512A2 WO 2011081512 A2 WO2011081512 A2 WO 2011081512A2 MY 2010000252 W MY2010000252 W MY 2010000252W WO 2011081512 A2 WO2011081512 A2 WO 2011081512A2
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- etch residue
- holes
- cleaning treatment
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- electronic devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Definitions
- the present invention relates generally to a method for effectively removing post via etch residue including fluorinated by-product and hence enhances functional product yield by first treating the etched substrate/ wafer with a preliminary solvent treatment prior to conventional methods of plasma resist stripping treatment followed by a wet/ solvent cleaning treatment.
- semiconductor devices are present in almost every electrical and electronic devices.
- the fabrication of semiconductor devices is a multiple step sequence that generally involves cycles of deposition, patterning and etching a substrate or wafer.
- One of the processes where circuit pattern or other structure is formed on a wafer or substrate is by means of photolithographic process wherein a photoresist layer is coated on the wafer or substrate which functions as a mask for protection to some areas of the wafer or substrate for subsequent patterning processes to be carried out.
- These electronic devices namely integrated circuits are predominantly metallic in nature which are layers patterned/ coated on the wafer or substrate. There are usually several layers of metal and each layer is separated by an insulating layer.
- the metal layer above the poly gate layer is the first-level metal (ml), the next is the second level metal (m2), the next is the third level metal (m3) and so on.
- an insulating layer also known as an interlevel dielectric or interlayer dielectric
- a connection has to be made between two interconnect layers. This is achieved by etching vias or trench-like structures on the interlayer dielectric before the upper interconnect layer is formed. In short the vias are situated in between the interconnect layers to provide vertical connection between stacked up interconnect metal lines.
- a connection between ml and m2 will use an ml / m2 via or a vial
- a connection between m2 and m.3 will use an m2/ m3 via or a via2 and so on.
- polymer material tend to build up at the vias as via veils or residues. These polymer residues tend to build up on the sidewalls at the bottom of the via and at the upper corners of the via.
- the etch residue is a by-product of materials used in etching and silicon and carbon from the etched interlayer dielectric and metal from the underlying interconnect layer that is sputtered onto the sidewalls of the via.
- the conventional post via interconnect-holes cleaning method includes a dry and wet treatment that is a plasma resist stripping treatment to remove the photoresist layer followed by a solvent cleaning step.
- the plasma resist strip typically uses a radio frequency (RF) energy for energizing the reactant species, a plasma which attacks the photoresist which is a polymer, to strip the photoresist.
- RF radio frequency
- the solvent cleaning step is used to remove the fluorinated compound by-product or other polymer residue deposited on the walls of the via.
- the conventional cleaning method was found to be ineffective in removing the fluorinated compound by-product completely even with longer duration in the solvent cleaning step. It was thought that the said by-product compound had become hardened when it was subjected to high temperature in the plasma resist strip process directly after the via interconnect-holes etching process.
- Yet another object of the present invention is to provide a reliable and efficient method for cleaning the etch residue from the via interconnecting hole of electronic devices that is capable of increasing product functional yield.
- Yet another object of the present invention is to provide a reliable and efficient method for cleaning the etch residue from the via interconnecting hole of electronic devices capable of reducing instances of manufacturing tool failure that utilises integrated circuits as one of its component.
- a method for removing etch residue from the via interconnecting hole of electronic devices comprising steps of, performing a brief preliminary wet cleaning treatment using aqueous solution; performing a dry cleaning treatment using plasma resist strip after performing the brief wet cleaning treatment; performing a subsequent wet cleaning treatment using aqueous solution after performing the dry cleaning treatment.
- FIG. 1 is a flow chart showing the process flow of the present invention for removing etch residue in its preferred method.
- FIG. 2 is a flow chart showing the process flow of the conventional method for removing etch residue.
- FIG. 3 is a graphical representation showing the results of an electrical test data for via resistance comparison.
- FIG. 4 is a graphical representation showing the yield improvement after applying the present method as disclosed in this mention.
- Figure 5-A and 5-B are views from the top using FESEM (Field Emission
- FIG. 6A and 6-B are using FDSEM cross-sectional views illustrating the comparison of via interconnect-holes such as via2 hole using the conventional and the present method of removing fluorinated by-product respectively.
- Figure 7-A and 7-B are views taken using the CD-SEM (Critical Dimension-Scanning Electron Microscopy) illustrating the comparison of via interconnect-holes such as via2 hole using the conventional and the present method of removing fluorinated by-product respectively.
- CD-SEM Critical Dimension-Scanning Electron Microscopy
- FIG. 1 is a block diagram showing the process flow of the preferred method of present invention for removing etch residue (1) from the via interconnect-holes (2).
- the preferred method as illustrated comprises four main steps namely a preliminary solvent cleaning step indicated by the first block (4), a dry cleaning step indicated by the second block (6), a subsequent solvent cleaning step indicated by the third block (8), and a barrier deposition step indicated by the fourth block (10).
- the preliminary solvent cleaning step (4) or also known as the preliminary wet cleaning step comprises the following sub-steps namely the wafer rotation step indicated by the reference numeral (4A), the wafer rinsing step indicated by the reference numeral (4B) and the wafer drying step indicated by the reference numeral (4C).
- the wafer rotation step (4A) the wafer rotated in a forward spin rotation at a motor speed of preferably 60 rotations per minute (rpm) for a duration of at least five minutes is subjected to interaction with an aqueous solution namely ELM (a fluorine based chemical solvent).
- ELM a fluorine based chemical solvent
- the wafer is rinsed off with deionised water (DI) for preferably seven minutes and then purged with Nitrogen gas (N 2 ) utilizing a forward spin rotation at a motor speed of preferably 60 rpm in the wafer rinsing step (413). Thereafter the wafer is dried for a duration of preferably twelve minutes with Nitrogen gas (N 2 ) purge utilizing a forward spin rotation at a motor speed of preferably 500 rpm in a wafer drying step (4C). It was found that employing a preliminary solvent cleaning step (4) briefly before the dry cleaning step (6) had a significant effect in removing the residue such as fluorinated byproduct (12) in the via unlike the conventional method.
- DI deionised water
- N 2 Nitrogen gas
- the next step is the dry cleaning step (6) or plasma resist stripping process, which is similar to conventional dry treatment.
- This is also known as plasma ashing.
- This step utilizes an oxygen plasma energized with RF (radio frequency) power of 2,500 watts under a pressure of 1,500 mTorr (Torr is a unit of pressure, commonly used in vacuum engineering, and is equivalent to approximately 133.3 pascals or 1/760 of standard atmosphere) with oxygen flow at 3000 seem (standard cubic centimeters per minute) and at a temperature of 250 degree Celcius. It is a process of removing photoresist pattern from wafer surface.
- RF radio frequency
- a plasma source Using a plasma source a monoatomic species is generated that is the plasma produces energetic free radicals neutrally charged that react at the surface of the wafer.
- the reactive species oxygen is the most common reactive species
- a subsequent solvent cleaning step (8) is employed. This is similar to the preliminary solvent cleaning step (4) in all aspects save for a longer initial forward spin rotation preferably ten instead of five minutes.
- barrier deposition step (10) When the above three steps are performed the device is ready for a thin layer of barrier metal (typically titanium/ titanium nitride) to be deposited which is carried out in the barrier deposition step (10).
- barrier metal typically titanium/ titanium nitride
- deposition is a process that grows, coats or otherwise transfers a material onto the wafer.
- etch residue cleaning involves only two main steps that is the dry cleaning step indicated by the first block (6A) and a solvent cleaning step (8A) before the barrier deposition step (10A) is carried out. There is no additional preliminary solvent cleaning step as in the present invention.
- FIG. 3 there is shown a graphical representation showing the results of an electrical test data for via resistance comparison.
- wafer electrical test performed on 0.5um CMOS 1P3M logic qualification lot revealed high via interconnect-holes resistance that had caused a drop in the functional product yield.
- the graph in FIG. 3 shows a great difference in via resistance value between the good and the bad lot.
- Lot number X000076-2 W6 and X0076W1 is the first lot run without process improvement which translates to lower yield of less than 30%.
- the second lot run with some improvement on via etching applies to lot X0124-1 which raises the yield to 60%.
- FIGS. 5- A and 5-B there are respectively shown views from the top using FESEM illustrating the comparison between two via interconnect-holes (2) such as via2 holes using the conventional and the present method of removing fluorinated by-product (12).
- FIGS. 5-A and 5-B are the respective FESEM cross-sectional views illustrating the comparison between two via interconnect-holes (2) such as via2 holes using the conventional and the present method of removing fluorinated by-product (12).
- FIGS. 6-A and 6-B are respective views taken using the CD-SEM illustrating the comparison between two via interconnect-holes (2) such as via2 holes using the conventional and the present method of removing fluorinated by-product (12).
- the present invention which is a new post via interconnect-holes (2) cleaning method is able to improve the via interconnect-holes (2) resistance to less than 6 ohm/hole. This has helped to increase the product yield to more than 85%. The high yield was also found to be stable during 15 consecutive engineering lots (refer FIG. 4). While the preferred embodiment of the present invention and its advantages has been disclosed in the above Detailed Description, the invention is not limited thereto but only by the spirit and scope of the appended claim.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present inyention relates generally to a method for effectively removing post via etch residue (1) including fluorinated by-product (12) and hence enhances functional product yield by first treating the etched wafer with a preliminary solvent cleaning treatment (4) prior to conventional plasma resist stripping treatment (6) and thereafter a subsequent solvent cleaning treatment
Description
CLEANING METHOD FOR REMOVING POST VIA ETCH RESIDUE
1. TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a method for effectively removing post via etch residue including fluorinated by-product and hence enhances functional product yield by first treating the etched substrate/ wafer with a preliminary solvent treatment prior to conventional methods of plasma resist stripping treatment followed by a wet/ solvent cleaning treatment.
2. BACKGROUND OF THE INVENTION
Semiconductor devices are present in almost every electrical and electronic devices. The fabrication of semiconductor devices such as integrated circuits is a multiple step sequence that generally involves cycles of deposition, patterning and etching a substrate or wafer. One of the processes where circuit pattern or other structure is formed on a wafer or substrate is by means of photolithographic process wherein a photoresist layer is coated on the wafer or substrate which functions as a mask for protection to some areas of the wafer or substrate for subsequent patterning processes to be carried out. These electronic devices namely integrated circuits are predominantly metallic in nature which are layers patterned/ coated on the wafer or substrate. There are usually several
layers of metal and each layer is separated by an insulating layer. The metal layer above the poly gate layer is the first-level metal (ml), the next is the second level metal (m2), the next is the third level metal (m3) and so on. As these interconnect layers are separated by an insulating layer also known as an interlevel dielectric or interlayer dielectric, a connection has to be made between two interconnect layers. This is achieved by etching vias or trench-like structures on the interlayer dielectric before the upper interconnect layer is formed. In short the vias are situated in between the interconnect layers to provide vertical connection between stacked up interconnect metal lines. A connection between ml and m2 will use an ml / m2 via or a vial, a connection between m2 and m.3 will use an m2/ m3 via or a via2 and so on. However when such etching are carried out, polymer material tend to build up at the vias as via veils or residues. These polymer residues tend to build up on the sidewalls at the bottom of the via and at the upper corners of the via. The etch residue is a by-product of materials used in etching and silicon and carbon from the etched interlayer dielectric and metal from the underlying interconnect layer that is sputtered onto the sidewalls of the via. On further failure analysis investigation performed on the via interconnect- holes (2) such as vial, via2, via 3 and so on, it was revealed the presence of fluorinated compound by-product on the sidewall of the vias. It was discovered that the said by-product was formed during via interconnect-holes (2) etching process.
The conventional post via interconnect-holes cleaning method includes a dry and wet treatment that is a plasma resist stripping treatment to remove the photoresist layer followed by a solvent cleaning step. The plasma resist strip typically uses a radio frequency (RF) energy for energizing the reactant species, a plasma which attacks the photoresist which is a polymer, to strip the photoresist. Thereafter the solvent cleaning step is used to remove the fluorinated compound by-product or other polymer residue deposited on the walls of the via. The conventional cleaning method was found to be ineffective in removing the fluorinated compound by-product completely even with longer duration in the solvent cleaning step. It was thought that the said by-product compound had become hardened when it was subjected to high temperature in the plasma resist strip process directly after the via interconnect-holes etching process.
Due to the above residues would be inadvertently left remaining on via interconnect-holes. These residues if left thereon will affect the performance of the semiconductor devices and can lead to lower yields and even manufacturing tool failure. Therefore removing such residue particularly post etch polymers is of utmost importance to ensure that a high resistance via interconnect-holes does not result and a reliable electrical contact is achieved hence a superior quality device guaranteeing high product functional yield is achieved. It would hence be extremely advantageous if the above shortcoming is alleviated by having a reliable and efficient method for cleaning the etch residue
from the via interconnecting hole of electronic devices that can effectively remove polymer residues deposited on the sidewalls of the via interconnect- holes including fluorinated compound by-product.
3. SUMMARY OF THE INVENTION Accordingly, it is the primary aim of the present invention to provide a reliable and efficient method for cleaning the etch residue from the via interconnecting hole of electronic devices that can effectively remove polymer residues deposited including fluorinated compound by-product on the sidewalls of the via2 hole. It is another object of the present invention to provide a reliable and efficient method for cleaning the etch residue from the via mterconnecting hole of electronic devices which is able to improve the via2 resistance to less than 6 ohm/hole.
Yet another object of the present invention is to provide a reliable and efficient method for cleaning the etch residue from the via interconnecting hole of electronic devices that is capable of increasing product functional yield.
It is another object of the present invention to provide a reliable and efficient metliod for cleaning the etch residue from the via interconnecting hole
of electronic devices thereby resulting in fabrication of reliable integrated circuit which is capable of providing electrical devices having reliable electrical contact.
Yet another object of the present invention is to provide a reliable and efficient method for cleaning the etch residue from the via interconnecting hole of electronic devices capable of reducing instances of manufacturing tool failure that utilises integrated circuits as one of its component.
Other and further objects of the invention will become apparent with an understanding of the following detailed description of the invention or upon employment of the invention in practice. According to a preferred embodiment of the present invention there is provided,
A method for removing etch residue from the via interconnecting hole of electronic devices comprising steps of, performing a brief preliminary wet cleaning treatment using aqueous solution; performing a dry cleaning treatment using plasma resist strip after performing the brief wet cleaning treatment;
performing a subsequent wet cleaning treatment using aqueous solution after performing the dry cleaning treatment.
4. BRIEF DESCRIPTION OF THE DRAWINGS
Other aspect of the present invention and their advantages will be discerned after studying the Detailed Description in conjunction with the accompanying drawings in which:
FIG. 1 is a flow chart showing the process flow of the present invention for removing etch residue in its preferred method.
FIG. 2 is a flow chart showing the process flow of the conventional method for removing etch residue.
FIG. 3 is a graphical representation showing the results of an electrical test data for via resistance comparison.
FIG. 4 is a graphical representation showing the yield improvement after applying the present method as disclosed in this mention. Figure 5-A and 5-B are views from the top using FESEM (Field Emission
Scanning Electron Microscopy) iUushatrng the comparison of via interconnect- holes such as via2 hole using the conventional and the present method of removing fluorinated by-product respectively.
Figure 6-A and 6-B are using FDSEM cross-sectional views illustrating the comparison of via interconnect-holes such as via2 hole using the conventional and the present method of removing fluorinated by-product respectively.
Figure 7-A and 7-B are views taken using the CD-SEM (Critical Dimension-Scanning Electron Microscopy) illustrating the comparison of via interconnect-holes such as via2 hole using the conventional and the present method of removing fluorinated by-product respectively.
5. DETAILED DESCRIPTION OF THE DRAWINGS
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those or ordinary skill in the art that the invention may be practised without these specific details. In other instances, well known methods, procedures and/or components have not been described in detail so as not to obscure the invention. The invention will be more clearly understood from the following description of the embodiments thereof, given by way of example only with reference to the accompanying drawings which are not drawn to scale.
Referring to the drawings in which like numerals indicate like parts throughout the views shown, FIG. 1 is a block diagram showing the process
flow of the preferred method of present invention for removing etch residue (1) from the via interconnect-holes (2). The preferred method as illustrated comprises four main steps namely a preliminary solvent cleaning step indicated by the first block (4), a dry cleaning step indicated by the second block (6), a subsequent solvent cleaning step indicated by the third block (8), and a barrier deposition step indicated by the fourth block (10). The preliminary solvent cleaning step (4) or also known as the preliminary wet cleaning step comprises the following sub-steps namely the wafer rotation step indicated by the reference numeral (4A), the wafer rinsing step indicated by the reference numeral (4B) and the wafer drying step indicated by the reference numeral (4C). In the wafer rotation step (4A) the wafer rotated in a forward spin rotation at a motor speed of preferably 60 rotations per minute (rpm) for a duration of at least five minutes is subjected to interaction with an aqueous solution namely ELM (a fluorine based chemical solvent). Then the wafer is rinsed off with deionised water (DI) for preferably seven minutes and then purged with Nitrogen gas (N2) utilizing a forward spin rotation at a motor speed of preferably 60 rpm in the wafer rinsing step (413). Thereafter the wafer is dried for a duration of preferably twelve minutes with Nitrogen gas (N2) purge utilizing a forward spin rotation at a motor speed of preferably 500 rpm in a wafer drying step (4C). It was found that employing a preliminary solvent cleaning step (4) briefly before the dry cleaning step (6) had a significant effect in removing the residue such as fluorinated byproduct (12) in the via unlike the conventional method.
After performing the preliminary solvent cleaning step (4), the next step is the dry cleaning step (6) or plasma resist stripping process, which is similar to conventional dry treatment. This is also known as plasma ashing. This step utilizes an oxygen plasma energized with RF (radio frequency) power of 2,500 watts under a pressure of 1,500 mTorr (Torr is a unit of pressure, commonly used in vacuum engineering, and is equivalent to approximately 133.3 pascals or 1/760 of standard atmosphere) with oxygen flow at 3000 seem (standard cubic centimeters per minute) and at a temperature of 250 degree Celcius. It is a process of removing photoresist pattern from wafer surface. Using a plasma source a monoatomic species is generated that is the plasma produces energetic free radicals neutrally charged that react at the surface of the wafer. The reactive species (oxygen is the most common reactive species) combine with photoresist material to form ash during oxidation to facilitate its removal. After performing the dry cleaning step (6) a subsequent solvent cleaning step (8) is employed. This is similar to the preliminary solvent cleaning step (4) in all aspects save for a longer initial forward spin rotation preferably ten instead of five minutes.
When the above three steps are performed the device is ready for a thin layer of barrier metal (typically titanium/ titanium nitride) to be deposited which is carried out in the barrier deposition step (10). Here deposition is a process that grows, coats or otherwise transfers a material onto the wafer.
In the conventional method as illustrated in FIG. 2 etch residue cleaning involves only two main steps that is the dry cleaning step indicated by the first block (6A) and a solvent cleaning step (8A) before the barrier deposition step (10A) is carried out. There is no additional preliminary solvent cleaning step as in the present invention.
The scope of this research is focused on via cleaning process improvement that affects the via resistance and the product functional yield. Experiments were carried out on a 0.6um via hole size. The semiconductor devices were subjected to a variety of electrical tests to determine whether they function properly, the proportion of devices on the wafer found to perform properly is referred to as the yield. Referring to FIG. 3, there is shown a graphical representation showing the results of an electrical test data for via resistance comparison. In the experiment wafer electrical test performed on 0.5um CMOS 1P3M logic qualification lot revealed high via interconnect-holes resistance that had caused a drop in the functional product yield. The graph in FIG. 3 shows a great difference in via resistance value between the good and the bad lot. FIG. 4 is a graphical representation showing the yield improvement after applying the present method as disclosed in the present invention wherein via resistance of each lot is measured and plotted to form a graphical representation. Lot number X000076-2 W6 and X0076W1 is the first lot run without process improvement which translates to lower yield of less than 30%. The second lot
run with some improvement on via etching applies to lot X0124-1 which raises the yield to 60%. Then using the new method of cleaning to lot X0124-3 till X0166-2 the yield performance significantly improved to more than 85%.
The experimental results were analyzed and evaluated based on CD SEM photo, FESEM cross sectional view and electrical PCM and functional yield (FIG. 3). Referring to FIGS. 5- A and 5-B there are respectively shown views from the top using FESEM illustrating the comparison between two via interconnect-holes (2) such as via2 holes using the conventional and the present method of removing fluorinated by-product (12). FIGS. 5-A and 5-B are the respective FESEM cross-sectional views illustrating the comparison between two via interconnect-holes (2) such as via2 holes using the conventional and the present method of removing fluorinated by-product (12). FIGS. 6-A and 6-B are respective views taken using the CD-SEM illustrating the comparison between two via interconnect-holes (2) such as via2 holes using the conventional and the present method of removing fluorinated by-product (12).
The present invention which is a new post via interconnect-holes (2) cleaning method is able to improve the via interconnect-holes (2) resistance to less than 6 ohm/hole. This has helped to increase the product yield to more than 85%. The high yield was also found to be stable during 15 consecutive engineering lots (refer FIG. 4).
While the preferred embodiment of the present invention and its advantages has been disclosed in the above Detailed Description, the invention is not limited thereto but only by the spirit and scope of the appended claim.
Claims
1. A method for removing etch residue (1) from the via interconnect- holes (2) of electronic devices comprising steps of, performing a preliminary wet cleaning treatment (4) using aqueous solution; performing a dry cleaning treatment (6) using plasma resist strip after performing the preliminary wet cleaning treatment (4); performing a subsequent wet cleaning treatment (8) using aqueous solution after performing the dry cleaning treatment (6).
2. A method for removing etch residue (1) from the from via interconnect- holes (2) of electronic devices as in Claim 1 wherein the said preliminary wet cleaning treatment (4) utilizes a forward spin rotation at a motor speed of at least 60 rpm for a duration of preferably five minutes is rinsed with Deionised water (DI) for at least seven minutes and then purged with Nitrogen gas (N2) utilizing a forward spin rotation at a motor speed of 60 rpm.
3. A method for removing etch residue (1) from the from via interconnect- holes (2) of electronic devices as in Claim 1 wherein the said subsequent wet cleaning treatment (8) utilizes a forward spin rotation at a motor speed of at least 60 rpm for a duration of preferably ten minutes.
4. A method for removing etch residue (1) from via interconnect- holes (2) of electronic devices as in Claim 1 wherein the etch residue which is removed includes fluorinated by-product.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| MYPI20095611 MY148116A (en) | 2009-12-28 | 2009-12-28 | Cleaning method for removing post via etch residue |
| MYPI20095611 | 2009-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2011081512A2 true WO2011081512A2 (en) | 2011-07-07 |
| WO2011081512A3 WO2011081512A3 (en) | 2011-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/MY2010/000252 WO2011081512A2 (en) | 2009-12-28 | 2010-11-08 | Cleaning method for removing post via etch residue |
Country Status (2)
| Country | Link |
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| MY (1) | MY148116A (en) |
| WO (1) | WO2011081512A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957261A (en) * | 2018-09-26 | 2020-04-03 | 长鑫存储技术有限公司 | Preparation method of semiconductor device interconnection structure barrier layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1511072A2 (en) * | 2003-08-26 | 2005-03-02 | Texas Instruments Incorporated | Post-etch clean process for porous low dielectric constant materials |
| KR20050069709A (en) * | 2003-12-31 | 2005-07-05 | 동부아남반도체 주식회사 | Method for removing photoresist pattern |
| US20080047594A1 (en) * | 2006-07-05 | 2008-02-28 | Wheeler Ronald K | Car washing appliance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH076942A (en) * | 1991-09-30 | 1995-01-10 | Fujitsu Ltd | Manufacture of semiconductor device |
-
2009
- 2009-12-28 MY MYPI20095611 patent/MY148116A/en unknown
-
2010
- 2010-11-08 WO PCT/MY2010/000252 patent/WO2011081512A2/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1511072A2 (en) * | 2003-08-26 | 2005-03-02 | Texas Instruments Incorporated | Post-etch clean process for porous low dielectric constant materials |
| KR20050069709A (en) * | 2003-12-31 | 2005-07-05 | 동부아남반도체 주식회사 | Method for removing photoresist pattern |
| US20080047594A1 (en) * | 2006-07-05 | 2008-02-28 | Wheeler Ronald K | Car washing appliance |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957261A (en) * | 2018-09-26 | 2020-04-03 | 长鑫存储技术有限公司 | Preparation method of semiconductor device interconnection structure barrier layer |
| CN110957261B (en) * | 2018-09-26 | 2022-11-01 | 长鑫存储技术有限公司 | Preparation method of semiconductor device interconnection structure barrier layer |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011081512A3 (en) | 2011-08-18 |
| MY148116A (en) | 2013-02-28 |
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