JP2001237415A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form sources/gates only at required parts for the process of implanting ions in the sources/drains by increasing the removing speed of a hard mask and cleaning out resulting residues. SOLUTION: The semiconductor device manufacturing method for forming gate electrodes of semiconductor transistors comprises a step of processing an insulation film (hard mask material) of one of SiO2, SiN, and SiON after laminating a gate oxide film, a gate electrode material and a hard mask material on a semiconductor substrate one above another and forming a resist film having a pattern corresponding to the gate electrodes, a step of removing deposition film deposited in the process of the hard mask material, and a step of continuously processing the gate electrode material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device related to an etching method.

[0002]

2. Description of the Related Art Conventionally, in a method of manufacturing a semiconductor device,
2. Description of the Related Art As the density of semiconductor devices increases, the technology for forming electrodes or wirings has been required to be more precise and finer. This electrode or wiring processing technology occupies an important position in a semiconductor device manufacturing process.

Here, as a conventional technique, Japanese Patent Laid-Open No. 11-1
No. 76807 will be described. In this publication, on a material layer containing silicon, for example, a refractory metal silicide layer, a polymer that could not be removed by ashing and a deposit by a silicon oxide film of a by-product by a reactive gas during ashing remain. When dry etching is performed using a hard mask as a mask, the etching is hindered in portions other than the hard mask, so that patterning faithful to the pattern of the photoresist layer is not performed, and so-called pattern conversion difference increases. It is intended to prevent it.

[0004] As shown in FIG.
1. For example, a gate insulating layer 12 made of a SiO ₂ film having a thickness of 10 nm is formed by thermal oxidation in a batch type thermal diffusion furnace on a gate forming portion on the surface of a silicon (Si) substrate. On top of this, low pressure CVD (Chemical Vapor Depositio
n) the raw material gas in the apparatus and the supply flow rate of the SiH ₄ gas 40
0 sccm, PH ₃ gas (SiH ₄ base 0.5%) 100
A sccm, a pressure of 40 Pa, a film formation temperature of 550 ° C., and an impurity-doped, low-resistivity, 100-nm-thick, for example, n ⁺ -type polycrystalline silicon as a conductive layer for forming a gate electrode or a wiring. The source gas and the supply flow rate of the layer 13 and the supply flow rate of the SiH ₄ gas are set to 1000 s by a low pressure CVD apparatus
CCM, WF ₆ gas is 10 sccm, pressure is 26.6 Pa, film formation temperature is 360 ° C., and a refractory metal silicide layer 14 of tungsten silicide having a thickness of 100 nm is sequentially deposited.

On the refractory metal silicide layer 14, a source gas and its supply flow rate are changed to SiH ₄ by a plasma CVD apparatus.
Gas 50 sccm, N ₂ O gas 50 sccm, pressure 330
Pa, film formation temperature 380 ° C., RF power 190 W (13.
56 MHz), an anti-reflection film 15 for preventing the reflection of exposure light upon pattern exposure of the photoresist layer described later is formed, and the raw material gas and its supply flow rate are changed to a SiH ₄ gas (100% ) For 50s
At a pressure of ccm, a normal pressure and a film forming temperature of 430 ° C., a hard mask material layer 16 constituting a hard mask of SiO ₂ , Si ₃ N ₄ or the like is deposited thereon. A 1.2 μm thick positive novolak photoresist is applied to the hard mask material layer 16 in a pattern corresponding to a target electrode or wiring pattern for performing pattern etching by photolithography. , I-line (36
A photoresist layer 17 is formed by pattern exposure with 5 nm) and development.

Next, as shown in FIG. 4B, the hard mask material layer 16 and the antireflection film 15 are patterned by dry etching using the photoresist layer 17 as a mask to form a hard mask 16. For etching the hard mask material layer 16 and the anti-reflection film 15, the etching gas and its flow rate are controlled by a magnetron plasma apparatus.
F ₄ gas is 20 sccm, CHF ₃ gas is 20 sccm, Ar gas is 200 sccm, gas pressure is 33 Pa, and upper RF power is 8
Etching is performed at 00 W with a stage temperature of 30 ° C., and the hard mask material layer 16 is patterned to form a hard mask 26. Thereafter, the photoresist layer 17 is removed by ashing. This ashing is performed by using a counter electrode type ashing apparatus, using an ashing gas and a supply flow rate of 12000 sccm of O ₂ gas and 60 sccm of C ₂ F ₆ gas.
The gas pressure is 2666 Pa, the RF power is 700 W, and the stage temperature is 250 ° C. By this ashing,
Residue is removed by resist shrinkage. Further, the polymer residue after the ashing treatment is subjected to a sulfuric acid / hydrogen peroxide treatment with a sulfuric acid / hydrogen peroxide solution, and a sulfuric acid / hydrogen peroxide solution (H ₂ SO ₄ : H ₂ O ₂ = 5: 1) by a dip (liquid tank) type washing device. At 110 ℃
Soak for 00 seconds and rinse in deionized water (ultra pure water) for 300
Seconds, last finish rinse in deionized water (ultra pure water) for 300 seconds and spin dry for 300 seconds. In this manner, the photoresist layer 17 is removed, but the material layer containing Si of the refractory metal silicide layer 14 is exposed in the portions other than the portion where the hard mask 26 is to be adhered, thereby forming the deposit 19. I do.

To remove the deposit 19, the hydrofluoric acid treatment apparatus is immersed in a 0.25% HF aqueous solution (25%) for 190 seconds using a dip (liquid tank) type cleaning apparatus, and deionized water (ultra pure water). )
The rinse was performed for 300 seconds, the final deionized water rinse was performed for 300 seconds, and the spin-drying process was equivalent to 1 nm or more in terms of an oxide film, as shown in FIG.
The deposit 19 shown in (B) is removed, and the surface of the refractory metal silicide layer 14 of the WSi layer is cleaned.

Thereafter, as shown in FIG. 4D, the refractory metal silicide layer 14 and the polycrystalline silicon layer 13 are etched using the hard mask 26 as an etching mask to form a patterned refractory metal silicide layer. A gate electrode or wiring 25 is formed by laminating the polysilicon layer 14 and the polysilicon layer 13. This etching is conducted by magnetic field microwave plasma etching apparatus, the supply flow rate and the etching gas Cl ₂ gas 74Sccm, O ₂ gas 6
sccm, gas pressure 0.67 Pa, microwave power 800 W (2.45 GHz), RF bias 10
0 W (2 MHz) and stage temperature of 20 ° C. are supplied.

Further, in order to secure a selectivity with respect to the gate insulating layer 12, the RF bias was lowered, and over-etching corresponding to a polysilicon thickness of 100 nm was performed. In this etching, an etching gas and its supply flow rate were 74 sccm of Cl ₂ gas, 6 sccm of O ₂ gas, and gas pressure of 0.67 Pa by a magnetic field microwave plasma etching apparatus.
The microwave power is set to 800 W (2.45 GHz), the RF bias is set to 70 W (2 MHz), and the stage temperature is set to 20 ° C.

The gate electrode or the wiring layer 25 made of the refractory metal silicide layer 14 and the polycrystalline silicon 13 formed in this manner removes the deposit 19 by a hydrofluoric acid treatment, and accurately matches the pattern of the photoresist layer 17. It is formed as a corresponding pattern with a small conversion difference.

As such a dry etching method,
Japanese Patent Application Laid-Open No. 11-162941 discloses that in a method of dry-etching titanium silicide, a hard-etched titanium silicide layer is formed on a titanium silicide layer so as not to depend on the crystal structure of titanium silicide and to prevent an undercut or worm-like side etch. The mask 8 is formed, and then the titanium silicide layer is etched by a gas plasma of a mixed gas obtained by adding methane gas and boron trichloride to chlorine or hydrogen bromide. It describes that anisotropic etching is ensured, and the addition of boron trichloride minimizes the difference in etch rate between titanium silicide and silicon oxide, thereby suppressing the generation of etching residues.

Japanese Patent Application Laid-Open No. H11-87263 discloses a method of manufacturing a semiconductor integrated circuit device capable of improving the performance and reliability of a wiring layer having a tungsten layer.
A step of depositing a wiring layer having a laminated structure including a conductive polycrystalline silicon film and a tungsten layer; a step of forming a hard mask made of a silicon nitride film (insulating film) on the tungsten layer; Patterning the tungsten layer using an etching technique using the resist film above the mask as an etching mask, and removing the resist film and patterning the polycrystalline silicon film using a silicon nitride hard mask as an etching mask. And forming a polycrystalline silicon film of a wiring layer.

Japanese Patent Laid-Open Publication No. Hei 7-202189 discloses a method of manufacturing a semiconductor device. A laminated film of a polycrystalline silicon film, a titanium nitride film, and a tungsten film as a conductive layer containing a refractory metal is formed on a silicon substrate. Forming a resist pattern on the tungsten film, forming a reactive gas containing silicon into plasma, anisotropically etching the titanium nitride film and the tungsten film using the resist pattern as a mask, Forming a deposit containing silicon as a main component on the side walls of the film and the tungsten film, and removing the resist pattern, and then forming a silicide layer on the side walls of the titanium nitride film and the tungsten film by heating in a non-oxidizing atmosphere. And forming a gate electrode that does not increase the resistance.

The procedure for forming the above-mentioned gate electrode or wiring layer 25 in an authorized manner will be described with reference to FIG.

In FIG. 3A, a gate oxide film 3 is formed on a silicon substrate (not shown), and a gate electrode material 2 is formed thereon.
Polysilicon or tungsten (W) polycide or the like, and a hard mask material 1 of SiO 2 is formed thereon.
_2. A resist 4 is formed by laminating SiON, SiN, a laminated film or the like, and patterning. Next, FIG.
As shown in FIG. 7, the gate electrode material 2 is exposed by etching SiO ₂ , a fluorocarbon-based deposition film remains on the surface as a residue, and further, etching is continued by leaving the resist 4 to perform gate etching. Electrode material utilization 2 remains as residue.

[0016]

However, when the hard mask is removed and the gate electrode is exposed, the remaining deposits are inevitably left in order to remove the remaining deposition film and cannot be completely removed. In addition, it is necessary to increase the removal speed for removing the hard mask.

Therefore, the present invention increases the removal rate of the hard mask and removes the residue at that time, so that only the necessary portions can be removed during the subsequent ion implantation step to the source / drain. An object is to form a source / gate.

[0018]

According to the present invention, in a method of manufacturing a semiconductor device for forming a gate electrode of a semiconductor transistor, a gate oxide film, a gate electrode material, and a hard mask material are sequentially laminated on a semiconductor substrate. After forming a resist film with a pattern corresponding to the gate electrode,
Processing of an insulating film (hard mask material) of any one of SiO ₂ , SiN, and SiON, removing a deposition film deposited during processing of the hard mask material, and processing of the gate electrode material are continuously performed. It is characterized by having.

In the method of manufacturing a semiconductor device, as a step of removing a deposition film deposited during processing of the hard mask, a chlorine (Cl ₂ ) gas is used, and an ion energy voltage Vpp of an etching apparatus is set to 300 V or more. Characterized by the following conditions:

According to the present invention, in a method of manufacturing a semiconductor device for forming a gate electrode of a semiconductor transistor, a gate oxide film, a gate electrode material and a hard mask material are sequentially laminated on a semiconductor substrate, and After forming a resist film having a pattern to be changed, an inductive-coupled-plasma
a) Etching equipment, dual frequency RIE (reactive-ion-etch)
ing) In one of the etching apparatuses, SiO ₂ , SiN,
A step of processing any insulating film (hard mask material) of SiON, and using a chlorine (Cl ₂ ) gas at the time of etching the hard mask material, depositing the ion energy voltage Vpp of the above etching apparatus under the condition of 300 V or more. The step of removing the deposition film to be formed and the processing of the gate electrode material are continuously performed by the same etching apparatus, and thereafter, the source and the drain are formed by ion implantation.

[0021]

Embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment (1) Description of Configuration A semiconductor gate electrode processing method of the present invention will be described with reference to the drawings.

In FIG. 1, a gate oxide film 3 is formed on a semiconductor substrate (not shown), for example, a silicon layer or a GaAs substrate of a compound semiconductor, and a gate electrode material 2, for example, a polycrystalline silicon film (Poly- Si) or tungsten (W) polycide or the like is laminated, and a hard mask material 1, for example, SiO ₂ , SiON, SiN, or a laminated film thereof is laminated thereon, and further, a resist for forming a region pattern corresponding to the gate electrode 2 The film 4 is formed.

Here, the present semiconductor device includes, for example, a MOS.
An FET, a CMOS, an ASIC, an LSI, or the like is applicable. When manufacturing the semiconductor device, the above-described layers are sequentially formed, and then the gate electrode is covered with a patterned resist 4 to form a gate electrode in a predetermined region. .

(2) Description of Operation FIG. 1 is a view showing a specific example of the present invention. The flow of continuously processing a hard mask material 1 and a gate electrode material 2 in the same chamber using a dry etching method is shown. It is shown.

First, in FIG. 1A, a gate oxide film is formed.
3 is polysilicon and tungsten polycide (WSi /
Sputtering gate electrode material 2 such as polysilicon laminated film)
It is formed using a ring method and a CVD method, and then,
SiO of hard mask material 1 _Two(Silicon dioxide), silicon
Recon nitride film (SiN, Si_ThreeN_Four), Silicon oxynitride film
(SiON) or the above three types of laminated films by a CVD method.
Formed by Then, by photolithography,
Then, patterning of the resist 4 is performed. Resist 4
Patterning is performed as a desired gate electrode region pattern.
You.

Next, in the state shown in FIG.
The mask material 1 is etched in areas other than the resist 4 pattern.
Fluorocarbon gas such as C
HF _ThreeProcess using gas. In this case, the following steps
Performs processing in the same chamber. At this time,
Fluorocarbon deposition on the surface of the electrode material 2
A film 5 is formed (FIG. 1B).

This fluorocarbon-based deposition film 5
Since this causes residues when the gate electrode 2 is processed, an etching step for removing the deposition film 5 is required. As an etching condition at this time, a chlorine (Cl ₂ ) gas is used, and Vpp indicating an ion energy voltage for ion implantation of the chamber is set to 300 V or more (FIG. 1C). Under these conditions, the occurrence of the fluorocarbon-based deposition film 5 can be prevented.

Then, the gate electrode 2 is processed. The etching gas for processing the gate electrode 2 varies depending on the gate electrode material 2, but in the case of polysilicon,
For example, a mixed gas of Cl ₂ (chlorine) / HBr (hydrogen bromide) is used, and in the case of W polycide, etching is performed using a mixed gas of Cl ₂ / O ₂ (oxygen) (FIG. 1D).

The etching apparatus used here is an ICP (inductive-coupled-pl.) Having a low-pressure high-density plasma source.
asma) etching equipment, dual frequency RIE (reactive-ion-e)
tching) Any etching apparatus such as an etching apparatus may be used.

FIG. 2 shows, as an example, the gate electrode material 2
Shows the results of a study using a sample using W polycide and SiN as the hard mask material 1. The etching rate of the fluorocarbon deposition film 5 deposited during the processing of the hard mask material 1 and the etching rate of the gate electrode material 2 are shown. W
The graph shows the Vpp dependence of the etching rate of Si (tungsten silicide). The etching gas used was
There are three types of HBr, CF ₄ and Cl ₂ gases.

At this time, only when the etching rate of the fluorocarbon-based deposition film 5 is higher than the etching rate of WSi, there is no residue when processing the gate electrode.
Good etching can be realized.

When HBr gas and CF ₄ gas are used,
Under any of the Vpp etching conditions, the etching rate of WSi was slower than the etching rate of the fluorocarbon-based deposition film, and residues were generated during gate electrode processing. On the other hand, when Cl ₂ gas is used, the etching rate of the fluorocarbon-based deposition film becomes WS
Since the etching rate became faster than the etching rate of i, good etching could be realized without any residue when processing the gate electrode. Also, substantially the same result was obtained when polysilicon was used for the gate electrode material 2.

According to the present invention, in the step of processing the gate electrode, a step of processing a hard mask material and a step of removing a deposition film deposited during the processing of the hard mask 1 are provided.
The processing of the gate electrode material is performed continuously, and a good etching shape is provided without any residue.

In the step of processing the gate electrode, there is no residue of the fluorocarbon-based deposition film, so that when the next gate electrode material 2 is etched and then the source / drain is formed by ion implantation,
Since a MOSFET can be formed smoothly and without unevenness, an FET having a constant threshold value can be secured at high speed, and a semiconductor device with reduced manufacturing variations can be obtained.

[0036]

According to the present invention, in a method of processing a semiconductor device, as a step of removing a deposition film deposited at the time of processing a hard mask, a chlorine (Cl ₂ ) gas is used at a Vpp of 300 V or more. Since the etching rate of the fluorocarbon-based deposition film is faster than the etching rate of the gate electrode material,
Good gate etching electrode processing can be performed without any residue.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a method for processing a semiconductor device of the present invention.

FIG. 2 is a graph of an etching gas and an etching rate used in the present invention.

FIG. 3 is a configuration diagram illustrating a conventional method for processing a semiconductor device.

FIG. 4 is a configuration diagram illustrating a conventional method for processing a semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 hard mask material 2 gate electrode material 3 gate oxide film 4 resist 5 fluorocarbon-based deposition 11 semiconductor substrate 12 gate insulating layer 13 polycrystalline silicon layer 14 refractory metal silicide layer 15 antireflection film 16 hard mask material layer 17 photoresist layer

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M104 AA01 AA05 BB01 CC05 DD08 DD65 DD71 EE05 EE14 EE15 EE17 FF14 GG09 GG10 GG14 HH14 5F004 AA09 BA20 BB13 CA03 DA00 DA04 DA26 DB02 DB17 EA03 EA06 EA07 DC03 EC03 FA18 FC21

Claims (6)

[Claims] In a method of manufacturing a semiconductor device for forming a gate electrode of a semiconductor transistor, a gate oxide film, a gate electrode material, and a hard mask material are sequentially laminated on a semiconductor substrate to form a pattern corresponding to the gate electrode. After forming the resist film, Si
Processing of an insulating film (hard mask material) of any one of O ₂ , SiN, and SiON, removing a deposition film deposited during processing of the hard mask material, and processing of the gate electrode material are continuously performed. A method for manufacturing a semiconductor device. 2. A step of removing a deposition film deposited at the time of processing the hard mask, the step of removing chlorine (C)
_{2. The} method of manufacturing a semiconductor device according to claim 1, wherein a gas is used and the ion energy voltage Vpp of the etching apparatus is removed under a condition of 300 V or more. 3. The semiconductor substrate is a silicon substrate,
The gate oxide film is SiO ₂ , the gate electrode material is polysilicon or tungsten polycide, and the hard mask material is SiO ₂ , SiON, Si.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the method is any one of N. 4. The semiconductor device is a MOSFET,
2. The method according to claim 1, wherein, in the step of removing the deposition film, the etching rate of the hard mask material is higher than the etching rate of the gate electrode material, thereby preventing the occurrence of a fluorocarbon-based deposition film. Or, the method of manufacturing a semiconductor device according to 2 or 3. 5. An etching apparatus for etching a gate electrode by etching after forming the resist film, wherein the etching apparatus comprises an ICP (Inductive-Plasma) having a low-pressure high-density plasma source.
coupled-plasma) etching equipment, dual frequency RIE (reac)
4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is any one of a tive-ion-etching etching apparatus. 6. A method of manufacturing a semiconductor device for forming a gate electrode of a semiconductor transistor, comprising: sequentially stacking a gate oxide film, a gate electrode material, and a hard mask material on a semiconductor substrate to form a pattern corresponding to the gate electrode. After forming a resist film, an ICP (inductive-coupled-plas
ma) Etching equipment, 2 frequency RIE (reactive-ion-etc)
hing) In one of the etching apparatuses, SiO ₂ , Si
N or SiON insulating film (hard mask material)
A step of removing a deposition film deposited by using a chlorine (Cl ₂ ) gas at the time of etching the hard mask material and setting an ion energy voltage Vpp of the etching apparatus to 300 V or more; A method of manufacturing a semiconductor device, wherein electrode materials are continuously processed by the same etching apparatus, and then a source and a drain are formed by ion implantation.