JPH0697123A - Dry etching method - Google Patents

Abstract

PURPOSE:To provide a highly selective etching method for gate electrode in which SiOx based residual deposition layer on the side wall of a pattern can be removed without causing corrosion of gate oxide. CONSTITUTION:When a gate electrode 3a of poly-Si is formed through etching by the use of HBr/O2 mixture gas, a side wall protective film 5 to be formed has composition shown by SiOxBry which must thereby be removed through same principle as SiOx. Consequently, depositional material is deposited on the entire surface through discharge dissociation of a mixture gas having composition of NH3/NF3=5:1 while simultaneously etch back is performed using Ar gas thus forming a condensation layer 6a selectively on the side wall protective film 5. Since the condensation layer 6a contains F atoms, the side wall protective film 5 is decomposed and removed only from the part coming into contact with the condensation layer 6a when a wafer is heated or cleaned with pure water. At that time, gate oxide 2 composed of SiO2 is not corroded at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices, and more particularly, to a deposit layer remaining on an etching cross section in ultra-high selective etching for forming a gate electrode, for example. The present invention relates to a method for removing a gate oxide film without eroding it.

[0002]

2. Description of the Related Art As semiconductor devices have become more highly integrated and have higher performance as seen in recent VLSI, ULSI, etc., high anisotropy, high speed and high anisotropy are achieved even in the etching of silicon-based material layers. There is a strong demand for a technology that achieves various requirements such as selectivity, low damage, and low pollution without sacrificing any of them.

Among the various processes for etching the silicon-based material layer, the gate electrode processing for etching polycrystalline silicon, refractory metal silicide, polycide, etc. requires a particularly high precision. It is M so that the source / drain regions are formed in a self-aligned manner.
This is because in the manufacturing process of the OS-FET, the dimensional accuracy and cross-sectional shape of the gate electrode directly affect the channel length, the dimensional accuracy of the sidewalls for realizing the LDD structure, the source / drain region formation region, and the like. Another important reason is that it is necessary to process the gate insulating film, which has become thinner and thinner in recent years, with extremely high selectivity for the underlying layer.

Conventionally, C is used for etching silicon materials.
CFC typified by FC113 (C ₂ Cl ₃ F ₃ )
(Chlorofluorocarbon) gas has been widely used as an etching gas. Since the CFC gas has F atoms and Cl atoms in one molecule, it is possible to perform etching while adjusting the balance between the radical reaction and the ion-assisted reaction by setting the conditions, and the carbon deposited from the gas phase. Anisotropic processing can be realized while protecting the side wall with a polymer.

However, it has been pointed out that CFC gas is a cause of the ozone layer depletion of the earth as is well known, and the prohibition of its production and use is imminent. Therefore, in the field of dry etching, CFC
It is an urgent task to find gas alternatives and establish effective ways to use them. Further, if the design rules of semiconductor devices are further miniaturized in the future, it is considered that carbon-based polymer deposited from the vapor phase becomes a source of particle contamination. From this point of view, countermeasures against CFC depletion are desired.

From this background, the method of using a bromine-based etching species is becoming the mainstream of etching of the silicon-based material layer instead of the CFC gas. For example, Digest of Papers 1989 2
nd Micro Process Conference
An example of anisotropic processing of an n ⁺ -type polycrystalline silicon layer by RIE (reactive ion etching) using HBr is reported on page ce ce 190. Since Br has a large atomic radius and does not easily penetrate into the crystal lattice or the grain boundaries of the silicon-based material layer, it does not spontaneously etch the silicon-based material layer, but it has high anisotropy due to the ion assist mechanism. Can be achieved.

Another reason why Br is supported as an etching species for the silicon-based material layer is silicon oxide (S
This is because theoretically high selectivity can be obtained with respect to the underlayer made of iO ₂ ). This is the proceedings of the 36th Joint Lecture on Applied Physics (Spring Annual Meeting 1989) p. 572, Lecture No. 1p-L-7, and Monthly Semiconductor World (Press Journal, Inc.) January 1990, p.
81-84, the magnitude relationship between the interatomic bond energies depends on the Si—O bond (464 kJ / mol).
e)> Si—Br bond (368 kJ / mole), and theoretically Br does not spontaneously etch the underlying SiO ₂ -based material layer.

In particular, under the present circumstances in which the surface step of the wafer is increasing due to the progress of higher integration of semiconductor devices and the complicated device structure, a certain degree of overetching is performed in consideration of the uniformity of processing within the wafer surface. It has become essential to do so. Therefore, for example, in the processing of a gate electrode for etching a polycrystalline silicon layer, a polycide film, or the like on a thin gate insulating film, extremely high selectivity to the underlayer is required during overetching. In such a case, the use of Br is advantageous.

However, such a phenomenon that the extremely high underlayer selectivity of Br is damaged and the cross-sectional shape of the pattern is deteriorated at the time of overetching is sometimes observed. It is considered that this is because Br ^{*, which} is relatively excessive due to an extreme phenomenon of the material to be etched during overetching, causes lateral migration and attacks the sidewall surface of the pattern to cause so-called notching. Has been.

To solve this problem, for example, the third
9th Joint Lecture on Applied Physics (Spring Annual Meeting 1992)
Lecture Proceedings p. 504, Lecture No. 28p-NC-4, a technique of adding a very small amount of O ₂ to HBr is reported. This improves the resist selectivity by coating the surface of the resist mask by SiO _x type coating, thereby it is intended to prevent deterioration of the pattern shape.

It is considered that the SiO _x type coating film is formed by the desorption of Br from the deposit originally formed in the form of containing Br such as SiO _x Br _y .

[0012]

By the way, in the dry etching of the silicon-based material layer using the Br-based etching species as described above, the reaction product SiBr _x having a relatively low vapor pressure is removed by the resist mask or the etching. Adhere to the side wall surface of the pattern. This SiBr _x exerts a surface protection effect and a side wall protection effect during the progress of etching and contributes to the improvement of the resist selection ratio and the achievement of high anisotropy, but it is difficult to remove after etching. . This problem is illustrated in FIG. 1 by using the processing of polycrystalline silicon gate electrode as an example.
This will be described with reference to FIG.

In FIG. 13A, S is formed on the silicon substrate 11.
A state is shown in which a polycrystalline silicon layer 13 is formed via a gate oxide film 12 made of iO ₂ , and a resist mask 14 is selectively formed on the polycrystalline silicon layer 13. When the polycrystalline silicon layer 13 is etched using HBr gas, SiBr _x having a low vapor pressure is deposited on the pattern side wall portion where vertical ion incidence does not occur, and the side wall protection film 15 as shown in FIG. 13B is formed. It is formed. As a result, the gate electrode 13a having an anisotropic shape is formed. Moreover,
Since Br ^* is used as an etching species, the selectivity to the gate oxide film 12 at this stage is extremely high.

However, if the ordinary O ₂ plasma ashing is performed after the etching is completed, the resist mask 14 can be removed, but the side wall protective film 15 cannot be removed as shown in FIG. 13C. This is because SiBr _x forming the side wall protective film 15 is converted into SiO _x by the action of O ₂ plasma.
It will change to. If the side wall protective film 15 is left as it is, it may become a source of dust or deteriorate the coverage of the interlayer insulating film in a later step,
This causes a significant decrease in device yield.

Therefore, in a normal process, this wafer is immersed in a dilute hydrofluoric acid solution used for removing the natural oxide film to remove the oxidized side wall protective film 15.
However, this wet etching naturally erodes the gate oxide film 12 as shown in FIG. 13D. Particularly, in recent devices, the thickness of the gate oxide film is 10 in order to achieve high integration and high speed operation.
Since the thickness is extremely thin, equal to or less than nm, it is extremely difficult to control the residual film thickness in such a process.

Oxidation of SiBr _x as described above is actually a phenomenon that is very likely to occur, and it is not necessary to carry out O ₂ plasma ashing, and immediately when the wafer after etching is exposed to the atmosphere for the purpose of analysis or the like. Occurs. Therefore, as a means for removing the side wall protective film made of SiBr _x , a means for removing SiO _x must be applied substantially.

This is all the more important in the process in which a small amount of O ₂ is added to HBr to intentionally increase the SiO _x that may remain in the etching reaction system as described above. Is. Further, in the above description, the case where the etching species of the silicon-based material layer is particularly Br ^* has been dealt with, but the above problems may occur when Cl ^* is used as the etching species. The etching reaction product when Cl ^* is used is SiCl _x . Although SiCl _x has a slightly higher vapor pressure than SiBr _x , it is known that when the wafer is cooled to a predetermined temperature, it deposits on the wafer and exerts a surface protection effect, and is easily oxidized. . Therefore, its removal is S
As with iBr _x , it is an important process.

Therefore, according to the present invention, in dry etching of a silicon-based material layer, an underlying S such as a gate oxide film is formed.
It is an object of the present invention to provide a method for removing a deposit layer that has contributed to sidewall protection while maintaining high selectivity with respect to an iO _x system material layer.

[0019]

The dry etching method of the present invention is proposed in order to achieve the above-mentioned object, and a silicon-based material layer laminated on a silicon oxide-based material layer is subjected to fluorine-based etching. A first step of selectively etching with a halogen-based etching species other than the seed, and a deposition layer formed on the etching cross section of the silicon-based material layer in the first step, containing a fluorine atom A second step of selectively coating with a layer and a third step of removing the deposit layer by reacting with the condensation layer
And the steps of.

The present invention is also characterized in that the deposition layer is selectively covered with the condensation layer by depositing the condensation layer on the entire surface of the substrate and then etching it back.

In the present invention, the condensation layer is formed of NH ₃ and N 2.
It is characterized in that it is formed by a depositable substance generated in the etching reaction system by the discharge dissociation of the mixed gas with F ₃ .

The present invention is further characterized in that, in the third step, the substrate is heated or pure water is washed to react the deposit layer with the condensed layer.

[0023]

When the deposit layer and the base material layer are both made of SiO _x , the present inventor has proposed a method of selectively removing the former by exerting a chemical action only on the deposit layer. Diligently studied. As a result, it does not have any effect on SiO _x while it is present as a normal solid phase, but when it is heated or comes into contact with pure water, it releases a fluorine-based etching species to condense SiO _x. It was contemplated to form a layer to selectively cover the deposit layer. According to this method, only the deposit layer in contact with the condensed layer is removed by the action of the fluorine-based etching species,
Similarly, for example, the gate oxide film made of SiO _x is not adversely affected by erosion.

The condensation layer must, of course, only be formed on top of the deposit layer, but advantageously the deposit layer is formed substantially perpendicular to the wafer. In other words, since the deposit layer is attached to the side wall surface of the pattern where the vertical incidence of ions does not occur in principle, the condensation layer is also applied by applying the well-known method of (total surface deposition + etchback). It can be selectively left on the side wall surface.

Here, the condensation layer should be in contact with the underlying SiO _x -based material layer when the entire surface is deposited. However, since the condensed layer has no effect on SiO _x while existing as a normal solid phase as described above, there is no fear that the gate oxide film is removed, for example.

By the way, specifically, the above-mentioned condensed layer can be formed by a depositable substance produced in the etching reaction system by discharge dissociation of a mixed gas of NH ₃ and NF ₃ . This technology is described in IEICE Technical Report p. 35-36, S
It was inspired by the content reported in DM 89-48 (1989). According to this paper, the mixing ratio of NH ₃ and NF ₃ is 5: 1 in a normal downflow etching apparatus.
When microwave discharge is performed using the mixed gas described above, a condensed layer containing fluorine is formed. Moreover, this condensed layer is formed on the silicon substrate covered with the natural oxide film,
It has been reported that, if heated to 100 ° C. in a vacuum thereafter, the condensed layer is sublimated and at the same time the natural oxide film is decomposed and removed.

In the present invention, this condensed layer is used for removing the deposit layer on the pattern side wall surface.

Further, as a method of reacting the condensed layer with the deposit layer, the wafer heating as described above may be used, but pure water cleaning may be performed. In the case of washing with pure water, fluorine is eluted from the condensed layer into pure water to locally generate hydrofluoric acid, which wet-etches the deposit layer.

[0029]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 In this example, the present invention is applied to processing a polycrystalline silicon gate electrode.
Applied to HBr / O ₂Polysilicon with mixed gas
NH layer after etching₃/ NF₃For mixed gas
Then, a condensed layer is deposited on the entire surface, and this is etched with Ar gas.
Etching by further heating the wafer
This is an example in which the side wall protective film formed during the etching is removed. This program
The process will be described with reference to FIGS.

The wafer used as an etching sample in this example is shown in FIG. In this wafer, a polycrystalline silicon layer 3 containing an n ⁺ -type impurity is formed on a silicon substrate 1 through a gate oxide film 2 of SiO _{2 having} a thickness of about 10 nm, and a predetermined shape is formed on the polycrystalline silicon layer 3. The patterned resist mask 4 is formed.

This wafer was set in a magnetic field microwave plasma etching apparatus of RF bias application type, and as an example, the polycrystalline silicon layer 3 was etched under the following conditions. HBr flow rate 120 SCCM O ₂ flow rate 4 SCCM Gas pressure 0.6 Pa Microwave power 120 W (2.45 GH
z) RF bias power 20 W (2 MHz) Wafer temperature 0 ° C. (using alcohol type refrigerant) In this process, the radical reaction by Br ^* generated from HBr is caused by incident ion energy such as O _x ⁺ , Br ^+. Etching progressed by the assisted mechanism. At this time, etching reaction products such as SiO _x Br _y are deposited on the side wall of the pattern on the wafer cooled at a low temperature.
The side wall protective film 4 as shown in FIG. 2 was formed.

O is used as the etching gas.₂Includes
Since it is rare, the upper surface of the resist mask 4 and the gate
SiO₂The exposed surface of the film 2 also contains some SiO not shown._x
Br _yIs attached.

Next, this wafer was set in a downstream type etching apparatus for generating plasma by microwave discharge, and as an example, a condensed layer was formed under the following conditions. NH ₃ flow rate 1000 SCCM NF ₃ flow rate 200 SCCM Gas pressure 133 Pa Microwave power 1000 W (2.45 GH
z) This process proceeded under the condition that charged particles were not incident on the wafer, and the condensed layer 6 containing F atoms was deposited on the entire surface of the wafer as shown in FIG. At this time, at least in the vicinity of the interface between the side wall protective film 5 and the condensed layer 6, the etching product SiF ₄ due to F ^* of the side wall protective film 5 reacts with the product NF ₄ F in the gas phase, and (NH ₄ ) It is considered that a compound having a composition of ₂ SiF ₆ is formed.

Next, this wafer was returned to the magnetic field microwave plasma etching apparatus again, and the condensed layer 6 was etched back under the following conditions as an example. Ar flow rate 100 SCCM Gas pressure 1.0 Pa Microwave power 850 W (2.45 GH
z) RF bias power 30 W (2 MHz) In this process, the condensing layer 6 is anisotropically etched by the sputter etching with Ar ⁺ , and as shown in FIG. The condensation layer 6a was selectively left on the above.

When the wafer was further heated to about 100 ° C., the deposit layer 5 and the condensed layer 6 were quickly removed as shown in FIG. At this time, since the condensed layer 6 did not exist on the gate oxide film 2, the gate oxide film 2 was not corroded at all. Finally, normal O ₂ plasma ashing was performed to remove the resist mask 4 as shown in FIG. Through the above process, the gate electrode 3a having a good anisotropic shape could be formed without leaving the residue of the sidewall protection film 5 on the wafer and without damaging the gate oxide film 2.

[0037] Example 2 This example of the present invention is applied to a tungsten polycide gate electrode processing, the upper side of the tungsten silicide (WSi _x) layer Cl ₂ / O ₂ mixed gas, the lower-side polycrystalline After the silicon layer is etched using HBr / O ₂ mixed gas, the sidewall protection film formed in these etching processes is reacted with the condensed layer formed using NH ₃ / NF ₃ mixed gas through pure water cleaning. It is the example removed by doing so. This process will be described with reference to FIGS. Reference numerals in these drawings are partially common to those in FIGS. 1 to 6 described above.

The wafer used as an etching sample in this example is shown in FIG. In this wafer, a tungsten polycide film 9 is formed on a silicon substrate 1 via a gate oxide film 2 made of SiO ₂ and having a thickness of about 10 nm, and a resist mask 4 is further formed thereon. . The tungsten polycide film 9 is formed by stacking a polycrystalline silicon layer 7 containing an n ⁺ -type impurity and a WSi _x layer 8 in this order from the lower layer side.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the WSi _x layer 8 was first etched under the following conditions. Cl ₂ flow rate 80 SCCM O ₂ flow rate 20 SCCM Gas pressure 0.6 Pa Microwave power 1200 W (2.45 GH
z) RF bias power 30 W (2 MHz) Wafer temperature 20 ° C. Cl ₂ was used instead of HBr in this etching process because when bromide vapor pressure of W (tungsten) was taken into consideration Because it is difficult. The reaction product SiO _x Cl _{y at} this time was mainly deposited on the side wall surface of the pattern, and the side wall protective film 10 was formed as shown in FIG. Due to the contribution of the sidewall protection film 10, the WSi _x pattern 8a having an anisotropic shape was formed.

Next, as an example, the polycrystalline silicon layer 7 was etched under the following conditions. HBr flow rate 80 SCCM O ₂ flow rate 20 SCCM Gas pressure 0.6 Pa Microwave power 1200 W (2.45 GH
z) RF bias power 20 W (2 MHz) Wafer temperature 0 ° C. Generally, in etching a polycide film, it overcomes the problem of ensuring anisotropy for both two types of material layers having different etching characteristics. It is necessary to prevent the occurrence of undercut or the like in the polycrystalline silicon layer. According to the above etching conditions, a high selection ratio with respect to the gate oxide film 2 is obtained due to the effects of using Br ^* as the etching species, reducing the RF bias power, and lowering the wafer temperature. Highly anisotropic etching proceeded while maintaining. As a result, the polycrystalline silicon pattern 5a having a good anisotropic shape can be formed as shown in FIG. 9, and thus the gate electrode 9a having a good anisotropic shape is formed.

In this etching process, the first embodiment is used.
By the mechanism described above in_xBr _ySide wall protection
The film 5 was formed.

Next, a microwave discharge was performed under the same conditions as in Example 1 using a NH ₃ / NF ₃ mixed gas, and the entire surface of the wafer was covered with the condensed layer 6 as shown in FIG. Further, the condensing layer 6 was etched back using Ar gas under the same conditions as in the example, and as shown in FIG. 11, the condensing layer 6a was selectively left on the sidewall protective films 5 and 10.

Finally, when this wafer was washed with pure water, fluorine was eluted from the condensed layer 6a into the pure water, and hydrofluoric acid (HF) was locally produced in the vicinity of the side wall protective films 5 and 10. This hydrofluoric acid is SiO _x Cl _y or SiO _x B
permeating into the porous side wall protective films 5 and 10 made of r _y ,
This was decomposed and removed. Since this process is a liquid phase reaction,
It is possible that hydrofluoric acid diffuses in water and affects the gate oxide film 2, but in reality, this effect can be ignored. The reason is that the generation of hydrofluoric acid is local as described above, the concentration of hydrofluoric acid in the vicinity of the gate oxide film 2 is extremely low because the cleaning is performed under running water, and the composition of the gate oxide film 2 is chemical. It is stoichiometric and excellent in film quality, and is much more stable than the side wall protection films 5 and 10 even with the same SiO _x type material.

Although the present invention has been described based on the two embodiments, the present invention is not limited to these embodiments. For example, the structure of the wafer, the etching conditions, the type of the etching apparatus, etc. It goes without saying that it can be changed as appropriate.

[0045]

As is apparent from the above description, according to the dry etching method of the present invention, the deposit layer generated when the gate processing is performed based on the ultra-high selection process has a thin base layer. It can be removed without eroding the gate oxide film. As a result, the device yield can be significantly improved.

Therefore, the present invention is suitable for manufacturing a semiconductor device designed according to a fine design rule and having a high degree of integration and high performance.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a process in which the present invention is applied to processing a polycrystalline silicon gate electrode, in which a polycrystalline silicon layer is laminated on a silicon substrate via a gate oxide film,
It is a schematic sectional drawing which shows the state of the wafer before the etching in which the mask was formed.

FIG. 2 is a schematic cross-sectional view showing a state where the polycrystalline silicon layer of FIG. 1 is etched to form a sidewall protective film.

3 is a schematic cross-sectional view showing a state where the entire surface of the wafer in FIG. 2 is covered with a condensation layer.

FIG. 4 is a schematic cross-sectional view showing a state in which the condensation layer of FIG. 3 is etched back and selectively left on the sidewall protective film.

5 is a schematic cross-sectional view showing a state in which the condensation layer of FIG. 4 is removed together with the sidewall protective film.

6 is a schematic cross-sectional view showing a state where the resist mask of FIG. 5 is ashed.

FIG. 7 is a wafer before etching in which a resist mask is formed by stacking a tungsten polycide film on a silicon substrate via a gate oxide film in a process example in which the present invention is applied to processing a tungsten polycide gate electrode. It is a schematic sectional drawing which shows the state of.

FIG. 8 is a schematic cross-sectional view showing a state in which the WSi _x layer of FIG. 7 is etched and a side wall protective film is formed.

9 is a schematic cross-sectional view showing a state where the polycrystalline silicon layer of FIG. 8 is etched to form a sidewall protective film.

10 is a schematic cross-sectional view showing a state in which the entire surface of the wafer in FIG. 9 is covered with a condensation layer.

FIG. 11 is a schematic cross-sectional view showing a state in which the condensed layer of FIG. 10 is etched back and selectively left on the sidewall protective film.

FIG. 12 is a schematic cross-sectional view showing a state in which the condensation layer of FIG. 11 is removed together with the sidewall protective film.

FIG. 13 is a schematic cross-sectional view for explaining a problem in processing a conventional polycrystalline silicon gate electrode, FIG.
Is a state of the wafer before etching, (b) is a state in which the polycrystalline silicon layer is etched to form a side wall protective film,
(C) shows a state where the sidewall protection film remains after the resist mask is ashed, and (d) shows a state where the gate oxide film is eroded when the sidewall protection film is wet-etched.

[Explanation of symbols]

1 ... Silicon substrate 2 ... Gate oxide film 3, 7 ... Polycrystalline silicon layer 3a ... (Polycrystalline silicon) gate electrode 4 ... Resist mask 5 ... Side wall protective film (SiO 2) _x Br _y ) 6 ... Condensed layer 6a ... (After etchback) condensed layer 8 ... WSi _x layer 9 ... Tungsten polycide film 9a ... (Polycide) gate electrode 10 ... Side wall protective film (SiO _x Cl _y )

Claims (4)

[Claims] 1. A first step of selectively etching a silicon-based material layer laminated on a silicon oxide-based material layer using a halogen-based etching species other than a fluorine-based etching species, and in the first step, A second step of selectively covering the deposit layer formed on the etched cross section of the silicon-based material layer with a condensation layer containing fluorine atoms; and removing the deposit layer by reacting with the condensation layer. And a third step of performing the dry etching method. 2. The selective coating of the deposit layer with the condensing layer is performed by depositing the condensing layer on the entire surface of the substrate and then etching back the same. The dry etching method described. 3. The condensing layer is formed of a depositable substance generated in an etching reaction system by discharge dissociation of a mixed gas of NH ₃ and NF ₃ . The dry etching method according to claim 1. 4. The method according to claim 1, wherein in the third step, the deposit layer and the condensed layer are reacted by heating the substrate or cleaning the substrate with pure water. The dry etching method according to item 1.