JP3225559B2 - Dry etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of semiconductor device manufacturing and the like, and more particularly to a method for performing anisotropic etching while protecting a side wall with a substance other than a carbon-based polymer. Furthermore, the present invention prevents generation of etching residues and reattachment, deterioration of a pattern cross-sectional shape, and the like, even when a wiring material layer is significantly over-etched, for example, on a wafer having a large step in a multilayer wiring process. About the method.

[0002]

2. Description of the Related Art As the integration and performance of semiconductor devices have increased as seen in recent VLSIs and ULSIs, silicon-based materials such as single crystal silicon, polycrystal silicon, refractory metal silicide, and polycide have been developed. In the etching of a material layer or an Al-based material layer, there is a strong demand for a technique that does not sacrifice any of requirements such as high anisotropy, high speed, high selectivity, and low contamination. .

[0003] For example, a typical etching process for single crystal silicon is trench processing for forming a trench for the purpose of isolating fine elements and securing a cell capacitance area. In the trench processing, high anisotropy is required in order to accurately control the filling of the trench and the capacitance in a later step. On the other hand, a typical etching process for polycrystalline silicon, refractory metal silicide, polycide, or the like is gate electrode processing. In gate electrode processing, high anisotropy is also required because the pattern width directly affects the channel length when the source / drain regions of the transistor are formed in a self-aligned manner and the dimensional accuracy of the sidewall in the LDD structure. . Also, high selectivity for a thin gate oxide film is required.

Further, the etching process of the Al-based material layer is, of course, various kinds of wiring processing. Al
A problem specific to the etching of the system material layer is how to prevent after-corrosion.

[0005] By the way, as the device structure becomes more three-dimensional, the surface step of the wafer necessarily increases, and in response to this, significant over-etching has recently been required. On a large step, the thickness of the various material layers formed is likely to be non-uniform, and due to the shape effect of the wafer surface, in a narrow portion such as the bottom of the step, a decrease in the incident amount of the etching species and a decrease in the amount of etching reaction products are caused. The vapor pressure tends to decrease. Due to these causes, at the stage where the just etching is completed, an etching residue called a stringer often remains at the bottom of the step. To remove this, over-etching is indispensable.

However, at the time of over-etching, it is generally difficult to achieve both high anisotropy and high selectivity. this is,
This is because radicals that become relatively excessive with the decrease in the area to be etched cause migration on the surface of the wafer and attack the pattern side wall to deteriorate the cross-sectional shape of the pattern. However, if the etching conditions are set such that the ion assist reaction is the main component in consideration of such a decrease in anisotropy, the underlayer may be damaged or the sputtered underlayer may be formed on the pattern side wall. The problem of redeposition occurs. In particular, silicon oxide (S
When an Al-based material layer is etched using an iO ₂ ) -based interlayer insulating film as a base, such a redeposit on the base tends to occlude residual chlorine and promote after-corrosion. I want to prevent it.

What has conventionally played an important role in solving the above-mentioned problems is protection of the side wall by a carbon-based polymer. For the etching of the silicon-based material layer, a chlorofluorocarbon (CFC) gas typified by CFC113 (C ₂ Cl ₃ F ₃ ) has been widely used as an etching gas. The CFC gas, which is a kind of so-called chlorofluorocarbon gas, has F and Cl as constituent elements in one molecule. Therefore, depending on conditions, a radical reaction due to radicals such as F ^* and Cl ^* and C ⁺ , CF _x ⁺ , CC
Etching can be advanced by both ion assist reactions with ions such as l _x ⁺ and Cl ⁺ . In this case, fragments of the CFC gas generated under discharge dissociation conditions polymerize to form a carbon-based polymer in the plasma, which deposits on the pattern side wall portion of the wafer surface and exerts a side wall protection effect. Anisotropy is achieved.

If the protection of the side wall by the carbon-based polymer is strengthened, both high anisotropy and high selectivity can be achieved. In other words, high selectivity is achieved by lowering the incident ion energy within a range that does not impair the practical etching rate, and a possible reduction in anisotropy is to be avoided by strengthening the sidewall protection. is there. A typical example is the 36th Joint Lecture on Applied Physics (1)
(Spring, 989) is described in the 2nd volume of the proceedings of the lecture, pp. 571, Abstract No. 1p-L-5. The tungsten polycide film is made of C ₂ Cl ₃ F ₃ (Freon 113) / SF ₆
Etching is performed using a mixed gas and a SiO ₂ mask.

In the case of an Al-based material layer, the carbon-based polymer is supplied from a resist mask. The etching of the Al-based material layer is performed using a chlorine-based gas typified by a BCl ₃ / Cl ₂ mixed gas. Since the reaction between Al and Cl proceeds spontaneously, in order to ensure anisotropy, etching is performed by extending the mean free path of ions under conditions of low gas pressure and high bias. At this time, the resist sputtered by ions having high incident energy
The decomposition products of the mask form a carbon-based polymer, which adheres to the pattern side wall to exert a side wall protecting effect.

On the other hand, there has been proposed a technique which does not achieve high anisotropy by the side wall protecting action of the carbon-based polymer as described above but achieves this by lowering the temperature of the substrate to be etched (wafer). . This is a process called low-temperature etching, in which the temperature of the wafer is reduced to zero.
By keeping the temperature below ℃, the radical reaction on the pattern side wall is frozen or suppressed to prevent shape abnormalities such as undercut while maintaining the etching rate in the depth direction at a practical level by the ion assist effect. Technology. For example, in the 35th Annual Meeting of the Japan Society of Applied Physics (Spring Annual Meeting, 1988), 495 pages of abstracts and abstract numbers 28a-G-2, the wafers were stored at −130 ° C.
In this case, the silicon trench etching and the n ⁺ -type polycrystalline silicon layer were etched using SF ₆ gas.

In general, in a dry etching process, unless the wafer is cooled, the temperature of the wafer rises to around 200 ° C. due to plasma radiation heat, reaction heat, and the like. May be included in low-temperature etching.

[0012]

However, a method for utilizing the above-mentioned carbon-based polymer for protecting the side wall is as follows.
The following problems have been pointed out. First, the CFC gas, which is the etching gas for the silicon-based material layer, is a well-known cause of the ozone depletion of the earth, and some of them will be prohibited from being manufactured and used in the near future. That is. Therefore, it is urgently necessary to find a substitute for CFC gas in the field of dry etching and to establish an effective use method.

The second problem is that in the etching of the silicon-based material layer, carbon contained in the CFC gas deteriorates the selectivity to the SiO ₂ -based material layer. This issue was addressed in the 36th Joint Lecture on Applied Physics (1989)
Spring), Lecture Proceedings, 2nd Volume, 572 pages, Abstract No. 1p-L-7, or Monthly Semiconductor World (Press Journal), January 1990, 81-8
It is reported in literature such as four pages. When carbon is adsorbed on the surface of a SiO ₂ material layer such as a gate oxide film, a C—O bond having a large interatomic bond energy (257 kcal) is formed.
/ Mole) to weaken the Si—O bond,
Alternatively, SiO ₂ is reduced to Si and easily extracted by halogen-based etching species. This is a serious problem when a gate electrode is processed using a thin gate oxide film as a base.

Third, there are concerns about particle contamination and after-corrosion by the carbon-based polymer. That is, if the design rules of semiconductor devices are further refined in the future, it is fully expected that carbon polymers deposited from the gas phase will also be a significant source of particle contamination. Further, particularly in the etching of the Al-based material layer, chlorine or a chlorine-based compound is occluded in the carbon-based polymer attached to the pattern side wall, and these residual chlorines cause after-corrosion. In recent years, Cu is added to the Al-based material layer as a countermeasure against electromigration, or the Al-based material layer is laminated with a different material layer such as a barrier metal or an antireflection film. Because of the increasing number of factors, there is a need for a sidewall protective material to replace carbon-based polymers.

Although the use of a deposition gas other than the CFC gas has been studied in some cases, if the design rules of semiconductor devices are further refined in the future, such a problem may not occur in the past. Even with particles having a particle size, there is a great possibility that the yield will be seriously reduced.

On the other hand, the aforementioned low-temperature etching removes C
It is expected to be one of the effective means of FC measures. However, if only the freezing or suppression of the radical reaction is to be achieved to achieve high anisotropy, low-temperature cooling requiring liquid nitrogen is required as described above. . However, this raises hardware problems such as the necessity of a large and special cooling device and the reduction of the reliability of the vacuum sealing material. In addition, there is a concern that the cooling of the wafer and the heating until returning to the room temperature take a long time to lower the throughput, and there is a great possibility that economic efficiency and productivity may be impaired.

Therefore, the present invention can protect the side wall with another material instead of the carbon-based polymer, can maintain high anisotropy and low damage even when performing large over-etching, and can reduce the contamination. It is an object of the present invention to provide a practical dry etching method which is excellent in economy.

[0018]

In order to achieve the above-mentioned object, the present invention provides an etching gas containing a nitrogen-based compound and a sulfur-based compound capable of producing free sulfur in plasma under discharge dissociation conditions. In the method, the material layer to be etched on the substrate is etched while a sulfur nitride-based compound is deposited on the surface of the material layer to be etched on the substrate.

The present invention is also directed to a method for manufacturing a semiconductor device, wherein the material layer to be etched is on a substrate having a step on the surface, and after the etching of the material layer to be etched is completed, the residue of the material layer to be etched remains at the bottom of the step. Is further removed under an etching condition in which a radical reaction is mainly performed. Here, desirably, the temperature of the substrate is set to 130 ° C. or lower.

[0020]

The present inventor has made the following solution in order to achieve the above object. In other words, from the viewpoint of preventing particle contamination, the side wall protective material is deposited only under a specific condition, and when unnecessary, a material which can be easily removed by any means such as sublimation, decomposition, or generation of a volatile substance. Use. Moreover, it is necessary to select a material having sufficient resistance to ion bombardment and excessive radicals as the above-mentioned side wall protective material. In addition, the overetching is performed under a condition mainly including a radical reaction in order to avoid an adverse effect on a base and to remove an etching residue remaining in a narrow portion such as a step bottom. At this time,
From the viewpoint of protecting the pattern side wall portion from the attack of excessive radicals, a material having high resistance is required as the side wall protection material.

In the course of studying in accordance with the above policy, the compound which the present inventors have noticed as a sidewall protective material is a sulfur nitride-based compound. As the sulfur nitride-based compound, various compounds are known as described below.
In the present invention, a typical compound expected to have a particularly excellent side wall protection effect is polythiazyl (SN) _x . (S
N) For the properties and structure of _x , see Am. Che
m. Soc. , Vol. 29, p. 6358-6363
(1975). 208 ° C under normal pressure,
It is a polymeric substance that exists stably at around 140 to 150 ° C. under reduced pressure, and in a crystalline state, SNSN-.
Are oriented parallel to each other. Therefore, the sulfur nitride-based compound layer mainly composed of (SN) _x can effectively prevent the penetration of F ^{* and the} like. Also, even if accelerated ions enter,
A so-called sponge effect is exhibited due to a change in the bond angle or conformation, and the ion impact can be absorbed or reduced. Moreover, (SN) _x is 140 to 1 under reduced pressure.
When heated to around 50 ° C., it can be easily decomposed or sublimated and completely removed.

In the present invention, in order to generate (SN) _x , an etching gas containing a nitrogen-based compound and a sulfur-based compound capable of generating free sulfur in plasma by discharge dissociation is used. This is because a reaction of both compounds generates a sulfur nitride-based compound in the gas phase and deposits the compound on the surface of the wafer to protect the side wall. That is, in the simplest case, N generated in the plasma by the discharge dissociation of the nitrogen-based compound and S generated in the plasma by the discharge dissociation of the sulfur-based compound combine to form thiazyl (N≡S) first. It is formed. This thiazil
It has unpaired electrons as inferred from the structure of nitric oxide (NO), which is an oxygen analog, and easily polymerizes (S
N) ₂ , (SN) ₄ , and (SN) _n .
(SN) ₂ readily polymerizes at around 20 ° C. to produce (SN) ₄ and (SN) _n , which itself decomposes at around 30 ° C. (SN) ₄ is a cyclic substance having a melting point of 178 ° C. and a decomposition temperature of 206 ° C. (SN) _x is chemically stable and does not decompose up to 130 ° C. Therefore, when the wafer temperature is approximately 1
If the temperature is controlled to 30 ° C. or lower, (SN) _x can be stably present on the wafer.

In addition, F ^* , Cl ^* , Br in the plasma
^When a halogen radical such as ^* exists, a thiazyl halide in which a halogen atom is bonded to the S atom of the above (SN) _x can also be formed. When a hydrogen-based gas is added to control the amount of F ^* generated, thiazyl hydrogen may also be generated. Further, depending on conditions, S ₄
N ₂ (melting point 23 ° C.), S ₁₁ N ₂ (melting point 150-155)
° C), S ₁₅ N ₂ (melting point 137 ° C), S ₁₆ N ₂ (melting point 12
(2 ° C.), etc., in which the number of S atoms and the number of N atoms in the molecule are unbalanced, or S ₇ NH in which H atoms are bonded to N atoms of these cyclic sulfur nitride compounds (melting point: 113.5). _{℃), 1,3-S 6 (} NH) 2 ( melting point 130
° C), 1,4-S ₆ (NH) ₂ (melting point 133 ° C),
5-S ₆ (NH) ₂ (melting point: 155 ° C.), 1,3,5-S
₅ (NH) ₃ (melting point 124 ° C), 1,3,6-S ₅ (N
H) ₃ (melting point 131 ° C.), S ₄ (NH) ₄ (melting point 145)
C) can also be produced.

All of the above-mentioned sulfur nitride-based compounds can be stably present on the wafer under the temperature condition on the wafer mounting electrode of a normal dry etching apparatus.
A sidewall protective film sufficient to protect the pattern sidewall from attack by radicals is formed. In the first aspect of the present invention, highly anisotropic processing can be performed by performing etching in a system in which the deposition process of the sulfur nitride-based compound and the etching process compete with each other.

In addition, the present invention includes a step of removing the residue of the material layer to be etched remaining on the bottom of the step under the etching conditions mainly involving a radical reaction after the above-described etching is performed. Since the side wall protecting effect of the sulfur compound is extremely excellent, there is no possibility that the anisotropic shape of the already formed pattern is impaired. In addition, the sulfur nitride-based compound heats the wafer at approximately 130 ° C.
Decomposes when heated above. Alternatively, when the resist mask is removed by ordinary O ₂ plasma ashing, it can be removed simultaneously with the resist mask by sublimation, combustion or decomposition reaction. The reaction product at this time is a gas such as N ₂ , NO _x , SO _x , or solid vapor of S, and does not cause any particle contamination.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Embodiment 1 This embodiment is an example in which the first invention of the present application is applied to processing of a gate electrode, and a polycrystalline silicon layer is etched using an S ₂ Cl ₂ / N ₂ mixed gas. This process will be described with reference to FIG. As shown in FIG. 1A, a wafer used as an etching sample in this embodiment is a gate oxide film 2 made of SiO ₂ on a single crystal silicon substrate 1.
And a polycrystalline silicon layer 3 having a thickness of about 0.3 μm containing an n ⁺ -type impurity is laminated thereon, and a resist mask 4 patterned in a predetermined shape is formed thereon. Here, the resist mask 4
Is formed to a pattern width of about 0.5 μm by performing g-line exposure and development processing on a coating film of a novolak-based positive photoresist material (trade name: TSMR-V3, manufactured by Tokyo Ohka Kogyo Co., Ltd.). did.

Next, in order to etch the polycrystalline silicon layer 3, the wafer was set on a wafer mounting electrode of an RF bias applying type magnetic field microwave plasma etching apparatus. The wafer mounting electrode has a built-in cooling pipe, and the wafer can be cooled to a predetermined temperature by receiving a supply of an appropriate coolant from a cooling facility such as a chiller installed outside the apparatus. Here, an ethanol refrigerant was used. An example of the etching conditions is shown below.

S ₂ Cl ₂ flow rate 10 SCCM N ₂ flow rate 10 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 30 W (2 MHz) Wafer temperature 20 ° C.

Here, S ₂ Cl ₂ is one of the sulfur chlorides which the present inventor previously proposed as an etching gas for a silicon-based material layer or an Al-based material layer in Japanese Patent Application No. 3-210516. Yes, very effective de-C
It provides FC measures. Cl ^* generated from S ₂ Cl ₂ contributes as a main etching species of the polycrystalline silicon layer 3, and etching proceeds by a mechanism in which this radical reaction is assisted by ions such as SF _x ⁺ , S ⁺ , and N ⁺ . . On the other hand, S generated from S ₂ Cl ₂ and N ₂ reacted to generate sulfur nitride-based compounds such as (SN) _{x in the} plasma. These sulfur nitride-based compounds are deposited on the side walls of the pattern in which normal incidence of ions does not occur in principle on the surface of the wafer maintained at 20 ° C., and FIG.
Was formed as shown in FIG. As a result,
The gate electrode 3a having a good anisotropic shape was formed.

N ₂ captures a part of F ^* generated from S ₂ F ₂ by N ^* generated by itself and removes it out of the system in the form of NF ₃ or the like. It also contributes to increasing the F ratio to promote the production of sulfur nitride-based compounds. In the above process, high selectivity was also achieved.
This is because the deposition rate of the sulfur nitride-based compound and the sputter removal compete on the vertically incident surface of the ions such as the upper surface of the resist mask 4 and the exposed surface of the gate oxide film 2, so that the etching rate is greatly reduced. is there. In addition, since the product from the gas phase is used for protecting the side wall, the incident ion energy required for anisotropic processing can be reduced. In this embodiment, the selectivity for the resist mask is about 10, and the selectivity for the gate oxide is about 30.
Met.

Next, the wafer was transferred to a plasma ashing apparatus, and the resist mask 4 was removed under conditions for performing ordinary O ₂ plasma ashing. In this step, a direct combustion reaction due to O ^* occurs in addition to the heating effect of plasma radiation heat or reaction heat, so that as shown in FIG. 1 (c), the sidewall protective film 5 made of a sulfur nitride-based compound is decomposed. NO _x , N ₂ , SO _x ,
It was quickly removed in the form of S or the like. Therefore, no particle contamination occurred on the wafer.

Alternatively, most of the sulfur nitride compounds are 1
If the wafer is heated to about 50 ° C., it will be decomposed, so the wafer may be heated first to remove the side wall protective film 5 and then the resist mask 4 may be removed by O ₂ plasma ashing. In the present invention, an extremely clean process can be realized by taking measures to prevent the sulfur nitride-based compound generated during etching from being excessively deposited inside the etching apparatus. For example, by heating an internal member of an etching apparatus that does not directly affect the wafer temperature, such as an inner wall portion of an etching chamber, to 150 ° C. or more by a built-in heater or the like, it is necessary to prevent particle contamination. It is an effective means.

Embodiment 2 This embodiment is an example in which the first invention of the present application is applied to processing of a gate electrode, and a polycrystalline silicon layer is etched using a mixed gas of S ₂ Cl ₂ / N ₂ / H ₂ S. is there. This process will be described with reference to FIG. 2 in addition to FIG. The wafer used as a sample in this embodiment is the same as that shown in FIG. This wafer is RF
The polycrystalline silicon layer 3 was etched under the following conditions, as set in a bias-applied magnetic field microwave plasma etching apparatus.

S ₂ Cl ₂ flow rate 10 SCCM N ₂ flow rate 10 SCCM H ₂ S flow rate 3 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 30 W (2 MHz) Wafer temperature 20 ° C.

Under the above etching conditions, H ₂ S is added to the composition of the etching gas used in the first embodiment. This H ₂ S captures Cl ^* with H ^* released by itself and releases free S at the same time. The apparent S / X ratio of the etching reaction system [the ratio of the number of S atoms to the number of halogen (X) atoms] ] Is efficiently increased. For this reason, as shown in FIG. 2, the formation of the sidewall protective film 5 mainly composed of (SN) _x was promoted, and the cross-sectional shape of the gate electrode 3b was tapered.

As described above, in the present invention, it is possible to change the sectional shape of the formed pattern by controlling the amount of the sulfur nitride-based compound deposited. For example,
The above-described tapering is performed in the manufacturing process of the CCD.
If performed on the second polysilicon layer, the step coverage of the interlayer insulating film is improved, and it becomes easy to prevent the generation of stringers at the time of etching the second and subsequent polysilicon layers.

Embodiment 3 In this embodiment, the first invention of the present application is applied to processing of a gate electrode, and two-step etching using a mixed gas of S ₂ F ₂ / N _{2 and a} mixed gas of S ₂ Br ₂ / N _{2 is performed.} With tungsten
This is an example in which a polycide film is etched. This process will be described with reference to FIG.

The wafer used in this embodiment is shown in FIG.
As shown in FIG.
_A polycide film 15 through a gate oxide film 12 of
Are laminated, and a resist mask 16 patterned in a predetermined shape is further formed thereon. Here, the polycide film 15, and the lower-side thickness of about 0.1μm polysilicon layer 13 and the thickness of about 0.1μm tungsten silicide of containing n-type impurity in this order from the (WSi _x) layer 14 These are sequentially laminated.

[0040] Set the above wafer RF bias application type magnetic field microwave plasma etching apparatus, for example, under the following conditions, firstly the upper layer side of the WSi _x layer 1
4 was etched. S ₂ F ₂ flow rate 10 SCCM N ₂ flow rate 10 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 30 W (2 MHz) Wafer temperature 20 ° C.

Here, S ₂ F ₂ is one of the sulfur fluorides used by the present inventor for etching a silicon-based material layer and the like in Japanese Patent Application No. 3-210516. The F ^* generated from S ₂ F _2, and serve as main etching species WSi _x layer 14, the radical reaction is SF
Etching proceeds by a mechanism assisted by ions such as _x ⁺ and S ⁺ . Further, the sidewall protective film 17 made of the sulfur nitride-based compound was formed based on the above-described mechanism. As a result, as shown in FIG. 3 (b), WSi _x pattern 14a having a highly anisotropic shape was formed.

By the way, although the etching of the WSi _x layer is F-based gas it has been conventionally used, which is a Cl-based gas and Br-based gas low vapor pressure of WCl _x and WBr _x to generate, etching progresses This is because anisotropic etching becomes difficult due to excessive attachment of these products even if they do not proceed. However, when an F-based gas is used, a decrease in the anisotropy due to F ^* is a major obstacle. Therefore, conventionally, sidewall protection is performed using a carbon-based polymer derived from a CFC gas, or a wafer having a low temperature of -60 ° C. This was to ensure high anisotropy by cooling.

On the other hand, in the present invention, since the strong side wall protective film 17 made of the sulfur nitride-based compound can be easily formed at around room temperature, it is possible to perform etching much more practically than before.
The process is realized.

Next, in order to etch the lower polycrystalline silicon layer 13, the etching conditions were switched as follows as an example. S ₂ Br ₂ flow rate 10 SCCM N ₂ flow rate 10 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W RF bias power 30 W (400 kHz) Wafer temperature 20 ° C. Here, S ₂ F ₂ of the etching gas composition is changed to S _2. B
The reason for changing to r ₂ is to improve the selectivity to the underlying gate oxide film 12 by excluding F ^* from the etching reaction system and using Br ^* generated from S ₂ Br ₂ as the main etching species. is there. The formation mechanism of the sulfur nitride-based compound is as described above. As a result, as shown in FIG. 3C, the gate electrode 1 having a favorable anisotropic shape is formed.
5a was formed. In the drawing, each material layer pattern after etching is indicated by adding a suffix a to the code of each material layer before etching.

In the process up to this point, the resist
The selectivity for the mask 16 was about 8, and the selectivity for the gate oxide film 12 was about 100. The selectivity to the resist is slightly lower than that of Example 1, WSi _x layer 14
This is because the resist mask 16 is slightly etched by F ^* generated from S ₂ F ₂ at the time of etching.

Finally, when O ₂ plasma ashing was performed, the resist mask 16 and the side wall protective film 17 were removed as shown in FIG. At this time,
No particle contamination occurred.

Embodiment 4 In this embodiment, the second invention of the present application is applied to bit line processing of an SRAM, and a tungsten polycide film is etched to a just-etched state using an S ₂ F ₂ / N ₂ mixed gas. After that, the residue is removed by performing over-etching using SF ₆ gas. This process will be described with reference to FIGS.

FIG. 4 is a schematic sectional view showing an example of the configuration of a wafer before etching. That is, a word line 25 of a first polycide film is formed on a single crystal silicon substrate 21 on which a shallow trench type element isolation region 22 is formed in advance via a gate oxide film made of SiO ₂ . The word line 25 is connected to the lower polycrystalline silicon layer 23.
And the WSi _x layer 24 of the upper side in which are stacked. Further, the entire surface of the wafer is made of Si
Interlayer insulating film 26 formed by depositing O ₂
And a second layer of polycide film 29 thereon.
Are formed. The second layer polycide film 29 are those with the lower layer side of the polycrystalline silicon layer 27 and the upper side of the WSi _x layer 28 are laminated to form a part of the bit line. Further, a resist mask 30 is formed on the second layer polycide film 29. This resist
The mask 30 is formed, for example, by applying a chemically amplified negative type three-component photoresist (manufactured by Shipley; trade name: SAL-601) to a thickness capable of absorbing the surface step of the wafer, and using a KrF excimer laser stepper. After the selective exposure, it is formed through an alkali developing treatment.

The above-mentioned wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the second polycide film 29 was etched under the following conditions. S ₂ F ₂ flow rate 35 SCCM N ₂ flow rate 15 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 100 W (2 MHz) Wafer temperature −30 ° C. This etching process is shown in FIG. As described above, the etching of the second polycide film 29 proceeded anisotropically with the formation of the sidewall protective film 31. As a result, a bit line 29a having a substantially vertical wall was formed. Each material layer after patterning is represented by adding a suffix a to the original code (number).

However, since this wafer has a large surface step, an unnecessary portion of the second polycide film 29 is not completely removed, and a residue 29b is generated at the bottom of the step or at a portion where the pattern is dense. I was This residue 29
b is mainly composed of polycrystalline silicon layer 27, but also includes a portion of the WSi _x layer 28 by location. The residue 29b is generated as described above because the above-mentioned portions are all narrow, and the incidence probability of the etching species and the vapor pressure of the reaction product are easily reduced.

Therefore, in order to remove the residue 29b,
The etching conditions were changed as follows as an example. SF ₆ flow rate 50 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 0 W Here, the etching conditions in which a radical reaction is mainly set are set. That is, SF ₆ has the lowest S / F ratio among sulfur fluorides and generates a large amount of F ^* from one molecule. Due to this large amount of F ^* , as shown in FIG.
Residue 29b was quickly removed. At this time, the side wall protective film 31 formed in the steps up to the above-described just etching exhibits extremely excellent chemical and physical resistance to the lateral attack of radicals or the incidence of ions. The cross-sectional shape of the line 29a did not deteriorate. In addition, since no RF bias power is applied, there is no factor other than the diverging magnetic field for accelerating ions toward the wafer, and the underlying interlayer insulating film 26 is sputtered out and reattached to the pattern side wall. There was no.

Thereafter, the wafer was transferred to a plasma ashing apparatus, and O ₂ plasma ashing was performed under ordinary conditions. As a result, as shown in FIG.
At the same time as the resist mask 30 is removed, the side wall protective film 31 is also decomposed or burned, and N ₂ , NO _x , SO _x , S
And so on.

Embodiment 5 This embodiment is similar to the embodiment 4 described above, except that the present invention
The present invention is applied to bit line processing of a RAM, and after an Al-based wiring material layer is etched to a just-etched state using an S ₂ Cl ₂ / N ₂ mixed gas, over-etching is performed using a Cl ₂ / SF ₆ mixed gas. This is an example in which the residue is removed. This process will be described with reference to FIGS.

FIG. 8 is a schematic sectional view showing an example of the configuration of a wafer before etching. That is, an interlayer insulating film 32 made of SiO ₂ is formed on the entire surface of the wafer shown in FIG. 7, and a via hole 32a is opened facing the bit line 29a. The via hole 32a is formed, for example, by a tungsten plug layer 33 grown by selective CVD.
Buried flat. Further, an Al-based wiring material layer 34 having a thickness of about 0.5 μm is formed on the entire surface by sputtering, and a resist mask 3 is formed thereon.
5 are formed.

Here, the Al-based wiring material layer 34 constitutes a final bit line together with the bit line 29a comprising the above-mentioned second-layer polycide film 29, and has a thickness of about The main component is a 0.4 μm Al-1% Si layer. Actually, a TiW barrier metal having a thickness of about 0.1 μm is interposed between the Al-1% Si layer and the interlayer insulating film 32, but in FIG.
The 1-1% Si layer and the TiW barrier metal were integrated and represented as a single-layer Al-based wiring material layer 34.

The resist mask 35 is coated with, for example, a novolak positive photoresist (TSMR-V3, trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.), and is selectively exposed to g-rays. It was formed through the process.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the Al wiring material layer 34 was etched under the following conditions. S ₂ Cl ₂ flow rate 80 SCCM N ₂ flow rate 20 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 100 W (2 MHz) Wafer temperature 25 ° C. Under the above conditions, generated from S ₂ Cl ₂ While the etching of the Al-based wiring material layer 34 progressed with Cl ^* as the main etching species, (SN) _n was deposited on the pattern side wall according to the mechanism described above.

By the above-mentioned mechanism, as shown in FIG.
6, the bit line 34a having an almost vertical wall was formed. But at this time, A
Unnecessary portions of the l-system wiring material layer 34 are not completely removed,
Residue 3 at the bottom of the step or in a dense part of the pattern
4b had occurred. The residue 34b is mainly composed of a TiW barrier metal, but may be Al-1% Si depending on the location.
It also includes some of the layers.

Therefore, in order to remove the residue 34b,
The etching conditions were changed as follows as an example. Cl ₂ flow rate 50 SCCM SF ₆ flow rate 50 SCCM Gas pressure 1.3 Pa (10 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 0 W Here, Cl ^* generated from Cl ₂ converts Al and Ti into chloride. 10 and the F ^* generated from SF ₆ contributes to the removal of W in the form of fluoride.
As shown in the figure, the residue 34b was promptly removed.
At this time, the cross-sectional shape of the bit line 34a did not deteriorate because the sidewall protective film 36 formed in the steps up to the above-described just etching has a strong sidewall protective effect.

Moreover, since no RF bias power was applied, the underlying interlayer insulating film 32 was not sputtered out and re-adhered to the pattern side wall.
This is particularly important in patterning the Al-based material layer. This is because if no re-deposits are formed, the residual chlorine is not occluded therein, and the after-corrosion resistance is greatly improved.

Finally, the wafer was transferred to a plasma ashing apparatus, and O ₂ plasma ashing was performed under ordinary conditions. As a result, as shown in FIG. 11, at the same time as the resist mask 35 was removed, the sidewall protective film 36 was also sublimated, decomposed, or burned off.

Although the present invention has been described based on the five embodiments, the present invention is not limited to these embodiments. For example, free S is generated in plasma under discharge dissociation conditions. As the sulfur-based compound to be obtained, other compounds can be used depending on the type of the material layer to be etched. For example, when the material layer to be etched is a silicon-based compound, in addition to S ₂ F ₂ , SF ₂ ,
SF _4, S ₂ F ₁₀ fluoride such as sulfur, S ₃ Cl _2, S ₂
Sulfur chloride such as Cl ₂ , SCl ₂ , S ₃ Br ₂ , S ₂ B
sulfur bromide such as r ₂ , SBr ₂ , or SOF ₂ , S
OCl ₂ , SOBr ₂ or the like can be used. In the case where the material layer to be etched is an Al-based compound, it can be used as long as a compound containing F as a constituent element is excluded from the above compounds.

On the other hand, as the nitrogen compound, the above-mentioned N ₂
Besides, N ₂ H ₂ , NF ₃ , NCl ₃ , NBr ₃ , NO
₂ etc. can be used. NH ₃ is not preferable because it reacts with the above-mentioned sulfur-based compound to produce ammonium sulfide which is difficult to remove. Although H ₂ S was used in Example 2 as a compound for increasing the apparent S / X ratio of the etching reaction system, H ₂ ,
A silane compound or the like can be used. In particular, when a silane compound is used, H ^* and Si ^* generated under discharge dissociation conditions both contribute to trapping of X ^* (halogen radical), so a large increase in the S / X ratio is expected. it can.

Further, a sputtering effect, a cooling effect,
A rare gas such as He or Ar may be added to the etching gas for the purpose of obtaining a dilution effect.

[0065]

As is clear from the above description, according to the dry etching method of the present invention, sidewall protection can be performed using a sulfur nitride-based compound instead of a conventional carbon-based polymer. Therefore, an effective countermeasure against de-CFC can be provided for the etching of the silicon-based compound layer, and the selectivity to resist and after-corrosion resistance can be improved for the etching of the Al-based material layer. In addition, the sulfur nitride-based compound can be deposited on the wafer under the temperature condition on the wafer mounting electrode of a normal dry etching apparatus, and has a lower contamination property than the carbon-based polymer. Furthermore, since the sulfur nitride-based compound has a very good side wall protection effect, even when performing a large overetching in the radical mode,
High anisotropy and low damage can be maintained.

Therefore, the present invention is designed based on fine design rules, is suitable for manufacturing a semiconductor device having a high degree of integration and high performance, and its industrial value is extremely large.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a process example in which the present invention is applied to processing of a polycrystalline silicon gate electrode in the order of steps, and FIG. 1 (a) shows a state in which a resist mask is formed on a polycrystalline silicon layer. (B) shows a state in which the gate electrode is formed by etching the polycrystalline silicon layer,
(C) shows a state in which the resist mask and the sidewall protective film have been removed, respectively.

FIG. 2 is a schematic cross-sectional view showing a state in which a gate electrode having a tapered shape is formed by excessive deposition of a side wall protective film in another process example in which the present invention is applied to polycrystalline silicon gate electrode processing.

FIGS. 3A and 3B are schematic cross-sectional views showing a process example in which the present invention is applied to polycide gate electrode processing in the order of the steps, wherein FIG. 3A is a state in which a resist mask is formed on a polycide film, and FIG. respectively represent a state where the WSi _x layer is etched, (c) a state where the gate electrode by etching the polycrystalline silicon layer is formed, (d) is a state where the resist mask and side wall protective film is removed.

FIG. 4 is a schematic cross-sectional view showing a state in which a resist mask is formed on a second polycide film in a process example in which the present invention is applied to bit line processing of an SRAM.

FIG. 5 is a schematic cross-sectional view showing a state in which a residue is formed by patterning the second polycide film of FIG. 4;

FIG. 6 is a schematic sectional view showing a state in which the residue of FIG. 5 has been removed.

FIG. 7 is a schematic sectional view showing a state where the resist mask and the side wall protective film of FIG. 6 have been removed.

FIG. 8 is a process example in which the present invention is applied to bit line processing of an SRAM;
FIG. 3 is a schematic sectional view showing a state where a mask is formed.

FIG. 9 is a schematic cross-sectional view showing a state where the wiring material layer of FIG. 8 is patterned and residues are formed.

FIG. 10 is a schematic sectional view showing a state where the residue of FIG. 9 has been removed.

11 is a schematic cross-sectional view showing a state where the resist mask and the side wall protective film of FIG. 10 have been removed.

[Explanation of symbols]

1,11,21 single crystal silicon substrate 2,12 gate oxide film 3,13,23,27 polycrystalline silicon layer 3a gate electrode (by polycrystalline silicon layer) 4, 16,30,35 ... resist mask 5,17,31,36 ... sidewall protective film 14,24,28 ··· WSi _x layer 15a ... (according polycide film) gate electrode 25 ... Word line 26, 32 ... interlayer insulating film 29 ... second layer polycide film 29a ... (by second layer polycide film) Bit line 29b ... (of second layer polycide film)
Residue 34 ... Al-based wiring material layer 34a ... Bit line (by Al-based wiring material layer) 34b ... Residue (of Al-based wiring material layer)

Claims (3)

(57) [Claims] A material to be etched on a substrate using an etching gas containing a nitrogen compound and a sulfur compound capable of generating free sulfur in plasma under discharge dissociation conditions.
A dry etching method, characterized by etching a material layer to be etched on the substrate while depositing a sulfur nitride-based compound on a surface of the layer . 2. The dry etching method according to claim 1,
The material layer to be etched is a substrate having a step on the surface.
And the etching of the material layer to be etched is completed.
The dry etching method which is characterized in that after, a step of the residues of the etched material layer remaining on the bottom of the stepped radical reaction is removed by etching conditions consisting mainly. 3. The dry etching method according to claim 1, wherein the temperature of the substrate is set to 130 ° C. or less.