JP2855898B2 - Dry etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method used in a semiconductor device manufacturing process or the like.

[0002]

2. Description of the Related Art In semiconductor devices such as VLSI, ULSI, etc. with high integration and high performance, silicon-based material layers such as single-crystal silicon, polycrystalline silicon, refractory metal silicide, and polycide, or Al-based materials are used. In the etching of the layer, it is necessary to satisfy high anisotropy, high speed, high selectivity, low contamination and the like.

As an etching process of single crystal silicon, a trench processing method for forming a trench for the purpose of isolating fine elements and securing a cell capacitance area is used.
In this process, anisotropic processing of a high aspect ratio pattern is required. However, the cross-sectional shape of the trench is liable to change in a complicated manner due to a change in a mask pattern or an etching condition, and undercut or bowing (bowin) is actually performed.
Shape abnormalities such as g) often occur. All of these make it difficult to control the filling of the trenches and the capacitance in the subsequent steps.

Polycrystalline silicon, refractory metal silicide,
A gate processing method is used as an etching process for polycide or the like. The pattern width of the gate electrode directly affects the channel length when the source / drain regions of the transistor are formed in a self-aligned manner and the dimensional accuracy of the sidewall in the LDD structure. Therefore, this process also requires extremely high processing accuracy.

Conventionally, etching of these silicon-based materials has been carried out by using CFC 113 (C ₂ Cl ₃ F ₃ ) or the like.
FC gas (a type of so-called chlorofluorocarbon gas) has been widely used as an etching gas. Since CFC gas has F and Cl as constituent elements in one molecule, depending on the conditions, radical reaction by radicals such as F ^* and Cl ^* and C
Etching by both ion-assisted reaction with ions such as F _x ⁺ and CCl _x ⁺ is possible, and high anisotropy can be achieved while protecting the side wall with a carbon-based polymer deposited from the gas phase. .

On the other hand, there has been proposed a technique which does not achieve high anisotropy by the side wall protecting action of the carbon-based polymer as described above but achieves this by lowering the temperature of the substrate to be etched (wafer). . This is a process called low-temperature etching, in which the temperature of the wafer is reduced to zero.
By keeping the temperature below ℃, the radical reaction on the pattern side wall is frozen or suppressed to prevent shape abnormalities such as undercut while maintaining the etching rate in the depth direction at a practical level by the ion assist effect. Technology. For example, in the 35th Federation of Applied Physics-related Lectures (Spring Annual Meeting, 1988), Proceedings, page 495, and Abstract No. 28a-G-2, the wafer was stored at -130 ° C.
Then, an example in which the silicon trench etching and the n ⁺ -type polycrystalline silicon layer were etched using SF ₆ gas was described.

In general, in a dry etching process, unless the wafer is cooled, the temperature of the wafer rises to about 200 ° C. due to plasma radiant heat or reaction heat, so that the temperature of the wafer is controlled to about room temperature in a broad sense. Included in low temperature etching. Although the above description relates to the etching of the silicon-based material layer, high-precision processing is similarly required for the Al-based material layer. Generally, dry etching of an Al-based material layer is performed using a chlorine-based gas typified by a BCl ₃ / Cl ₂ mixed gas. A
Since the reaction between 1 and Cl proceeds spontaneously, etching is performed by extending the mean free path of ions under conditions of low gas pressure and high bias in order to ensure anisotropy. At this time, the decomposition product of the resist mask sputtered by the ions having high incident energy forms a carbon-based polymer, which adheres to the pattern side wall to protect the side wall.

[0008]

The CFC gas used for etching a silicon-based material is such that carbon contained in the CFC gas is silicon oxide (SiO 2).
₂ ) There is a problem that the selectivity to the system material layer is deteriorated. This issue is discussed in the 36th Lecture Meeting on Applied Physics (Spring 1989), Proceedings of the Second Preliminary Volume, 572 pages, Abstract No. 1p-L-7, or Monthly Semiconductor World (published by Press Journal), 1990 It is described in literature such as the January issue, pages 81 to 84. When carbon is adsorbed on the surface of a SiO ₂ -based material layer such as a gate oxide film, a C—O bond (2
57 kcal / mole) is generated to weaken the Si—O bond, or SiO ₂ is reduced to Si and easily extracted by halogen-based etching species.

Further, there is a possibility of particle contamination by the carbon-based polymer. That is, when the design rules of the semiconductor device are further miniaturized, the carbon polymer deposited from the gas phase also becomes a significant source of particle contamination. If the low-temperature etching described above relies only on freezing or suppressing the radical reaction to achieve high anisotropy, a low temperature that requires liquid nitrogen is required as described above. However, this raises hardware problems such as the necessity of a large and special cooling device and the reduction of the reliability of the vacuum sealing material. In addition, it takes a long time to cool the wafer and heat it to return to room temperature, which lowers the throughput, and there is a great possibility that economic efficiency and productivity may be impaired.

Further, in a process in which anisotropy is ensured by a sidewall protective film derived from a mask material, such as an Al-based material layer, depending on the configuration of the mask, sidewall protection is interrupted in the middle and anisotropic processing is performed. In some cases, it becomes impossible. Then, under the miniaturized design rules, the surface step of the wafer further increases. In order to realize a uniform resolution in the photolithography process on the surface of such a wafer, there is a multilayer resist process. For example, in a three-layer resist process, a thick lower resist layer, an intermediate film made of silicon oxide, and a thin upper resist layer are sequentially stacked. Next, the upper resist layer is patterned by exposure and development, using the mask as a mask to pattern the intermediate film by RIE (reactive ion etching), and further etching the lower resist layer using the upper resist layer and the intermediate film as a mask. . Here, during the etching of the thick lower resist layer, the removal of the thin upper resist layer also progresses at the same time, and the intermediate film exposed from the middle functions alone as a mask. However, at this stage, since there is no resist material serving as a supply source of the carbon-based polymer on the vertical incidence surface of the ions, the side wall protective film cannot be formed. Therefore, in the conventional etching gas system, anisotropic etching of the Al-based material layer by the three-layer resist process becomes impossible.

By combining the low-temperature cooling of the wafer with the protection of the side walls, anisotropic processing can be performed even in a higher temperature range than before, and a practical low-temperature etching process can be provided. If an etching gas which can generate a deposition material containing no carbon in plasma under discharge dissociation conditions is selected as the etching gas at this time, the sidewall can be always protected regardless of the configuration of the mask. Note that it is necessary that the deposited substance can be easily removed after the end of the etching.

In order to satisfy such conditions, various kinds of etching gases mainly composed of sulfur halide having a relatively large S / X ratio (ratio of the number of S atoms to the number of X (halogen) atoms in a molecule) are used. For example, it is possible to protect the side wall by depositing free sulfur (S) generated by dissociation in the plasma.

Accordingly, the present invention is based on the technical background as described above, and it is possible to set the wafer temperature within a practical temperature range even if low-temperature etching is performed, and furthermore, it is possible to obtain a carbon-based polymer from a resist material layer. It is an object of the present invention to provide a dry etching method that enables good anisotropic processing even in a system in which generation of GaN is not expected.

[0014]

A dry etching method according to the present invention proposed to achieve the above object is to control the temperature of a substrate to be etched disposed in a plasma etching apparatus to a room temperature or lower. While S ₂ F ₂ ,
SF ₂ , SF ₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , S ₃ Br ₂ ,
Halogen radical used as an etching species for a silicon-based material layer using an etching gas containing at least one kind of sulfur halide selected from S ₂ Br ₂ and SBr ₂
That generate cations and assist in radical reactions
Is performed by generating .

In another dry etching method according to the present invention, at least one type selected from S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F ₁₀ while controlling the temperature of the substrate to be etched to room temperature or lower. Etching containing sulfur fluoride
Etching the silicon-based material layer substantially by the thickness of the layer using a gas, and controlling the temperature of the substrate to be etched to a room temperature or lower while controlling the S ₃ Cl ₂ , S ₂ Cl ₂ , SC
removing the silicon-based material layer remaining in the etching step using an etching gas containing at least one kind of sulfur halide selected from l ₂ , S ₃ Br ₂ , S ₂ Br ₂ and SBr _2. And

Further, another dry etching method according to the present invention is a method for etching a polycide film in which a polycrystalline silicon layer and a refractory metal silicide layer are sequentially laminated on a substrate to be etched, While controlling the temperature of the substrate below room temperature, S ₂ F ₂ , SF
Etching the refractory metal silicide layer using an etching gas containing at least one kind of sulfur fluoride selected from ₂ , SF ₄ , and S ₂ F _10; and keeping the temperature of the substrate to be etched below room temperature. While controlling, S ₃
Cl ₂ , S ₂ Cl ₂ , SCl ₂ , S ₃ Br ₂ , S ₂ Br
And etching the polycrystalline silicon layer using an etching gas containing at least one kind of sulfur halide selected from SBr ₂ and SBr ₂ .

Further, in another dry etching method according to the present invention, while controlling the temperature of the substrate to be etched to room temperature or lower, S ₃ Cl ₂ , S ₂ Cl ₂ , SCl ₂ , S ₃
The aluminum material layer is etched using an etching gas containing at least one kind of sulfur halide selected from Br ₂ , S ₂ Br ₂ , and SBr ₂ .

Among the sulfur halides used in the dry etching method according to the present invention, S ₂ F ₂ , SF ₂ , SF ₄
, S ₂ F ₁₀ is sulfur fluoride and sulfur monofluoride S ₂
F ₂ has a melting point of −133 ° C. and a boiling point of 15 ° C., sulfur difluoride SF ₂ is a gas at room temperature, and sulfur tetrafluoride F ₄ has a melting point of −12.
1 ℃, boiling point -38 ℃, sulfur pentafluoride S ₂ F ₁₀ melting point
52.7 ° C, boiling point 30 ° C.

Also, among the sulfur halides used in the dry etching method according to the present invention, S ₃ Cl ₂ , S ₂
Cl ₂ and SCl ₂ are sulfur chlorides. Trisulfur trichloride S ₃ Cl ₂ has a melting point of −46 ° C. and sulfur monochloride S ₂ Cl _2.
Is melting point -80 ° C, boiling point 137.1 ° C, sulfur dichloride SC
l ₂ has a melting point of −122 ° C. and a boiling point of 59.6 ° C.

Further, among the sulfur halides used in the dry etching method according to the present invention, S ₃ Br ₂ , S
₂ Br ₂ and SBr ₂ are sulfur bromides, and sulfur monobromide S ₂ Br ₂ has a melting point of −46 ° C. and sulfur dibromide S ₃ Br ₂
And sulfur dibromide SBr ₂ are liquid substances at room temperature.

These sulfur halides are gaseous or liquid substances at normal temperature and normal pressure, as is clear from the above physical property data. Even if a liquid is introduced into the etching reaction system by means such as bubbling, it can easily exist in a gaseous state under a high vacuum where dry etching is performed.

[0022]

Various sulfur halides used in the dry etching method according to the present invention generate halogen radicals (F ^* , Cl ^* , Br ^* ) which serve as etching species for the silicon-based material layer under discharge dissociation conditions. At the same time, ions (SF _x ⁺ , SCl _x ⁺ , S
Br _x ⁺ , S _x ⁺ , Cl ⁺ , Br ^+, etc.).

Also, free sulfur (S) can be released into the plasma. This S is deposited on the surface of the wafer whose temperature is controlled to be equal to or lower than room temperature, and is used for side wall protection.

Therefore, by using the above-mentioned sulfur halide, it is possible to balance a high-speed isotropic etching reaction based on a radical reaction with a proper incident ion energy and a proper amount of S deposition, thereby making it possible to use a silicon-based compound. Anisotropic processing of the material layer can be performed.

The use of sulfur fluoride speeds up the etching. This is because the radical radius of F ^* is small, so that it can easily penetrate into the crystal lattice of the silicon-based material layer. Also, when viewed from the interatomic bond energy, the Si—F bond (132 kcal / mol) becomes the Si—Si bond (54 kcal / mol).
kcal / mol).

Further, by using sulfur chloride and sulfur bromide, etching is performed with emphasis on anisotropy and base selectivity. This is because the radical radii of Cl ^* and Br ^* are so large that they cannot easily penetrate into the crystal lattice of the silicon-based material layer, the etching does not proceed without ion bombardment, and the value of the interatomic bond energy is examined. And Si-Cl bond (96 kcal / mol) and Si-B
This is because the value of the r bond (88 kcal / mol) is not so far from the value of the Si—Si bond.

In the dry etching method according to the present invention,
There is no risk of particle contamination. S deposited on the wafer is easily sublimated by heating the wafer to about 90 ° C. after the completion of the etching. Alternatively, the resist mask burned simultaneously with the ashing is also removed in the form of SO _x.

The dry etching method according to the present invention, which includes an etching step and a step of removing the silicon-based material layer remaining in this etching step, can reduce the difference in reactivity between halogen radicals and the silicon-based material layer. By utilizing this, the selectivity with respect to the base is improved while maintaining the high speed, and the anisotropy is prevented from being deteriorated when the silicon-based material layer remaining in the etching step is removed. In other words, in the step until the silicon-based material layer is substantially etched by the thickness of the layer (just etching step), sulfur fluoride is used and high-speed etching by F ^* is performed. This is because in the step of removing the material layer (overetching step), sulfur chloride that generates Cl ^* having lower reactivity than F ^* or sulfur bromide that generates Br ^* is used.

The dry etching method according to the present invention, in which the refractory metal silicide layer is etched using sulfur fluoride and the polycrystalline silicon layer is etched using sulfur chloride or sulfur bromide, is characterized in that the refractory metal is vaporized. In the case of etching the polycrystalline silicon layer, F ^* is eliminated from the etching reaction system when fluoride is rapidly removed in the form of a high-pressure fluoride, so that selectivity to the SiO ₂ -based base material layer is also improved.

In addition, the dry etching method according to the present invention for etching an Al-based material layer using sulfur chloride or sulfur bromide provides a method for producing Cl ^* ,
Br ^* combines with Al to form AlCl _x or AlBr _x
Al is removed in the form of.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. Embodiment 1 In this embodiment, the first invention of the present application is applied to gate electrode processing, and polycrystalline silicon containing an n-type impurity (DOPOS = doped polysilico) using S ₂ F ₂ is used.
n) Example of etching a layer. This process will be described with reference to FIG.

First, as shown in FIG. 1A, a DOPOS layer 3 containing an n-type impurity is formed on a single crystal silicon substrate 1 via a gate oxide film 2 made of SiO _2.
Is formed, and a wafer having a resist mask 4 patterned in a predetermined shape on the DOPOS layer 3 is prepared.

Next, the wafer is set on a wafer mounting electrode of an RF bias applied type magnetic field microwave plasma etching apparatus. A cooling pipe is built in the wafer mounting electrode, and an organic solvent or a chlorofluorocarbon-based refrigerant (Sumitomo 3M, manufactured by Sumitomo 3M, Ltd.)
The wafer can be cooled by supplying and circulating the product (Fluorinert, etc.). Here, ethanol is used as a coolant so that the wafer temperature during etching is maintained at about -70 ° C.

In this state, as an example, the S ₂ F ₂ flow rate 5S
CCM, gas pressure 1.3 Pa (10 mTorr), microwave power 850 W, RF bias power 30 W (2
MHz), the DOPOS layer 3 is etched. In this etching step, the radical reaction by F ^* to produce dissociated from S ₂ F ₂ is likewise SF ⁺ generated from S ₂ F _2, etched with mechanisms assisted ion S _x ⁺ or the like progresses. Further, free S is also released from S ₂ F ₂ into the plasma. This S is deposited on the side wall of the pattern where the normal incidence of ions does not occur on the surface of the wafer cooled at a low temperature, and forms a side wall protective film 5 as shown in FIG. As a result, the gate electrode 3a having a good anisotropic shape is formed without undercut or the like immediately below the resist mask 4.

In this process, the gate oxide film 2
And high selectivity to the same. This is because the low-temperature cooling of the wafer lowers the reactivity of radicals on the wafer surface, and the RF bias power can be reduced by the amount corresponding to the side wall protection. For example, the above RF
The value of the bias power is 20 V or less when converted to the self-bias potential V _dc , and belongs to an extremely low region as incident ion energy. Therefore, it is effective for forming a gate oxide film having a small thickness.

Further, under the above-described low bias condition, the sputter removal of the resist mask 4 is also suppressed, so that the selectivity with respect to the resist is improved and the particle contamination by the carbon-based polymer can be prevented. . Next, after the temperature of the wafer is returned to room temperature, the wafer is moved to a plasma ashing apparatus and ordinary oxygen plasma ashing is performed. As a result, as shown in FIG. 1C, the resist mask 4 is removed by a combustion reaction, and at the same time, the sidewall protective film 5 is also quickly removed. This side wall protective film 5
The mechanism of removal, other forms of the SO _x from combustion reaction,
Sublimation due to heating of the wafer by reaction heat or plasma radiation heat also contributes. Therefore, no particle contamination occurs on the wafer.

In the above-described example, the removal of the side wall protective film 5 is performed simultaneously with the ashing of the resist mask 4, but the heating for returning the wafer after the low-temperature etching to room temperature is extended to about 90 ° C. May be heated, and the side wall protective film 5 may be removed by sublimation before ashing.

[0038] Example 2 This examples are intended to perform a gate electrode processing, S ₂
This is an example in which a DOPOS layer containing an n-type impurity is etched using Cl ₂ . First, the wafer shown in FIG. 1A is set in an RF bias applying type microwave plasma etching apparatus, and as an example, the flow rate of S ₂ Cl _{2 is} 50 SCCM, and the gas pressure is 1.3 Pa (10 mTorr).
r), the DOPOS layer 3 is etched under the conditions of a microwave power of 850 W, an RF bias power of 100 W (2 MHz), and a wafer temperature of −20 ° C.

In this etching step, ions such as SCl ⁺ , S _x ⁺ and Cl ⁺ generated from S ₂ Cl ₂ are converted to DOP.
The etching collides with the surface of the OS layer 3 to activate it, and the etching proceeds in such a manner as to assist the reaction between the already adsorbed Cl and the DOPOS layer 3. At the same time, S is deposited on the side wall of the pattern, and a side wall protective film 5 is formed as shown in FIG. According to this embodiment as well, the gate electrode 3a having a favorable anisotropic shape can be formed.

In this embodiment, the ion-assisted reaction of Cl ^* is used instead of the etching species having high reactivity to the silicon-based material such as F ^*. It is possible to realize anisotropic processing even in a region where the wafer cooling temperature is high. In addition, high selectivity is achieved for the underlying gate oxide film 2, and the anisotropic shape is prevented from deteriorating during over-etching, which is a step of removing the DOPOS layer 3 remaining in the above-described etching step.

Embodiment 3 In this embodiment, a polycide gate electrode is processed, in which a tungsten polycide film is etched using S ₂ F ₂ . This process will be described with reference to FIG.

First, as shown in FIG. 2A, a polycide film 15 is formed on a single crystal silicon substrate 11 via a gate oxide film 12 made of SiO _2, and a resist patterned into a predetermined shape is formed. Prepare a wafer on which the mask 16 is formed. Here, the polycide film 15 is used.
Are DOPOs each having a thickness of 0.1 μm in order from the lower layer side.
S layer 13 and the tungsten silicide (WSi _x) layer 1
4 are laminated. The resist mask 16 is formed, for example, by exposing a chemically amplified negative type three-component resist (trade name: SAL-601, manufactured by Shipley Co., Ltd.) using a KrF excimer laser stepper and performing alkali development. It has a width of 35 μm.

Next, the wafer is set in an RF bias applied type magnetic field microwave plasma etching apparatus. As an example, the flow rate of S ₂ F _{2 is 5} SCCM and the gas pressure is 1.3.
Pa (10 mTorr), microwave power 850 W,
The polycide film 15 is etched under the conditions of an RF bias power of 30 W (2 MHz) and a wafer temperature of −10 ° C.

[0044] In this etching process, WSi _x layer 14
Is removed in the form of WF _x and SiF _x to obtain WSi
_{An x} pattern 14a is formed, and the DOPOS layer 13 is removed in the form of SiF _x to form a DOPOS pattern 13a. At this time, S is deposited on the pattern side wall to form the side wall protective film 17. As a result,
As shown in FIG. 2B, a gate electrode 15a having a good anisotropic shape is formed.

In this embodiment, since S can be deposited from a gas phase by using S ₂ F ₂ , anisotropic processing can be performed. Finally, when the resist mask 16 was removed by ashing, the side wall protective film 1 was removed.
7 was also quickly removed.

[0046] Example 4 This example is an example applied to the trench processing, S ₂
This is for etching a single crystal silicon substrate using Br ₂ . This process will be described with reference to FIG.

First, as shown in FIG. 3A, an SiO ₂ mask 22 is formed on a single-crystal silicon substrate 21.
A wafer having an opening 22a formed by patterning is prepared. The wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus. As an example, the flow rate of S ₂ Br _{2 was} 50 SCCM, and the gas pressure was 1.3 Pa (1).
The single crystal silicon substrate 21 is etched under the conditions of 0 mTorr), microwave power of 850 W, and RF bias power of 200 W (2 MHz).

In this etching step, S generated by dissociation from S ₂ Br ₂ is deposited on the side wall along with a reaction product such as SiBr _x to form a side wall protective film 23, and an abnormal state as shown in FIG. A trench 21a having an isotropic shape is formed. At this time, SB accelerated under high bias conditions
r ^+, S _x ^+, by sputtering action of ions of Br ^+, etc., the edge portion of the SiO ₂ mask 22 is rounded retracted. In the conventional process, ions scattered in the receding portion of the mask obliquely enter the opening 22a and attack the side wall of the trench to cause so-called bowing. According to this, the trench 21a having a substantially vertical wall can be formed by the sidewall protecting action of S.

When the wafer is heated to about 90 ° C. after the etching, the side wall protective film 23 is quickly sublimated and removed as shown in FIG. 3C, and no particle contamination occurs. Embodiment 5 This embodiment shows an example in which the method of the present invention is applied to gate electrode processing. First, the DOPOS layer is just etched using S ₂ F _2, and then, S ₂ Cl ₂ is used.
DOPOS remaining in the just etching process
This is to remove the layer.

First, the wafer shown in FIG. 1A was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the S ₂ F ₂ flow rate was 5S.
CCM, gas pressure 1.3 Pa (10 mTorr), microwave power 850 W, RF bias power 30 W (2
MHz), the DOPOS layer 3 under the condition of a wafer temperature of −70 ° C.
Is etched. As a result, a gate electrode 3a having an anisotropic shape as shown in FIG. 1B is formed.

This etching is performed while monitoring the emission spectrum, and stops when the emission peak intensity derived from SiF _x starts to decrease. Next, as an example of the etching conditions, the flow rate of S ₂ Cl _{2 is 20} SCCM, the gas pressure is 1.3 Pa (10 mTorr), and the microwave power is 85.
Switching to 0 W, RF bias power of 10 W (2 MHz), and a wafer temperature of −70 ° C., the remaining DOPOS layer 3 is removed in the above-described step of etching the DOPOS layer 3. In the etching step for removing the DOPOS layer 3, the selectivity to the underlying gate oxide film 2 is further improved as compared with the first embodiment because F ^* does not exist and the incident ion energy is reduced. Can be done. Also, since S is continuously deposited from the gas phase,
The anisotropic shape of the gate electrode 3a does not deteriorate during over-etching for removing the remaining DOPOS layer 3.

[0052] Example 6 This example, the present invention method are those showing an example of applying the polycide gate electrode processing, with S ₂ F ₂ WS
After the i _x layer is etched, using the S ₂ Cl ₂ DOP
The OS layer is etched. This process will be described with reference to FIG.

First, the wafer shown in FIG. 2A was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the S ₂ F ₂ flow rate was set to 50.
SCCM, gas pressure 1.3Pa (10mTorr), microwave power 850W, RF bias power 100W
Etching the WSi _x layer 14 under the conditions of (2MHz).

In this etching step, the side wall protective film 17
There while being formed etching proceeds, WSi _x pattern 14a having anisotropic shape is formed. Next, S ₂
DOPO under the same conditions except that F ₂ was replaced with S ₂ Cl ₂
The S layer 13 is etched to obtain DO having an anisotropic shape.
The POS pattern 13a is formed. Thus, the gate electrode 15a having a favorable anisotropic shape as a whole is formed.

In addition, when the DOPOS layer 13 is etched, the incident ion
If the energy is reduced, the selectivity to the underlying gate oxide film 12 can be further improved. Incident ion energy can be easily reduced by reducing the RF bias power or increasing the RF frequency.

Embodiment 7 In this embodiment, after an etching mask is formed by a three-layer resist process, Al-1% is formed by using S ₂ Cl _2.
This is an example in which a Si layer is etched. This process will be described with reference to FIG.

First, as shown in FIG. 5A, an Al-1% Si layer 32 is formed on an interlayer insulating film 31, and an etching / resisting layer including a lower resist layer 33 and an SOG intermediate film 34 is further formed thereon. A wafer on which a mask 35 is formed in a predetermined pattern is prepared. Here, the SOG intermediate film 34
Is formed by performing RIE (Reactive Ion Etching) as a mask for an upper resist layer (not shown) formed by photolithography and development. The lower resist layer 33 is formed by etching using the upper resist layer and the SOG intermediate film 34 as a mask. Since the upper resist layer is a thin layer that emphasizes resolution, it is removed at the same time as the thick lower resist layer is being etched. Therefore, the layer finally exposed on the surface of the etching mask in the three-layer resist process becomes the SOG intermediate film 34.

The wafer was set in a magnetic field microwave plasma etching apparatus of RF bias application type, and as an example, the flow rate of S ₂ Cl _{2 was} 80 SCCM, and the gas pressure was 1.3 Pa.
(10mTorr), microwave power 850W, RF
Bias power 50W (2MHz), wafer temperature 0 ° C
Etching of the Al-1% Si layer 32 is performed under the following conditions.

In this etching step, Al-1% Si
Layer 32 is removed in the form of AlCl _x , SiCl _x . In this case, S generated by dissociation from S ₂ Cl ₂ accumulates on the side wall of the pattern, and as shown in FIG.
6 is formed. Therefore, the Al-based wiring layer 32a having a favorable anisotropic shape can be formed.

In this example, since a carbon-based polymer is not used for protecting the side wall, A using chlorine-based gas is not used.
This is effective for suppressing after-corrosion in the etching of the l-type material layer. When the sidewall protective film is formed of a carbon-based polymer, the carbon-based polymer itself contains chlorine as a constituent element, or absorbs a chlorine compound, thereby causing a large amount of chlorine to remain on the pattern sidewall. Such a problem does not occur if the sidewall protection film is formed of S.

It should be noted that the method of the present invention is not limited to the above-described embodiment, and the etching gas used in the method of the present invention may contain He, A rare gas such as Ar may be appropriately added. Further, the configuration of the sample wafer, the etching apparatus, the etching conditions, and the like can be appropriately changed.

[0062]

As described above, the method of the present invention can realize anisotropic processing in a much higher temperature range than conventional low-temperature etching, so that the method is excellent in economy and productivity. Furthermore, without depending on the decomposition products of the resist mask and the etching reaction products, etc.
Anisotropic processing can be performed irrespective of the configuration of the etching mask, since it is formed by deposits from the gas phase.

Therefore, according to the method of the present invention, a semiconductor device which is designed based on a fine design rule and has a high degree of integration and high performance can be reliably manufactured.

[Brief description of the drawings]

FIG. 1 shows the first invention and the second invention of the present application as DOPOS.
FIGS. 3A and 3B are schematic cross-sectional views showing a process example applied to gate electrode processing in the order of steps, wherein FIG. 3A is a state in which a resist mask is formed on a DOPOS layer, and FIG.
(C) shows a state in which the POS layer has been anisotropically etched, and (c) shows a state in which the resist mask and the sidewall protective film have been removed.

FIGS. 2A and 2B are schematic cross-sectional views showing a process example in which the method of the present invention is applied to polycide gate electrode processing in the order of the steps, wherein FIG. 2A is a state in which a resist mask is formed on a polycide film, and FIG. Shows a state in which the polycide film has been anisotropically etched, and (c) shows a state in which the resist mask and the side wall protective film have been removed.

FIG. 3 is a schematic cross-sectional view showing an example of a process in which the method of the present invention is applied to trench processing in the order of steps;
(A) is a state where a SiO ₂ mask is formed on a single crystal silicon substrate, (b) is a state where a trench is formed,
(C) shows a state in which the sidewall protective film has been removed.

[4] The present invention method is a schematic sectional view showing in accordance with the order of steps a process example of applying the polycide gate electrode processing, (a) shows the state in which WSi _x layer is anisotropically etched, (b) is The state where the DOPOS layer is anisotropically etched is shown.

FIG. 5 shows the method A of the present invention using a three-layer resist process.
1 is a schematic cross-sectional view showing an example of a process applied to l-wiring processing in the order of steps, (a) showing a state in which an etching mask composed of a lower resist layer and an SOG intermediate film is formed on an Al-1% Si layer; , (B) shows Al-1% Si
The state where the layer was anisotropically etched is shown.

[Explanation of symbols]

1,11,21 single crystal silicon substrate, 2,12 gate oxide film, 3,13 DOPOS layer, 3a, 15a
Gate electrode, 4,16 Resist mask, 5,1
7,23,36 sidewall protective film (S), 14 WSi _x
Layer, 15 polycide film, 22 SiO ₂ mask,
21a trench, 31 interlayer insulating film, 32 Al
-1% Si layer, 32a Al-based wiring layer, 33 lower resist layer, 34 SOG intermediate film, 35 etching mask

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-217917 (JP, A) JP-A-2-309631 (JP, A) JP-A-61-256725 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H01L 21/3065 JOIS

Claims (4)

(57) [Claims] 1. The method according to claim 1, wherein the temperature of the substrate to be etched disposed in the plasma etching apparatus is controlled to a room temperature or less.
₂ F ₂ , SF ₂ , SF ₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , S ₂ C
etching of _{l 2, SCl 2, S 3} Br 2, S 2 Br 2, SBr at least one silicon-based material layer by using an etching gas containing a sulfur halide selected from ₂
Generates halogen radicals,
A dry etching method characterized in that etching is performed by generating ions that assist a Cull reaction . 2. While the temperature of the etched substrate was controlled to below room temperature, using at least one etching gas containing sulfur fluoride selected from _{S 2 F 2, SF 2,} SF 4, S 2 F 10 Etching the silicon-based material layer by a thickness substantially equal to the thickness of the silicon-based material layer.
₃ Cl ₂ , S ₂ Cl ₂ , SCl ₂ , S ₃ Br ₂ , S ₂ Br ₂ , S
Removing the silicon-based material layer remaining in the etching step using an etching gas containing at least one kind of sulfur halide selected from Br ₂ . 3. A dry etching method for etching a polycide film in which a polycrystalline silicon layer and a refractory metal silicide layer are sequentially stacked on a substrate to be etched, wherein the temperature of the substrate to be etched is controlled to room temperature or lower. Etching the refractory metal silicide layer using an etching gas containing at least one kind of sulfur fluoride selected from S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F _10; Of S ₃ Cl ₂ , S ₂ Cl ₂ , SCl ₂ , S ₃ Br ₂ , S ₂ Br while controlling the temperature of
Etching the polycrystalline silicon layer using an etching gas containing at least one kind of sulfur halide selected from SBr ₂ and SBr ₂ . 4. A method for controlling the temperature of a substrate to be etched to be equal to or lower than room temperature while controlling S ₃ Cl ₂ , S ₂ Cl ₂ , SCl ₂ and S ₃ B.
A dry etching method characterized by etching an aluminum-based material layer using an etching gas containing at least one kind of sulfur halide selected from r ₂ , S ₂ Br ₂ , and SBr ₂ .