JPH05136104A - Dry etching method - Google Patents

Abstract

PURPOSE:To prevent the sputtering off and re-adhesion of a base material layer while a lower resist later is etched in a three-layer resist process. CONSTITUTION:In the process of producing the etching mask of the second polycide film 9 of SRAM, a lower resist layer 10 is etched with a mixed gas of S2Cl2, N2, and O2 while the wafer temperature is maintained at -30 deg.C. Besides the burning of the resist material by O2, polythiazyl (SN)x is produced by the reaction between the S and N2 supplied from the S2Cl2 and it forms a side wall protective film 13 together with resulted products of reaction, such as CClx, etc. Because of the strong side wall protecting effect of the film 13, the incident ion energy required for anisotropic working can be reduced and the sputtering off and re-adhesion of a base WSix layer 8 can be prevented. The (SN)x can be easily resolved or sublimated when the wafer is heated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied to the manufacture of semiconductor devices and the like. The present invention relates to a method of performing anisotropic processing while preventing re-deposition of a sputtered product derived from a layer on a pattern side wall portion.

[0002]

2. Description of the Related Art As semiconductor device design rules are highly miniaturized from sub-micron level to quarter-micron level, demands for various processing techniques are becoming more severe. Photolithography technology is no exception. In recent years, the exposure wavelength has been shortened in order to obtain high resolution, and the surface steps of the substrate have also increased. Therefore, the adoption of a multilayer resist process is becoming essential. The multi-layer resist process is a method of using a combination of at least two resist layers, a lower resist layer thick enough to absorb surface steps of a substrate and an upper resist layer thin enough to achieve high resolution. ..

As a well-known method, a lower resist layer, an extremely thin intermediate layer made of a silicon oxide (SiO _x ) material such as SOG (spin on glass), etc. on a substrate, and patterning directly by photolithography. Using three types of thin top resist layers,
There is a so-called three-layer resist process. In this process, first, the upper resist layer is patterned into a predetermined shape, the intermediate layer thereunder is patterned by RIE (reactive ion etching), and the upper resist layer and the intermediate layer are used as masks. O ₂
The lower resist layer is patterned by dry etching using gas or the like. Since the upper resist layer is thinner than the lower resist layer, it is consumed during the etching of the lower resist layer, and the intermediate layer finally constitutes the upper surface of the etching mask.

By the way, in the step of patterning the lower resist layer which is an organic material layer with O ₂ gas,
In order to prevent the pattern shape deterioration due to the isotropic combustion reaction due to O ^* (oxygen radical), it is necessary to adopt a condition in which the ion incident energy is increased to some extent. That is, the mean free path of ions and the self-bias potential V _dc under the conditions of low gas pressure and high bias power.
, And high anisotropy is achieved based on the etching mechanism in which the sputter reaction by ions having high kinetic energy is the main.

However, the adoption of such etching conditions is also a main cause of impeding the practical application of the multilayer resist process. This problem will be described with reference to FIG. FIG. 3 shows the state of the wafer at the stage when an etching mask for patterning the second-layer polycide film is formed in the bit line processing of SRAM by the three-layer resist process.

The steps up to this point will be briefly described. First, on the silicon substrate 21 in which the shallow trench type element isolation region 22 is formed, the gate electrode made of the first polycide film is formed via the gate oxide film made of SiO _2. 5 was formed, and then a second layer polycide film 29 was formed via the SiO ₂ interlayer insulating film 26. Here, the first-layer polycide film is the polycrystalline silicon layer 23 and the WSi _x layer 24, and the second-layer polycide film 29 is the polycrystalline silicon layer 27.
And the WSi _x layer 28 are sequentially laminated.
Subsequently, the entire surface of the wafer was flattened with the lower resist layer 30, and then a thin upper resist layer (not shown) was formed via the SOG intermediate layer 31. Next, the upper resist layer is patterned by photolithography and development processing, and RIE (reactive ion etching) is performed using the obtained pattern as a mask to form a pattern of the SOG intermediate layer 31, and further, both patterns are formed. The lower resist layer 30 was etched using the as a mask. Here, since the pattern of the thin upper resist layer disappears during the etching of the lower resist layer 30, finally, as shown in FIG.
An etching mask having the SOG intermediate layer 31 is formed on the lower resist layer 30.

Here, the lower resist layer 30 is a layer formed to have a film thickness sufficient to absorb the step difference on the surface of the wafer based on the purpose of the multi-layer resist process. There is a big difference, and the time required for etching is naturally different. For example, in the region B where the thickness of the lower resist layer 30 is thin, the lower resist layer 3
The WSi _x layer 28 is exposed earlier than in the region A having a thick film thickness of 0, and is removed by sputter by being irradiated with ions having large incident energy. Part of the sputtered product is redeposited on the pattern side wall of the lower resist layer 30,
The reattachment layer 28a is formed. The redeposited layer 28a is difficult to remove and becomes a source of particle contamination, and it also causes a substantial line width of the etching mask to become thick and causes a dimensional conversion difference.

The problem of reattachment as described above is described in, for example, Proceedings of the 33rd Joint Lecture of Applied Physics (Spring Annual Meeting 1986) p. 542, Abstract No. 2p-Q-8 has been pointed out and is well known. Reattachment layer 28
Although it is clear that the reduction of incident ion energy is effective in suppressing the formation of helium, this causes the above-mentioned isotropic combustion reaction to predominate, resulting in a decrease in anisotropy.

Therefore, a dry etching method for a resist material layer, which can achieve both reduction of incident ion energy and achievement of high anisotropy, has been earnestly desired.

As a technique to meet such demands, (a) a process using N ₂ gas, (b) an ultra-low pressure process using ECR plasma, (c) a low temperature etching process, etc. have been proposed so far. However, it is difficult to put them into practical use immediately. The process using N ₂ gas in the above (a) can be performed, for example, by Proceedingsof
5th Dry Process Symposiu
m (1983), p. 41, it is intended to achieve high anisotropy even under the condition that the ion incident energy is lowered by using N which is an etching species that is not likely to cause radical reaction with an organic substance. However, this low reactivity inevitably results in a decrease in etching rate.

The ultra-low pressure process using the ECR plasma of the above (b) is described in the 35th Joint Lecture on Applied Physics (1)
1988 Spring Annual Meeting) Proceedings p. 502, abstract number 2
8a-G-12, 10 ^-4 to 10 ^-5 To.
The radical generation amount is reduced under an ultra-low pressure of rr level, and etching using substantially only ions is enabled. However, considering the ionization rate, it is still difficult to secure a practically sufficient etching rate. Also, 5
There are major hardware restrictions such as the large displacement turbo molecular pump of the 000 liter / sec class is indispensable, and the device that enables accurate pressure control in the low pressure range is not currently available. ..

The low temperature etching process (c) above is described in the proceedings of the 35th Joint Lecture of Applied Physics (Spring Annual Meeting 1988) p. 494, Abstract No. 28a-G-
4, it is intended to freeze or suppress the radical reaction by cooling the substrate to be processed at a low temperature. This method is considered to be the best in principle, but low temperature cooling down to -100 ° C or higher is necessary to secure high anisotropy, and the reliability and temperature There are still many hardware problems such as controllability.

In view of the above problems, the present inventor achieved the achievement of high anisotropy not only by reducing the radical property and enhancing the ionic property but also by using side wall protection by the reaction product. We are proposing various technologies to try. That is,
By using side wall protection together, the ion incident energy can be reduced to the extent that the practical etching rate is not impaired, and even if low temperature etching is performed, the same effect is achieved in a temperature range much closer to room temperature than before. Is obtained.

For example, in JP-A-2-244625, a reaction product of a lower resist layer and a Cl-based gas is obtained by using an etching gas in which chlorine (Cl) -based gas is added to O _2. A technique for anisotropically etching the lower resist layer while depositing CCl _x as a sidewall protective film has been disclosed. Further, Japanese Patent Application No. 2-198044 proposes a technique of etching a resist material layer using an etching gas mainly composed of NH ₃ in a state where the wafer temperature is controlled at 50 ° C. or lower. .. Here, the etching reaction product containing at least N, C, and O as constituent elements plays a role of a sidewall protective film.

Further, in Japanese Patent Application No. 2-298167, a reaction product of a lower resist layer and a Br-based gas is obtained by using an etching gas in which bromine (Br) -based gas is added to O ₂ . A technique of anisotropically etching the lower resist layer while depositing CBr _x as a side wall protective film was proposed.

[0016]

The respective dry etching methods previously proposed by the present inventor achieve anisotropic etching with low-energy ions in a practical temperature range while ensuring a practical etching rate. In that respect, they were all extremely innovative technologies. However, in the present situation where the surface step difference of the substrate in the semiconductor device is increasing more and more, over-etching up to 100% may be required, and spatter removal of the base material layer and reattachment accompanying it may occur. Layer formation is becoming a more serious problem than ever before.

As a countermeasure against this problem, it has been proposed to add a compound capable of etching the underlying material layer to the etching gas. For example, the technique previously disclosed by the present inventor in Japanese Patent Application Laid-Open No. 2-244718 is an example thereof, and an etching gas is used during overetching when etching a multilayer resist film using an aluminum (Al) -based material layer as a base. Is added with BCl ₃ . As a result, even if a redeposited layer made of an Al-based material is formed on the side wall of the pattern, the lower resist layer can be over-etched while removing it with BCl ₃ .

However, considering the recent device structure in which the film thickness has been remarkably advanced, even a slight removal of the base material layer has a high possibility of degrading the reliability of the device. If the underlying material layer is exposed to the high V _dc condition with a slight delay in the timing of switching the etching conditions during overetching, the fear of redeposition cannot be eliminated. Therefore, it is an object of the present invention to provide a dry etching method capable of suppressing reattachment of sputter products derived from a base material layer to a higher degree and truly enhancing the practicality of a multilayer resist process.

[0019]

The present invention is proposed to achieve the above object. That is, the dry etching method according to the first aspect of the present invention, the organic material layer formed on a _{substrate, S 2 F 2, SF 2} , SF 4 while the temperature of the substrate was controlled to below room temperature, S ₂ F ₁₀ , S ₃
Cl ₂ , S ₂ Cl ₂ , SCl ₂ , S ₃ Br ₂ , S ₂ Br
Etching is performed using an etching gas containing at least one sulfur halide selected from ₂ , SBr ₂ , a nitrogen compound and O ₂ .

In the dry etching method according to the second invention of the present application, the organic material layer formed on the substrate is controlled to S ₂ F ₂ , SF ₂ , SF while controlling the temperature of the substrate at room temperature or below.
₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , S ₂ Cl ₂ , SCl ₂ , S
Etching is performed substantially by the layer thickness thereof using a first etching gas containing at least one sulfur halide selected from ₃ Br ₂ , S ₂ Br ₂ and SBr ₂ , a nitrogen compound and O _2. Process and the first etching
Over-etching using a second etching gas obtained by adding H ₂ S to the gas.

[0021]

In order to make the conventional measures easier to implement and more effective, the present inventor has no fundamental solution other than more thorough prevention of redeposition from the underlying material layer. We have reached the view that it is indispensable to further reduce the etching condition to V _dc . However, in order to perform anisotropic processing under the condition where the incident ion energy is lowered in this way, it becomes necessary to deposit a stronger sidewall protective material on the pattern sidewall portion than ever before. Moreover, this side wall protective material must be one that can be easily removed after the etching is completed in order to prevent particle contamination.

As the side wall protective material, the present inventor has focused on sulfur nitride compounds. Although various compounds are known as the sulfur nitride-based compound as described below, a typical compound expected to have a side wall protecting effect in the present invention is polythiazyl (SN) _x . (SN)
_For the properties and structure of _x , see J. Am. Chem. S
oc. , Vol. 29, p. 6358-6363 (19
75). It is a polymeric substance that stably exists at 208 ° C. under normal pressure and around 140 to 150 ° C. under reduced pressure, and in the crystalline state, the main chain composed of repeated covalent bonds of S—N—S—N —... ing. Therefore, the sulfur nitride based compound layer mainly composed of (SN) _x can effectively prevent the intrusion of F ^{* and the} like.
Further, even if ions accelerated by the conditions are incident, a so-called sponge effect is exerted due to a change in the bond angle or the conformation, and the ion impact can be absorbed or alleviated. Moreover, (SN) _x is 140 under reduced pressure.
When heated up to about 150 ° C, it is easily decomposed or sublimated and can be completely removed.

The above (SN) _x can be generated in plasma by dissociating a gas mixture containing a nitrogen compound and a sulfur compound capable of releasing free S (sulfur) under discharge dissociation conditions. it can. In the first invention of the present application,
That is why an etching gas containing sulfur halides, nitrogen compounds and O ₂ is used. here,
Of course, O _{2 in} the composition of the etching gas is a component that contributes to the combustion reaction of the organic material layer.

The above-mentioned sulfur halide is a compound serving as a source of free S under discharge dissociation conditions. This property is
SF, which is also well known as an etching gas in the field of dry etching, has been used in the field of dry etching.
It is quite different from ₆ not releasing free S into the plasma. Of course, the halogen atom supplied from this sulfur halide also contributes to the reaction with the organic material layer to form a reaction product having a low vapor pressure, as in the prior art.

Further, the nitrogen-based compound supplies a low-reactivity etching species for the organic material layer and also serves as a supply source of N for producing a sulfur nitride-based compound.

When the organic material layer is etched using the etching gas having the above composition, a sulfur nitride compound is produced in parallel with the combustion reaction of the organic material layer. That is, in the simplest way, N generated in plasma by discharge dissociation of a nitrogen-based compound and S generated in plasma by discharge dissociation of a sulfur-based compound are bonded to each other, and first, thiazyl (N≡S) is formed. It is formed. This thiazyl has an unpaired electron by analogy with the structure of an oxygen analog, nitric oxide (NO), and is easily polymerized (SN) ₂ ,
(SN) ₄ and further (SN) _x are generated. (SN)
₂ easily polymerizes at around 20 ° C. (SN) ₄ and (S
N) _x is generated and decomposes at around 30 ° C. (S
N) ₄ is a cyclic substance having a melting point of 178 ° C. and a decomposition temperature of 206 ° C.

In addition to the above, halogen such as F ^{* is} contained in the plasma.
When a radical is present, S in (SN) _x above
A thiazyl halide having a halogen atom attached on the atom may also be produced. Further, when hydrogen-based gas is added to control the amount of F ^* produced, thiazyl hydrogen can also be produced. Furthermore, depending on the conditions, S ₄ N ₂ (melting point 23
℃), S ₁₁ N ₂ (melting point 150 to 155 ℃), S ₁₅ N
₂ (melting point 137 ° C.), S ₁₆ N ₂ (melting point 122 ° C.), etc., a cyclic sulfur nitride compound in which the number of S atoms and N atoms in the molecule is imbalanced, or N of these cyclic sulfur nitride compounds
S ₇ NH (Helting point 113.5
℃), 1,3-S ₆ (NH) ₂ (melting point 130 ℃), 1,
4-S ₆ (NH) ₂ (melting point 133 ° C.), 1,5-S
₆ (NH) ₂ (melting point 155 ° C.), 1,3,5-S ₅ (N
H) ₃ (melting point 124 ° C.), 1,3,6-S ₅ (NH) ₃
An imide type compound such as (melting point 131 ° C.) and S ₄ (NH) ₄ (melting point 145 ° C.) can also be produced.

These sulfur nitride compounds are deposited on the side wall surface of the pattern in which vertical incidence of ions does not theoretically occur on the surface of the wafer whose temperature is controlled to room temperature or lower, and exert a strong side wall protecting effect. On the other hand, in the present invention, a compound having a low vapor pressure such as CF _x polymer or CCl _x or CBr _x is produced by the reaction between the halogen contained in the sulfur halide and the organic material layer. It exhibits a side wall protection effect together with the compounds.

Therefore, according to the present invention, the incident ion energy required for anisotropic processing can be reduced, and the removal of the underlying material layer by sputtering and the formation of a redeposited layer accompanying it can be prevented. .. Moreover, any of the above sulfur nitride compounds can be easily removed by decomposition or sublimation by heating the wafer after the etching is completed, and does not cause any particle contamination. Other deposits can be removed at the time of resist ashing, but there is no risk of contamination because the deposition amount is relatively reduced by the amount expected to deposit the sulfur nitride-based compound.

[0030]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 In this example, the first invention of the present application is applied to the bit line processing of SRAM by a three-layer resist process, and S ₂ Cl ₂ is applied.
In this example, the lower resist layer on the second-layer polycide film was etched using a mixed gas of / N ₂ / O ₂ . This process will be described with reference to FIG.

FIG. 1A is a schematic sectional view showing one structural example of a wafer before etching. That is, the gate electrode 5 made of the first polycide film is formed on the silicon substrate 1 in which the shallow trench type element isolation region 2 is formed in advance, with the gate oxide film made of SiO ₂ interposed therebetween.
The gate electrode 5 is formed by stacking a lower polycrystalline silicon layer 3 and an upper WSi _x (tungsten silicide) layer 4. Further, the entire surface of the wafer is covered with an SiO ₂ interlayer insulating film 6 formed by depositing SiO ₂ by CVD, for example, and a second-layer polycide film 9 is formed thereon. This 2
The layer polycide film 9 is formed by laminating the lower polycrystalline silicon layer 7 and the upper WSi _x layer 8.
This is a part that constitutes the bit line of the SRAM.

Further, in order to pattern the second-layer polycide film 9, first, a lower resist layer 10 is formed to a thickness capable of substantially absorbing and flattening the surface steps of the wafer, and an SOG intermediate layer pattern 11 is formed thereon. , The upper resist pattern 12 is sequentially formed. The lower resist layer 10 is, for example, a novolac-based positive photoresist (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name OFPR-80).
0). At this time, a region A having a large layer thickness and a region B having a small layer thickness are generated depending on the arrangement of the gate electrode 5, but the average layer thickness in the former case is set to about 1.0 μm.

The SOG intermediate layer pattern 11 is, for example, SOG (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name OCD-Type).
e2) is used to form a coating film having a thickness of about 0.15 μm, and then RIE (reactive ion etching) is performed using the upper layer resist pattern 12 described later as a mask. The etching conditions at this time are, for example, a CHF ₃ flow rate of 75 using a hex type RIE apparatus.
SCCM, O ₂ flow rate 8 SCCM, gas pressure 6.5 Pa, R
The F power was 1350 W (13.56 MHz).

The upper resist pattern 12 is, for example, a chemically amplified negative type three-component resist (manufactured by Shipley Co .; trade name SAL-601) and has a thickness of about 0.5 μm.
After forming the coating film of No. 3, it is patterned using a KrF excimer laser stepper.

Next, in order to etch the lower resist layer 10, the above-mentioned wafer was set on the wafer-mounted electrode of the RF bias application type magnetic field microwave plasma etching apparatus. Here, the wafer mounting electrode has a built-in cooling pipe, and the wafer being etched can be cooled to a predetermined temperature by supplying and circulating an appropriate cooling medium from a cooling device such as a chiller installed outside the apparatus. It is done like this. Here, an ethanol refrigerant was used. An example of etching conditions is shown below.

S ₂ Cl ₂ flow rate 10 SCCM N ₂ flow rate 10 SCCM O ₂ flow rate 30 SCCM Gas pressure 0.67 Pa (5 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 30 W (2 MHz) Wafer temperature -30 ° C.

In this etching process, the combustion reaction of the upper layer resist pattern 12 and the lower layer resist layer 10 due to O ₂ progresses, and as shown in FIG. 1B, the lower layer resist pattern having a good anisotropic shape is formed. The pattern 10a was formed. The upper resist pattern 12 disappears during the etching of the thick lower resist layer 10. The reason why the high anisotropy is achieved even under the low bias condition is that the sidewall protection is efficiently performed. That is, S ₂ Cl
By reaction with S and N ₂ generated from _2, sulfur nitride based compound mainly composed of (SN) _x is generated in the plasma,
Deposition is carried out on the side wall of the pattern in which vertical incidence of ions does not occur in principle on the surface of the wafer maintained at -30 ° C. This sulfur nitride compound is used as a resist material and S ₂ C.
sidewall protection with CCl _x is the reaction product of l ₂ layer 13
To protect the side wall of the pattern from O ^* attack.

Further, since it is possible to lower the bias of the etching conditions in this way, it is possible to prevent the underlying WSi _x layer 8 from being sputtered off and redeposited during overetching. This is especially true for the lower resist layer 10
Was extremely effective from the viewpoint of improving the selectivity to the WSi _x layer 8 in the region B having a small film thickness.

After the etching is completed, the above-mentioned wafer is about 150
When heated to 0 ° C., as shown in FIG. 1C, the side wall protective film 13 was promptly decomposed or sublimated, and was removed without causing any particle contamination. The etching mask thus formed has no risk of causing a dimensional conversion difference even when the second-layer polycide film 9 is etched.

Embodiment 2 In this embodiment, the second invention of the present application is applied to the bit line processing of SRAM by the three-layer resist process, and S ₂ Br ₂ is applied.
/ N ₂ / O ₂ mixed gas is used to etch the lower resist layer on the second polycide film by almost the thickness of the layer (just etching), and then H ₂ S is added to the mixed gas to perform overetching. Here is an example. This process will be described with reference to FIG. 2 in addition to FIG.

The wafer used as the etching sample in this example is the same as that shown in FIG. This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the lower resist layer 10 was etched to a just etching state under the following conditions. The just-etched state here means a state in which the surface of the WSi _x layer 8 starts to be exposed in the region B where the film thickness of the lower resist layer 10 is thin, as shown in FIG. 2.

S ₂ Br ₂ flow rate 20 SCCM N ₂ flow rate 10 SCCM O ₂ flow rate 20 SCCM Gas pressure 0.67 Pa (5 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 20 W (13.56 MHz) Wafer temperature 20 ° C.

In this etching process, the sulfur nitride compound mainly composed of (SN) _x is produced by the reaction between S and N ₂ supplied from S ₂ Br ₂ . Further, CBr _x , which is a reaction product of the resist material and S ₂ Br ₂ , is also generated,
This formed the side wall protection film 13 together with the above (SN) _x . As a result, as shown in FIG. 2, the lower-layer resist pattern 10a having a good anisotropic shape was completed in the region B and partially formed in the region A. Here, it is possible to perform anisotropic processing with a lower bias than in Example 1 and at a high wafer temperature, because the sidewall protective film 1 is formed.
This is because the vapor pressure of CBr _x , which is a constituent component of No. 3, is lower than that of CCl _x , and deposition can be performed efficiently.

Next, over-etching for removing the remaining portion of the lower resist layer 10 was performed under the following conditions as an example. S ₂ Br ₂ flow rate 20 SCCM N ₂ flow rate 10 SCCM O ₂ flow rate 20 SCCM H ₂ S flow rate 10 SCCM Gas pressure 0.67 Pa (5 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 10 W (13.56 MHz) Wafer temperature 20 ° C.

In this overetching process, the etching gas composition in the just etching process is changed to H.
By adding ₂ S, the supply of S to the etching reaction system is increased, and excess radicals are trapped by H ^* . Also, compared to the just etching process, R
The F bias power is also reduced. That is, (S
This is a condition for promoting the deposition of N) _x , which strengthens the sidewall protection effect, and more effectively suppresses sputter removal of the underlying WSi _x layer 9 in the region B in particular.

Although the present invention has been described above based on two embodiments, the present invention is not limited to these embodiments. For example, the above-mentioned S ₂ Cl ₂ , S ₂ Br as sulfur halide can be used. Similar effects can be obtained by using the compounds specified in the present invention other than ₂ . However, when a sulfur fluoride-based compound is used, although the sidewall protection by CF _x polymer can be expected in addition to (SN) _x , the underlying material layer is a polycrystalline silicon layer, a refractory metal silicide layer, or the like. Therefore, there is a possibility that the background selectivity may be slightly reduced, so that attention should be paid to the optimization of the conditions.

Further, as the nitrogen-based compound, the above-mentioned N ₂
Besides, it is possible to use NF ₃ or the like, but it is necessary to optimize the conditions in order to prevent deterioration of the underlayer selectivity due to F ^* . NH ₃ is likely to consume S for the production of ammonium sulfide, and is not suitable for the purpose of the present invention. In addition, the configuration of the wafer, etching conditions, equipment used, composition of etching gas, etc. can be changed as appropriate.

[0049]

As is clear from the above description, in the present invention, efficient sidewall protection is provided to effectively prevent spatter removal and redeposition of a base material layer when etching a thick organic material layer. can do. Therefore, a resist pattern having an anisotropic shape can be formed under clean conditions without causing a dimensional conversion difference, and the practicality of the multilayer resist process can be truly enhanced.

The present invention is extremely effective in manufacturing a semiconductor device which is designed based on a fine design rule and has a high degree of integration and high performance.

[Brief description of drawings]

FIG. 1 is an SRA of the present invention with a three-layer resist process.
FIG. 4 is a schematic cross-sectional view showing an example of a process applied to the bit line processing of M in the order of the steps, (a) shows a state where an intermediate layer pattern is formed by using an upper layer resist pattern as a mask, and (b) shows a side wall protective film. The state where the lower layer resist pattern is formed while being formed, and (c) shows the state where the side wall protective film is removed.

FIG. 2 is an SRA of the present invention with a three-layer resist process.
In another process example applied to M bit line processing,
It is a schematic sectional drawing which shows the state in which the lower layer resist pattern was formed in the middle by just etching.

[Explanation of symbols]

6 ... SiO ₂ interlayer insulating film 7 ... Polycrystalline silicon layer (of second polycide film) 8 ... WSi _x layer (of second polycide film) 9 ... Second polycide film 10・ ・ ・ Lower resist layer 10a ・ ・ ・ Lower resist pattern 11 ・ ・ ・ SOG intermediate layer pattern 12 ・ ・ ・ Upper resist pattern 13 ・ ・ ・ Sidewall protection film

[Procedure amendment]

[Submission date] October 21, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is an SRA of the present invention with a three-layer resist process.
FIG. 6A is a schematic diagram showing an example of a process applied to the bit line processing of M according to the order of steps, and FIG.
The intermediate layer pattern is formed using the pattern as a mask, (b) shows the state where the lower layer resist pattern is formed while the side wall protective film is formed, and (c) shows the state where the side wall protective film is removed.

FIG. 2 is an SRA of the present invention with a three-layer resist process.
In another process example applied to M bit line processing,
It is a schematic sectional drawing which shows the state in which the lower layer resist pattern was formed in the middle by just etching.

FIG. 3 SRAM by a conventional three-layer resist process
FIG. 6 is a schematic cross-sectional view showing a state in which a redeposited layer derived from the underlying WSi _X layer is formed in a region where the lower resist layer is thin in the bit line processing of FIG.

[Explanation of reference numerals] 6 SiO ₂ interlayer insulating film 7 Polycrystalline silicon layer (of second layer polycide film) 8 WSi _X layer (of second layer polycide film) 9 Second layer polycide film 10 Lower resist layer 10a Lower resist Pattern 11 SOG intermediate layer pattern 12 Upper layer resist pattern 13 Side wall protective film

Claims (2)

[Claims] 1. An organic material layer formed on a substrate is formed of S ₂ F ₂ , SF ₂ , while controlling the temperature of the substrate below room temperature.
SF ₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , S ₂ Cl ₂ , SC
dry etching characterized by etching using an etching gas containing at least one kind of halogenated sulfur selected from l ₂ , S ₃ Br ₂ , S ₂ Br ₂ and SBr ₂ , a nitrogen compound and O _2. Method. 2. An organic material layer formed on a substrate is formed of S ₂ F ₂ , SF ₂ , while controlling the temperature of the substrate below room temperature.
SF ₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , S ₂ Cl ₂ , SC
_{l 2, S 3 Br 2,} S substantially its thickness by using _{the 2} Br _2, at least one of the first etching gas containing a sulfur halide and nitrogen-based compound and O ₂ are selected from SBr ₂ A dry etching method comprising: a step of etching by an amount corresponding to the above; and a step of performing over-etching using a second etching gas obtained by adding H ₂ S to the first etching gas.