JP3120569B2 - Dry etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of semiconductor device manufacturing and the like, and more particularly to a method of etching a silicon-based material layer with high anisotropy, high selectivity, low contamination and low damage. About the method.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated and higher in performance as seen in recent VLSI, ULSI, etc., etching of silicon-based material layers such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc. Also, there is a strong demand for a technique for achieving various requirements of high anisotropy, high selectivity, low contamination, and low damage without sacrificing any of them.

There are two typical fields for etching a silicon-based material layer: trench processing and gate electrode processing. Trench processing is a process for forming a trench for the purpose of isolating fine elements and securing a memory cell capacity area. The depth of the trench varies depending on the type and application of the device, and is 4 to 5 μm (deep trench) for a capacitor, 1 μm (shallow trench) for a MOS-FET for element isolation, and 4 μm for a bipolar transistor.
m. Each of the trenches has an opening diameter of 0.
The thickness is about 35 to 1 μm, and anisotropic processing of a high aspect ratio pattern is required.

In the trench processing, a chlorine-based gas is generally used. This is because Cl ^* has a larger atomic radius than F ^* , so there is little risk of spontaneously penetrating into the crystal lattice of Si and deteriorating the anisotropic shape. This is because high selectivity with respect to the system etching mask can be maintained. However, in practice, the cross-sectional shape of the trench is liable to change in a complicated manner due to a change in a mask pattern or etching conditions, and a shape abnormality such as undercut or bowing is often experienced. All of these make it difficult to control the filling of the trenches and the capacitance in the subsequent steps.

Therefore, in order to prevent the above-described deterioration of the cross-sectional shape of the trench, an etching gas capable of generating a deposition material under discharge dissociation conditions is used, and the sidewall protection is performed by using the deposition gas. Several methods have been proposed in the past. For example, the applicant of the present application has disclosed
The SiCl ₄ / N ₂ mixed gas disclosed in Japanese Patent No. 73526 is a typical example. This, together to generate a Cl ^* and Cl ⁺ from SiCl ₄ as a main etching species, Si _x N in the gas phase by reaction with SiCl ₄ and N _2
y, to produce a Si _x N _y Cl _z and the like, a method of depositing these perform sidewall protection. According to this technique, particle contamination can be reduced far more than when a carbon-based polymer is used as a side wall protective material, and etching can be performed under clean conditions.

Further, the applicant of the present application has disclosed a technique disclosed in Japanese Patent Application Laid-Open No. 64-599.
Japanese Patent Publication No. 17 also discloses a technique for performing silicon trench etching using a Cl ₂ / N ₂ mixed gas. This technique is also utilized Si _x N _y, the Si _x N _y Cl _z such as a sidewall protection substance, it is an etching reaction product SiCl _x and N ₂ is produced by reacting. Therefore, it is possible to further reduce particle contamination as compared with a case where a deposition material is generated in a gas phase by a reaction between components of an etching gas as in the above-described process using a SiCl ₄ / N ₂ mixed gas. It becomes possible.

On the other hand, a typical etching process for polycrystalline silicon is gate processing. The pattern width of the gate electrode directly affects the channel length when the source / drain regions of the MOS-FET are formed in a self-aligned manner and the dimensional accuracy of the sidewall in the LDD structure. Therefore, this process also requires extremely high processing accuracy.

[0008] Conventionally, CFC11 has been used for gate electrode processing.
CFC (chlorofluorocarbon) gas typified by 3 (C ₂ Cl ₃ F ₃ ) has been widely used as an etching gas. Since the CFC gas has F and Cl as constituent elements in one molecule, the balance between the radical reaction due to the contribution of F ^* and Cl ^* and the ion assist reaction due to the contribution of CCl _x ⁺ and Cl ⁺ depending on the conditions. It is possible to advance the etching while controlling. Also, high anisotropy can be achieved while protecting the side wall with a carbon-based polymer deposited from the gas phase.

However, it is well known that CFC gas contributes to the depletion of the earth's ozone layer, and its production and use will be banned in the near future. Therefore, even in the field of dry etching, C
There is an urgent need to find an alternative to FC gas and establish an effective way to use it. Further, if the design rule of the semiconductor device is further miniaturized in the future, it is considered that a carbon-based polymer deposited from the gas phase may be a source of particle contamination. In this sense, measures to eliminate CFC are desired.

As one of the technologies considered promising as one of the countermeasures against CFC removal, there is a process using a Br-based chemical species as a main etching species. For example, Digest o
fPapers 1989 2nd MicroPro
cess Conference, p. 190 has H
It has been reported that gate electrode processing of n ⁺ -type polycrystalline silicon using Br is performed. Br has a large ionic radius and does not enter the crystal lattice or crystal grain boundaries of the silicon-based material layer. Therefore, there is little possibility that the silicon-based material layer is spontaneously and isotropically etched like F ^*.
Anisotropic etching can be advanced by the assist mechanism. When the interatomic bond energies were compared, the Si—O bond (1077 kJ / mol)
As is clear from the fact that it is much larger than the r-bond (368 kJ / mol), high selectivity can be achieved for the gate oxide film made of SiO ₂ . In addition, since the surface of the resist mask can be coated with CBr _x having a low vapor pressure, the selectivity of the resist can be improved.

On the other hand, there has been proposed a technique which does not achieve high anisotropy by the side wall protecting action of the carbon-based polymer as described above but achieves this by lowering the temperature of the substrate to be etched (wafer). . This is a process called low-temperature etching, in which the temperature of the wafer is reduced to zero.
By keeping the temperature below ℃, the radical reaction on the pattern side wall is frozen or suppressed to prevent shape abnormalities such as undercut while maintaining the etching rate in the depth direction at a practical level by the ion assist effect. Technology. For example, in the 35th Federation of Applied Physics-related Lectures (Spring Annual Meeting, 1988), Proceedings of the Lecture, page 495, Abstract No. 28a-G-2, the wafer was cooled to -130 ° C and SF ₆ gas was used. Examples of performing a silicon trench etching and an etching of an n ⁺ -type polycrystalline silicon layer have been reported.

[0012]

However, as design rules for semiconductor devices continue to advance at a rapid pace, it becomes necessary to reduce particle contamination at a higher level than ever before. From this viewpoint, in trench processing, S
i _x N _y, the aforementioned processes utilizing Si _x N _y Cl _z and the like to the side wall protection current requirements are met but have yet to avoid the fundamental particle contamination. In addition, trench processing generally requires a long process time and a large amount of deposited material. Therefore, even if such a material is used for protecting a sidewall, it is premised that the material can be easily and completely removed after completion of etching.

[0013] Even in a process using HBr for gate electrode processing, it is difficult to avoid particle contamination due to SiBr _x or the like.

On the other hand, low-temperature etching removes CFCs.
It is expected to be one of the effective means of countermeasures, but if the only way to achieve high anisotropy is to freeze or suppress the reaction of radicals, low-temperature cooling, which requires liquid nitrogen, is required as described above . However, this raises hardware problems such as the necessity of a large and special cooling device and the reduction of the reliability of the vacuum sealing material. Also,
Since it takes time to cool the wafer and heat it to room temperature, there is a concern that the throughput may be reduced, and there is a great possibility that the economy and productivity may be impaired.

Accordingly, the present invention provides a silicon-based material layer which satisfies at a high level various properties which are difficult to achieve at the same time, such as high anisotropy, high selectivity, low contamination, and low damage, and which can be implemented in a practical temperature range. It is an object of the present invention to provide a dry etching method.

[0016]

The dry etching method of the present invention is proposed to achieve the above-mentioned object, and uses at least an etching gas containing an etching gas containing carbonyl sulfide and a halogen compound. The method is characterized in that the silicon-based material layer is etched while depositing the carbon-based polymer and sulfur on the side wall surface of the pattern.

The present invention also provides an etching method comprising adding a carbonyl sulfide to a gas composition capable of generating a halogenated chemical species and free sulfur in a plasma under discharge dissociation conditions.
The method is characterized in that a silicon-based material layer is etched while depositing a carbon-based polymer and sulfur on at least the side wall surface of the etching pattern using a gas.

According to the present invention, a silicon-based material layer is substantially formed while depositing a carbon-based polymer and sulfur on at least the side wall surface of an etching pattern using an etching gas containing carbonyl sulfide and a halogen-based compound. Using a just etching step of etching by the thickness of the layer and an etching gas obtained by adding carbonyl sulfide to a gas composition capable of generating halogenated species and free sulfur in plasma under discharge dissociation conditions, An overetching step of etching a remaining portion of the silicon-based material layer while depositing a carbon-based polymer and sulfur on at least a side wall surface of the etching pattern.

The present invention further provides the above-mentioned silicon material layer,
It is characterized by being composed of at least one selected from single crystal silicon, polycrystalline silicon, and amorphous silicon.

[0020]

The present inventor has come to believe that it is extremely effective to enhance the film quality of the carbon-based polymer constituting the sidewall protective film and improve the etching resistance in order to achieve the above-mentioned object. Was. This is because the following merits can be expected in reinforcing the carbon-based polymer.

First, since the side wall protection effect is improved, the incident ion energy required for anisotropic processing can be reduced. As a result, the sputter removal of the etching mask and the gate oxide film can be suppressed, the selectivity to these is improved, and the damage is reduced. Secondly,
Since the amount of carbon-based polymer deposited necessary to achieve high anisotropy and high selectivity can be reduced, particle contamination can be reduced as compared with the prior art. Further, since the extraction of O atoms from SiO ₂ by C atoms constituting the carbon-based polymer is also suppressed, the selectivity to the gate oxide film at the time of processing the gate electrode is improved.

Third, since the F-type chemical species and the Cl-type chemical species having high reactivity with Si can be used for etching by improving the side wall protection effect, high anisotropy and high selectivity can be achieved. The etching rate is remarkably increased as compared with the case where only the Br-based chemical species is used.

In the present invention, a mixed system containing carbonyl sulfide (COS) and a halogen compound is used as an etching gas capable of strengthening the carbon-based polymer. Here, the halogen-based compound is added to supply the main etching species of the silicon-based material layer. On the other hand, COS has a linear molecular structure of O = C = S, and the carbonyl group in the molecule has a high polymerization promoting activity, thereby increasing the degree of polymerization of the carbon-based polymer, and increasing the incidence of ions and radicals. Increase resistance to attacks. Further, when the above-mentioned functional group or a fragment derived therefrom is introduced into the carbon-based polymer, simply -CX
Recent studies have also revealed that the chemical and physical stability is higher than that of a conventional carbon-based polymer having a _2- (X represents a halogen atom) repeating structure.
This is because when comparing the bond energy between two atoms, C-
The O bond (1077 kJ / mol) is replaced by the CC bond (607).
It is intuitively understood from the fact that it is much larger than (kJ / mol). In addition, the introduction of the functional group as described above increases the polarity of the carbon-based polymer, and increases the electrostatic attraction force of the negatively charged wafer during etching, thereby increasing the etching resistance of the carbon-based polymer. And the surface protection effect is improved.

Further, COS can release S (sulfur) under discharge dissociation conditions. This S is deposited on the surface of the wafer if the temperature is controlled to approximately room temperature or lower, depending on conditions, and contributes to the protection of the side wall or the surface. In addition, if the wafer is heated to about 90 ° C. or higher, it easily sublimates, and S itself does not become a source of particle contamination.

As described above, the film quality of the carbon-based polymer itself is enhanced, and the deposition of S can be expected.
Energy can be reduced, selectivity to a resist mask and a base material layer can be improved, and damage can be reduced. In addition, the amount of carbon-based polymer deposited can be relatively reduced, and particle contamination can also be reduced.

The present invention is based on the above concept, but also proposes a method for further reducing pollution and damage. The method is to enhance the S deposition by the presence of a compound capable of releasing S in addition to COS. In this case, S may be supplied from the same compound as the supply source of the halogen-based chemical species, or may be supplied from another compound. In any case, since the deposition of S is enhanced as compared with the case where S is supplied only from COS,
Incident ion energy can be further reduced, and high selection, low contamination, and low damage can be thoroughly achieved. In addition, the amount of carbon-based polymer deposited can be relatively reduced, and particle contamination can be more effectively reduced.

As described above, if a mixed system that contains COS in the presence of a halogen-based species or can further enhance the deposition of S is used, basically one of the silicon-based material layers is used.
Step etching becomes possible, and a sufficient effect can be obtained with respect to trench processing in which it is not necessary to consider base selectivity. The present invention further proposes a method for improving high-speed, low-contamination, and base selectivity in gate electrode processing in which base selectivity needs to be considered.
This is a two-step etching in which the gas composition is switched between just etching and over etching.

First, in the just etching step of etching the silicon-based material layer substantially by the thickness thereof,
An etching gas containing carbonyl sulfide and a halogen compound is used. At this stage, the reinforced carbon-based polymer and S are deposited. Next, in the over-etching step of etching the remaining portion of the silicon-based material layer, an etching gas obtained by adding carbonyl sulfide to a gas system capable of generating halogen-based chemical species and free S is used. At this stage, the carbon-based polymer is of course deposited, but the deposition of S is enhanced. Thereby, even if the incident ion energy is reduced in order to reduce the damage during over-etching, a favorable anisotropic shape of the etching pattern of the silicon-based material layer is maintained due to the enhanced side wall protection effect. .

In each of the above-mentioned etchings,
The carbon-based polymer and S deposited on the side wall surface of the pattern can be removed by ashing. This ashing can be performed also by removing the resist mask if it is a process using a resist mask. If the process uses an inorganic etching mask such as deep trench processing, it is performed in another step. In any case, the amount of the carbon-based polymer deposited is much smaller than that of the conventional process, so that the removal is easy.
On the other hand, sulfur is easily sublimated by plasma radiation heat or reaction heat at the time of ashing, and is also burned by O ₂ , so that there is no fear of causing particle contamination.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Embodiment 1 In this embodiment, the present invention is applied to a shallow trench process, and a single crystal silicon substrate is etched using a COS / SF ₆ mixed gas. This process will be described with reference to FIG. First, as shown in FIG. 1A, a pad oxide film 2 and a polycrystalline silicon layer 3 are sequentially laminated on a single crystal silicon substrate 1, and a resist mask 4 patterned into a predetermined shape is formed. A sample wafer was prepared. Here, the polycrystalline silicon layer 3
Is formed to a thickness of about 0.15 μm by CVD, for example, and is provided as a buffer layer for preventing the retreat of the edge of the resist mask 4 during etching from being reflected on the deterioration of the trench shape. The pad oxide film 2 is formed to a thickness of 0.01 μm by, for example, thermal oxidation of the single crystal silicon substrate 1, and is used as a stopper layer when the polycrystalline silicon layer 3 is etched back after trench processing is completed. It is provided as. Further, the resist mask 4 is formed to a layer thickness of 0.7 μm using a negative type three-component type chemically amplified negative type photoresist material (manufactured by Shipley; trade name: SAL-601). A first opening 5 having an opening diameter of 0.35 μm and a second opening 6 having an opening diameter of 1 μm are formed by laser lithography and alkali development.

Next, the wafer was set on a wafer mounting electrode of an RF bias applying type magnetic field microwave plasma etching apparatus. The wafer mounting electrode has a built-in cooling pipe, and the wafer can be cooled to a desired temperature by receiving a supply of an appropriate coolant from a cooling facility such as a chiller installed outside the apparatus. Here, etching was performed under the following conditions as an example, using ethanol as a refrigerant.

COS flow rate 10 SCCM SF ₆ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 30 W (2 MHz) Wafer temperature −30 ° C.

In this step, F ₆ dissociated from SF ₆
^{* And} other radical reactions are C ⁺ , CO ⁺ , COS ⁺ ,
Etching proceeded by a mechanism assisted by the incident energy of ions such as S ⁺ and SF _x ⁺ . At the same time, CF _x derived from the decomposition product of the resist mask 6
Was generated, and a carbonyl group, a C—O bond, and the like were incorporated into the structure to form a strong carbon-based polymer.
This carbon-based polymer is deposited on the pattern side wall and
The side wall protective film 7 as shown in (b) was formed, and although the amount of deposition was small, it exhibited high etching resistance and contributed to anisotropic processing. This sidewall protective film 7 also contains free S generated by dissociation from COS. Moreover, in this embodiment, the radical reaction on the pattern side wall surface is suppressed by the effect of wafer cooling. As a result, the conventional CFC
Although the RF bias power is reduced by about 70% as compared with the process using gas, the shallow trenches 1a and 1b having a favorable anisotropic shape are formed, and the resist selectivity is about the same as the conventional one. Improved by a factor of two.

If only the anisotropic etching of the single crystal silicon substrate 1 is intended, even if the etching gas of this embodiment can generate Cl ^* or Br ^* as a halogen-based chemical species. Should be good. However, in the shallow trench processing, the polycrystalline silicon layer 3 and the pad oxide film 2 are usually etched by a gas system having a common composition. Therefore, in order to remove the pad oxide film 2 without generating a residue, SF _{6 is used.} Is added to generate F ^* that can etch the SiO ₂ -based material. This F ^* naturally contributes to speeding up the shallow trench processing. This is extremely effective in preventing the loading effect.

In general, in the shallow trench processing, the area to be etched is 50% or more of the wafer area, and the area must be etched by one digit larger than that in the deep trench processing of 5% or less. No. When the area to be etched is increased in this manner, the etching rate is inevitably reduced due to the loading effect, and in some cases, the rate of decrease may reach nearly 50%. Therefore, in order to realize a practical process, it is essential to increase the etching rate. Therefore, a process in which F ^* can be used in combination and in which anisotropy and resist selectivity do not decrease as in this embodiment is extremely practical.

Finally, the wafer was transferred to a plasma ashing apparatus, and the resist mask 4 was burned off under ordinary O ₂ plasma ashing conditions. At this time, as shown in FIG. 1C, the sidewall protective film 7 was also promptly removed. The sidewall protective film 7 is composed of the carbon-based polymer and S reinforced as described above. However, since the amount of the carbon-based polymer deposited is much smaller than that of the conventional process, the particle level is not deteriorated at all. I never did.

Embodiment 2 This embodiment is also an example of shallow trench processing, but using a COS / S ₂ F ₂ mixed gas as an etching gas, enhancing the deposition of S (sulfur) and selecting a resist. It is intended to further improve the properties and reduce pollution. The wafer used as the etching sample in this embodiment is the same as that shown in FIG. This wafer was etched under the following conditions as an example.

COS flow rate 10 SCCM S ₂ F ₂ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo)
rr) Microwave power 850 W (2.45 GHz)
z) RF bias power 20W (2MHz) Wafer temperature -30 ° C

The above S ₂ F ₂ is, of course, a source of F ^* , but plays an important role of releasing S under discharge dissociation conditions. That is, in this embodiment, S generated from both COS and S ₂ F ₂ can participate in the formation of the sidewall protective film 7 in addition to CF _x reinforced by a carbonyl group or a CO bond. Due to these effects, favorable anisotropic processing could be performed despite the condition that the incident ion energy was lower than in Example 1. In addition, the amount of carbon-based polymer deposited could be further reduced by an amount corresponding to the increased amount of S deposited, so that particle contamination was significantly reduced.

When O ₂ plasma ashing was performed after the completion of the etching, the resist mask 4 and the side wall protective film 7 were promptly removed as shown in FIG.

Embodiment 3 This embodiment is an example in which the present invention is applied to deep trench processing, and a single crystal silicon substrate is etched using COS / Cl ₂ . This process will be described with reference to FIG. First, as an example, as shown in FIG. 2A, a sample wafer in which an etching mask including a SiO ₂ pattern 12 and a sidewall 13 was formed on a single crystal silicon substrate 11 was prepared. Here, the SiO ₂ pattern 12 is a novolak-based positive photoresist material (Tokyo Ohka Kogyo Co., Ltd.) obtained by patterning a 0.2 μm thick SiO ₂ deposited film formed by CVD or the like by g-line exposure and alkali development. Made; trade name TS
The opening having a diameter of 0.5 μm is formed by etching through a mask made of MR-V3). After removing the resist mask, the sidewalls 13 are formed on the entire surface of the wafer by TEOS as an example.
An SiO ₂ deposited film is formed by CVD using (tetraethoxysilane) as a source gas and the SiO ₂ deposited film is subjected to RIE.
And formed by etching back. Thus, the diameter of the opening 14 formed in the etching mask is reduced to 0.2 μm, exceeding the resolution limit of photolithography.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the single crystal silicon substrate 11 was etched under the following conditions. COS flow rate 10 SCCM Cl ₂ flow rate 10 SCCM Gas pressure 0.27 Pa (= 2 mTorr)
r) Microwave power 850 W (2.45 GHz) RF bias power 50 W (2 MHz) Wafer temperature -30 ° C

In this etching process, a radical reaction due to Cl ^* generated from Cl ₂ causes C ⁺ , CO _x ⁺ , C
The single crystal silicon substrate 11 was etched by a mechanism assisted by the incident energy of ions such as OS ⁺ , S ⁺ , and Cl _x ⁺ . At this time, carbonyl groups and C—O bonds are incorporated into the discharge dissociation product of COS to form a strong carbon-based polymer, which deposits on the pattern side wall surface, as shown in FIG. 2 (b). Thus, the side wall protective film 15 was formed. That is, the COS also plays a role of supplying a fragment serving as a raw material of the carbon-based polymer in the gas phase in a system in which the carbon-based polymer is not supplied from the etching mask as in this embodiment. In addition, COS can also release S, which contributes to the formation of the sidewall protective film 15. The RF bias power is the same as the conventional, for example, Cl ₂ /
This is almost halved as compared with the etching using the N ₂ mixed gas system, whereby the selectivity with respect to SiO ₂ can be improved about twice as much as the conventional one. Further, a device has been devised in which the mean free path of ions is extended by greatly lowering the gas pressure to increase the vertical incidence component on the wafer surface. Due to these effects, a deep trench 11a having an anisotropic shape was formed.

After the completion of the etching, the wafer was subjected to O ₂ plasma ashing. As a result, the side wall protective film 15 was quickly removed as shown in FIG. I never did.

Embodiment 4 This embodiment is also an example of deep trench processing, but a COS / Cl ₂ / H ₂ S mixed gas is used as an etching gas. First, the wafer shown in FIG. 2A was set in a magnetic field microwave plasma etching apparatus, and as an example, etching was performed under the following conditions.

COS flow rate 10 SCCM Cl ₂ flow rate 10 SCCM H ₂ S flow rate 5 SCCM Gas pressure 0.27 Pa (= 2 mTorr)
r) Microwave power 850 W (2.45 GHz) RF bias power 50 W (2 MHz) Wafer temperature −30 ° C. In this embodiment, Cl _{2 is} used as a Cl ^* supply source, and S
H ₂ S is separately added as a source of
The mechanism for forming the side wall protective film 15 as shown in FIG. 3B is almost as described above in the third embodiment. Also in this example, the deep trench 11a having a favorable anisotropic shape was formed.

Embodiment 5 In this embodiment, the present invention is applied to gate electrode processing, and COS
This is an example in which a polycrystalline silicon layer is just etched using a / HBr mixed gas, and then over-etched using a COS / S ₂ Br ₂ mixed gas. This process will be described with reference to FIG.

The wafer used as the etching sample in the present embodiment is, as shown in FIG.
An n-type polycrystalline silicon layer 2 of about 0.3 μm thickness doped with n-type impurities via a gate oxide film 22 of about 0.01 μm thickness made of SiO ₂ on a single crystal silicon substrate 21
3 is formed thereon, and a resist mask 24 having a thickness of about 1 μm is further formed thereon in a predetermined pattern.

This wafer was subjected to a magnetic field microwave plasma
The n-type polycrystalline silicon layer 23 was etched under the following conditions as an example. COS flow rate 10 SCCM HBr flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850 W (2.45 GHz)
z) RF bias power 30 W (2 MHz) Wafer temperature −30 ° C. In this etching process, Br generated by dissociation from HBr
Etching proceeds with ^* as the main etching species. At this time, CBr reinforced by a carbonyl group, a CO bond, etc.
_{Since the x-} based polymer and S supplied from the COS were deposited to form the sidewall protective film 25, the gate electrode 23a having an excellent anisotropic shape was formed. However, since the surface of the resist mask 24 is also coated with a CBr _x polymer having a low vapor pressure, the selectivity to the resist mask 24 is high.

This etching is completed when the surface of the gate oxide film 22 is exposed, but the remaining portion 23b of the n-type polycrystalline silicon layer 23 remains partially in the region to be etched.

Therefore, the etching conditions were changed as follows, for example, and over-etching was performed to remove the remaining portion 23b. COS flow rate 10 SCCM S ₂ Br ₂ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850 W (2.45 GHz)
z) RF bias power 15 W (2 MHz) Wafer temperature −30 ° C. At this stage, the total amount of S deposited increases due to S dissociated and generated from S ₂ Br _2, so that it is much lower than in the just etching process. Biasing is now possible.
As a result, the residual portion 23b could be completely removed as shown in FIG. 3C, while maintaining extremely high selectivity with respect to the gate oxide film 22.

Finally, the wafer after the etching is transferred to an ashing apparatus and subjected to O ₂ plasma ashing. As shown in FIG. 3D, the resist mask 24 and the side wall protective film 25 become clean. Removed.

As described above, the present invention has been described based on the five embodiments, but the present invention is not limited to these embodiments. For example, as the halogen compound used in combination with COS, NF ₃ , HCl, ClF _{3 and the} like can be used in addition to SF ₆ , HBr, and Cl ₂ described above. Compounds capable of releasing free S into plasma under discharge dissociation conditions include the above-mentioned H ₂ S, S ₂ F ₂ , and S ₂ Br.
₂ , other sulfur fluoride such as SF ₂ , SF ₄ , S ₂ F ₁₀ , sulfur chloride such as S ₂ Cl ₂ , S ₃ Cl ₂ , SCl ₂ , and other sulfur fluoride such as S ₃ Br ₂ , SBr ₂ Sulfur bromide or the like can be used. In particular, sulfur fluoride, sulfur chloride,
When sulfur bromide is used, these compounds themselves can also serve as the source of the halogen-based species.

The combination of the above compounds is optional, but when performing shallow trench processing, F ^* can be supplied under discharge dissociation conditions in order to enable rapid removal of the pad oxide film. It is desirable to use a gas system. A rare gas such as He or Ar may be added to the etching gas for the purpose of obtaining a sputtering effect, a cooling effect, and a dilution effect.

The silicon-based material layer to be etched may be made of amorphous silicon in addition to the above-described single crystal silicon and polycrystalline silicon. Further, it goes without saying that the etching apparatus, the etching conditions, the configuration of the wafer, and the like to be used can be appropriately changed.

[0057]

As is apparent from the above description, in the present invention, when etching a silicon-based material layer, an etching gas containing carbonyl sulfide and a halogen-based compound is used to deposit S and carbon. High anisotropy and high selectivity can be achieved even when the film quality of the base polymer is enhanced and the relative deposition amount of the carbon base polymer is reduced. Moreover, these can be achieved in a practical wafer temperature range. Further, if the etching gas further contains a sulfur-based compound capable of releasing S under discharge dissociation conditions, the deposition of S is enhanced, and higher selectivity, lower contamination, and lower damage are achieved. be able to.

The present invention is designed on the basis of fine design rules, and is extremely suitable for manufacturing a semiconductor device which requires high integration, high performance, and high reliability. Particularly in the gate electrode processing, a promising countermeasure against CFC can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to shallow trench processing in the order of steps, and FIG. 1 (a) shows a single crystal silicon substrate with a pad oxide film and a polycrystalline silicon layer interposed therebetween. (B) shows a state in which a shallow trench is formed while a sidewall protective film is formed, and (c) shows a state in which the resist mask and the sidewall protective film are removed by ashing. .

FIG. 2 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to deep trench processing in the order of steps, and FIG. ₂ (a) shows a state in which an etching mask made of SiO ₂ is formed on a single crystal silicon substrate. (B) shows a state in which a deep trench is formed while a sidewall protective film is being formed, and (c) shows a state in which the sidewall protective film is removed by ashing.

FIG. 3 is a schematic cross-sectional view showing a process example in which the present invention is applied to gate electrode processing in the order of steps;
(A) shows a state in which a resist mask is formed on the n-type polycrystalline silicon layer, (b) shows a state in which the n-type polycrystalline silicon layer is just etched, and (c) shows a state in which the n-type polycrystalline silicon layer is over-etched. (D) shows a state in which the resist mask and the sidewall protective film have been removed by ashing, respectively.

[Explanation of symbols]

1,11,21 single crystal silicon substrate 1a, 1b shallow trench 2 pad oxide film 3 polycrystalline silicon layer 4,24 resist mask 7,15,25 ... sidewall protective film 11a ... deep trench 12 ... SiO ₂ pattern 13 ... side wall 22 ... gate oxide film 23 ... n-type polycrystalline silicon layer 23a ... gate electrode

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-61-256638 (JP, A) JP-A-53-146939 (JP, A) JP-A-3-72087 (JP, A) JP-A-4- 84427 (JP, A) JP-A-2-162730 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 C23F 4/00 H01L 21/28

Claims (4)

(57) [Claims] An etching gas containing a carbonyl sulfide and a halogen-based compound is used for etching at least.
A dry etching method characterized by etching a silicon-based material layer while depositing a carbon-based polymer and sulfur on a side wall surface of a pattern. 2. An etching gas obtained by adding carbonyl sulfide to a gas composition capable of generating halogenated species and free sulfur in plasma under discharge dissociation conditions,
A dry etching method characterized by etching a silicon-based material layer while depositing a carbon-based polymer and sulfur on at least a side wall surface of an etching pattern. 3. Using an etching gas containing carbonyl sulfide and a halogen compound, at least etching
A just etching process in which a silicon-based material layer is etched substantially by the thickness of the silicon-based material layer while depositing a carbon-based polymer and sulfur on the side wall surface of the pattern, and liberation of halogen-based species into the plasma under discharge dissociation conditions Using an etching gas obtained by adding carbonyl sulfide to a gas composition capable of producing sulfur and the remaining portion of the silicon-based material layer while depositing a carbon-based polymer and sulfur on at least the side wall surface of the etching pattern And an over-etching step of etching the substrate. 4. The method according to claim 1, wherein the silicon material layer is a single crystal silicon.
, Polycrystalline silicon, amorphous silicon
4. The method according to claim 1, wherein the material is at least one kind.
The dry etching method according to claim 1.