JP3008543B2 - Dry etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices, and more particularly to a method of etching a silicon-based material layer without using a chlorofluorocarbon-based gas. The method of improving the performance.

[0002]

2. Description of the Related Art As high integration and high performance of semiconductor devices have progressed as seen in recent VLSIs and ULSIs, high anisotropy, high speed, and high etching are also required for etching silicon-based material layers. There is a strong demand for a technology that achieves various requirements such as selectivity, low damage, and low pollution without sacrificing any of them.

Conventionally, a Freon-based gas such as Freon 113 (C ₂ Cl ₃ F ₃ ) has been widely used as an etching gas for etching silicon-based materials. Since the fluorocarbon-based gas has F and Cl as constituent elements in one molecule, it can be etched by both radical reaction and ion-assisted reaction, and while protecting the side wall with a carbon-based polymer deposited from a gas phase. Anisotropic processing can be realized. However, it has been pointed out that Freon-based gas is the cause of the ozone depletion of the earth as is well known, and production and use will be prohibited in the near future. Therefore, in the field of dry etching, it is urgently necessary to find a substitute for a CFC-based gas and to establish an effective method of using the same. Further, if the design rule of the semiconductor device is further refined in the future, it is considered that a carbon-based polymer deposited from the gas phase may be a source of particle contamination, and from this point of view, measures to remove CFCs are desired.

A promising technique for removing CFCs is low-temperature etching. This is because by keeping the temperature of the substrate to be etched (wafer) at 0 ° C. or lower, the radical reaction on the pattern side wall is frozen or suppressed while the etching rate in the depth direction is maintained at a practical level by the ion assist effect. This is a technique for preventing shape abnormalities such as undercut. For example, 35
Proceedings of the Annual Meeting of the Japan Society of Applied Physics (Spring Annual Meeting, 1988), 495 pages, Abstract No. 28a-G-2,
It is reported that a wafer is cooled to −130 ° C. and a silicon trench etching and an n ⁺ -type polycrystalline silicon layer are etched using SF ₆ gas.

However, if an attempt is made to achieve high anisotropy in low-temperature etching only by freezing or suppressing the radical reaction, an appropriate level of low-temperature cooling is required, and there is a possibility that economic efficiency and throughput may be significantly reduced. Therefore, as a more practical approach, it is conceivable to combine the suppression of the radical reaction at a low temperature with the protection of the side wall and perform the etching in a temperature region closer to room temperature.

The applicant of the present invention has proposed a number of techniques for protecting the side wall by depositing sulfur (S). This S deposition is carried out by etching mainly using sulfur halide having a relatively small ratio of the number of halogen (X) atoms to the number of S atoms in one molecule, that is, the X / S ratio.
This is made possible by using gas. For example, Japanese Patent Application No. 2-198045 discloses S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F ₁₀ as such sulfur halides. These sulfur fluorides can generate S in the gas phase by discharge dissociation, unlike SF _6, which is also best known in the art. This S accumulates on the surface of the substrate when the substrate is cooled at a low temperature, and exhibits a sidewall protection effect. Moreover, the deposited S
Since the substrate can be easily removed by sublimation by heating the substrate after the etching, there is no possibility of causing particle contamination. The applicant of the present application has noticed that the amount of F ^* (fluorine radical) generated from these sulfur fluorides is smaller than that of SF ₆ and that an ion assist reaction by SF _x ⁺ can be expected. Applied to layer etching to achieve high selectivity to silicon underlayer.

As described above, the compound originally proposed as the sulfur halide is sulfur fluoride having a relatively small F / S ratio, which is intended for etching a silicon oxide-based material layer. The present applicant has subsequently proposed various techniques for applying sulfur halide to etching of a silicon-based material layer. For example, Japanese Patent Application No. 2-199249
In the specification, a technique of low-temperature etching a silicon-based material using a gas containing sulfur chloride such as S ₂ Cl ₂ or sulfur bromide such as S ₂ Br ₂ while a substrate to be etched is cooled to 0 ° C. or less. Is disclosed. This is because by using a gas that cannot generate highly reactive F ^* ,
It is intended to reduce the influence of radicals and more advantageously achieve high anisotropy.

[0008]

Among various processes for etching a silicon-based material layer, gate electrode processing for etching polycrystalline silicon, refractory metal silicide, polycide, or the like requires particularly high precision. Process. In a manufacturing process of a MOS-FET in which a source / drain region is formed in a self-aligned manner, the dimensional accuracy and cross-sectional shape of a gate electrode are channel length, the dimensional accuracy of a side wall for realizing an LDD structure, the source This is because it directly affects the formation region of the / drain region. Another important reason is that it is necessary to process a gate insulating film, which has become increasingly thin in recent years, with extremely high selectivity to the underlayer.

However, in general, in the dry etching process, it is indispensable to perform a slight over-etching in consideration of the uniformity of the processing within the wafer surface, and high selectivity to the underlayer and high anisotropy are required throughout the process. Maintaining is not really easy. For example, among the above-mentioned sulfur halides, S ₂ F ₂ can be expected to be used for gate electrode processing because it can be expected to have a high etching rate and is relatively easy to handle. However, in such a system in which F ^{*, which} is extremely reactive, is the main etching species, it is difficult to maintain high selectivity to the gate insulating film made of silicon oxide (SiO ₂ ) even during overetching. It is. This is because the value of the interatomic bond energy is 111 kcal for a Si—O bond.
/ Mol compared to 132 kc for the Si-F bond.
This is supported by the large al / mol. Therefore, an object of the present invention is to provide a dry etching method that can prevent deterioration of an anisotropic shape and a decrease in selectivity with respect to an underlayer even during overetching, and can utilize characteristics of sulfur halide.

[0010]

SUMMARY OF THE INVENTION The dry etching method of the present invention is proposed to achieve the above-mentioned object, wherein the temperature of a substrate to be etched is controlled to room temperature or less,
S ₂ F ₂ , SF ₂ , SF ₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , S
Overetching with a step of etching the silicon-based material layer, the etching gas mainly containing bromine-based gas by using an etching gas containing at least one compound selected from ₂ Cl _2, SCl ₂ And a process.

[0011]

In the present invention, most of the silicon-based material layer is etched using sulfur fluoride or sulfur chloride (hereinafter, the etching process up to this point is called just etching), and the subsequent over-etching is performed using a bromine-based gas. The etching gas is mainly used.

[0012] Sulfur fluoride or sulfur chloride used in the process up to the just etching is based on F / F which has been proposed by the present applicant in a series of applications.
It is a compound having a low S ratio or Cl / S ratio. When sulfur fluoride is used, F ^* having a small atomic radius and extremely high reactivity is generated, and contributes as a main etching species, so that the etching reaction proceeds at a high speed.
On the other hand, when sulfur chloride is used, since the main etching species is Cl ^* , the etching rate is slightly lower than that in the case of F ^* , but it is more advantageous from the viewpoint of the selectivity to SiO ₂ . This is apparent from the fact that the interatomic bond energy of the Si—Cl bond is 96 kcal / mol, which is smaller than that of the Si—O bond. Any of the compounds can generate F ^* or Cl ^* as an etchant of the silicon-based material layer by discharge dissociation and simultaneously generate S in the plasma. Generated S
Is easily deposited on the surface of the substrate to be etched because the substrate is maintained at a temperature lower than room temperature. Here, the S deposited on the ion incident surface is immediately removed by sputtering, but the deposition of S continues on the side wall of the pattern where the incidence of ions is small, and this functions as a sidewall protective film. Moreover,
Since the radical reaction is suppressed to some extent by controlling the temperature of the substrate to be etched, high anisotropy is ensured. Moreover, the deposited S can be easily removed by sublimation if the temperature of the substrate to be etched is raised to a temperature higher than room temperature after completion of the etching, so that particle contamination does not occur in the etching system.

In the subsequent over-etching, a bromine-based gas is used. Since the interatomic bond energy of the Si—Br bond is 88 kcal / mol, which is smaller than that of the Si—O bond, Br ^* does not spontaneously etch SiO ₂ . This is the reason why high selectivity can be achieved for the SiO ₂ gate insulating film in the present invention.

Regarding the technique of using a bromine-based gas at the time of over-etching, the present inventor has previously described in Japanese Patent Application No. Hei.
No. 265236, specifically, after etching a polycide film to a just-etched state with a SF ₆ / HBr mixed gas system, cooling the substrate to be etched to 0 ° C. or less, and using a single gas system of HBr. To perform over-etching. Although the present invention follows the idea of the prior application for the over-etching portion, the process up to just etching is more advantageous than the above-mentioned prior application. That is, in the above-mentioned SF ₆ / HBr mixed gas system, the deposition of S did not occur, and the protection of the side wall was performed by the reaction product of the fragment of the resist mask with Br or the etching reaction product SiBr _x . In contrast,
In the present invention, since the S generated from the gas phase protects the side wall, particle contamination can be reduced, and the selectivity to resist is improved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Embodiment 1 In this embodiment, the present invention is applied to gate processing, and a polycrystalline silicon layer is etched to a just-etched state using S ₂ F ₂ and then over-etched using HBr. It is an example.

First, an n ⁺ -type polycrystalline silicon layer is formed on a single-crystal silicon substrate via a gate oxide film of SiO _2, and a resist mask patterned in a predetermined shape is formed. Was prepared. The wafer is set on a wafer mounting electrode of a magnetic field microwave plasma etching apparatus, and an ethanol refrigerant is supplied and circulated from a cooling system such as a chiller to a cooling pipe built in the wafer mounting electrode. Was cooled to about -60 <0> C. In this state, the S ₂ F ₂ flow rate 20S
CCM, gas pressure 1.3 Pa (10 mTorr), microwave power 850 W, RF bias power 10 W (2
Under the condition of (MHz), the polycrystalline silicon layer was etched (just-etched) almost by the thickness of the polycrystalline silicon layer. In this process, while the radical reaction by F ^* generated from S ₂ F ₂ proceeds by a mechanism assisted by ions such as S ⁺ and SF _x ⁺ , the etching also proceeds from S ₂ F ₂ and forms on the pattern side wall. Sidewall protection was provided by the deposited S. As a result, a gate electrode having a good anisotropic shape was formed.

However, in the process up to the above-mentioned just etching, since F ^* is a main etching species, the selectivity to the gate oxide film is at most about 5 to 6. Therefore, if over-etching is performed under these conditions, the gate oxide film is likely to be removed in a region where the gate oxide film is relatively quickly exposed. Therefore, overetching was performed by switching the etching gas to HBr. The condition at this time is, for example, an HBr flow rate of 50 S
CCM, gas pressure 1.3Pa (10mTorr), microwave power 850W, RF bias power 5W (2M
Hz) and a wafer temperature of −60 ° C. Under these conditions, the selectivity to the gate oxide film was about 50, and local removal of the gate oxide film could be prevented. This is H
This is because Br ^* generated by dissociation from Br does not spontaneously etch the gate oxide film, and the RF bias power is reduced.

In this embodiment, the deposition of S cannot be expected at the time of over-etching, but a carbon-based compound such as CBr _x which is a reaction product of Br and a resist mask, or a SiBr _x which is an etching reaction product is used. Were deposited on the pattern side wall, and these exerted the effect of protecting the side wall. Therefore, the anisotropic shape of the gate electrode was favorably maintained even during overetching. Since the amount of these deposits is relatively small, it does not lead to particle contamination or the like. The S deposits that served to protect the side walls in the process up to the just etching were easily sublimated and removed by heating the wafer to about 90 ° C. after the completion of the etching. Therefore, no particle contamination occurred.

Embodiment 2 In this embodiment, the present invention is applied to gate processing, and after etching a polycrystalline silicon layer to a just-etched state using S ₂ F ₂ , overetching using S ₂ Br _2. This is an example of performing.

First, after the polycrystalline silicon layer was etched to the just-etched state as in the first embodiment, the etching gas was switched to S ₂ Br ₂ to perform over-etching. The conditions for over-etching are
As an example, the S ₂ Br ₂ flow rate is 20 SCCM and the gas pressure is 1.3.
Pa (10 mTorr), microwave power 850 W,
RF bias power 5W (2MHz), wafer temperature-
60 ° C. Generally, at the time of over-etching, radicals tend to be relatively excessive because the material layer to be etched is reduced. Excessive radicals cause migration on the wafer surface, which attack the pattern side wall and cause a shape abnormality such as an undercut or an inversely tapered shape. However, in the present embodiment, unlike the first embodiment, the sidewall protection is performed by S generated from S ₂ Br ₂ even during over-etching. Therefore,
In this embodiment, not only high selectivity to the gate oxide film was achieved as in the first embodiment, but also more reliable anisotropic processing became possible.

The present invention is not limited to the above-described embodiment. For example, various additional gases may be mixed with the etching gas. For example, when N ₂ is added, enhancement of the side wall protection by the reaction product can be expected, and H ^* and / or silicon-based in the etching system such as H ₂ , H ₂ S, and silane-based gas. If a gas capable of supplying an active species is added, excess halogen radicals can be trapped, and the S deposition effect can be enhanced. Further, a rare gas such as He or Ar may be added for the purpose of obtaining a sputtering effect, a cooling effect, and a dilution effect.

In the above-described embodiment, the case where S ₂ F ₂ is used as the etching gas has been described. However, the same mechanism is used when other sulfur fluoride and sulfur chloride proposed in the present invention are used. As a result, etching species are generated and sidewalls are protected by S. However, it is necessary to vaporize the compound which is in a liquid state at normal temperature by bubbling with an inert gas before introducing the compound into the etching reaction system. In particular, when sulfur chloride is used, since an extremely reactive etching species such as F ^* is not generated, although the etching rate tends to slightly decrease,
This is advantageous from the viewpoint of achieving anisotropy.

[0024]

As is apparent from the above description, according to the dry etching method of the present invention, a silicon-based material layer can be formed with high anisotropy, high speed, high selectivity without using a chlorofluorocarbon gas. Etching can be performed with low contamination. Moreover, since the etching gas mainly bromine-based gas during overetching is used, versus SiO ₂
The base selectivity can be improved. Therefore, the present invention is designed based on a fine design rule, is suitable for manufacturing a semiconductor device having a high degree of integration and high performance, and is extremely excellent as a measure against CFC removal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-110726 (JP, A) JP-A-2-224240 (JP, A) JP-A-2-86126 (JP, A) JP-A-1- 241126 (JP, A) JP-A-62-292324 (JP, A) JP-A-4-84427 (JP, A) JP-A-1-217917 (JP, A) JP-A-2-262334 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/3065 C23F 4/00

Claims (1)

(57) [Claims] The temperature of a substrate to be etched is controlled to a room temperature or lower, and S ₂ F ₂ , SF ₂ , SF ₄ , S ₂ F ₁₀ , and S ₃ Cl are controlled.
Over with the step of etching the silicon-based material layer by using an etching gas containing at least one compound selected from _{2, S 2 Cl 2, SCl} 2, an etching gas mainly containing bromine gas And a step of performing etching.