JPH05343367A - Dry etching method - Google Patents

Abstract

PURPOSE:To provide less contamination, high selectivity, damage, etc., in the case of etching a silicon series material layer to be processed with a trench, a gate, etc. CONSTITUTION:In the case of forming shallow trenches 1a, 1b, a single crystalline silicon substrate 1 is etched by using mixture gas of COS (carbonyl sulfide)/ SF6. In this case, carbonyl group (>C=O), etc., is introduced to carbon series polymer CFX to be formed with decomposed product of a resist mask 4 and COS itself to strengthen its structure, free S(sulfur) generated from the COS is added thereto to form a rigid sidewall protective film 7. Incident ion energy necessary for anisotropy processing and depositing amounts of the carbon based polymer can be reduced, resist selectivity is improved, and particle contamination can be reduced. The film 7 is easily removed by ashing. When it is applied to a gate electrode processing, promising CFC removal is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices, etc., and in particular, performs high anisotropy, high selectivity, low contamination and low damage etching of a silicon-based material layer. Regarding the method.

[0002]

2. Description of the Related Art As semiconductor devices have become more highly integrated and have higher performance as seen in VLSI, ULSI, etc. in recent years, etching of silicon-based material layers such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc. Also in the above, there is a strong demand for a technology that achieves the various requirements of high anisotropy, high selectivity, low contamination, and low damage without sacrificing any of them.

There are two typical fields for etching a silicon-based material layer: trench processing and gate electrode processing. Trench processing is a process for forming trenches for the purpose of isolating fine elements and ensuring the memory cell capacity area. The depth of the trench depends on the type and application of the device, and is 4 to 5 μm (deep trench) for the capacitive element, 1 μm for the MOS-FET (shallow trench) for element isolation, and 4 μ for the bipolar transistor.
It is about m. The opening diameter of each trench is 0.
It is about 35 to 1 μm, and anisotropic processing of a high aspect ratio pattern is required.

Chlorine gas is generally used for trench processing. Since Cl ^* has a larger atomic radius than F ^* , there is little risk that it will spontaneously enter the Si crystal lattice and deteriorate the anisotropic shape, and especially in deep trench processing, silicon oxide is used. This is because high selectivity can be maintained with respect to the etching mask of the system. In reality, however, the cross-sectional shape of the trench is likely to change intricately due to changes in the mask pattern and etching conditions, and shape abnormalities such as undercut and bowing are often experienced. All of these make it difficult to fill trenches and control the capacitance in the subsequent process.

Therefore, in order to prevent the above-described deterioration of the cross-sectional shape of the trench, an etching gas capable of producing a depositable substance under discharge dissociation conditions is used, and the depositable substance is utilized to protect the sidewall. Several methods have been proposed in the past. For example, the applicant of the present invention first disclosed in Japanese Patent Laid-Open No. 63-
The SiCl ₄ / N ₂ mixed gas disclosed in Japanese Patent No. 73526 is a typical example. This, together to generate a Cl ^* and Cl ⁺ from SiCl ₄ as a main etching species, Si _x N in the gas phase by reaction with SiCl ₄ and N _{2
In this method, y} , Si _x N _y Cl _z, etc. are generated, and these are deposited to protect the side wall. According to this technique, particle contamination can be reduced far more than when a carbon-based polymer is used as a sidewall protective substance, and etching can be performed under clean conditions.

Further, the applicant of the present application is disclosed in Japanese Patent Laid-Open No. 64-599.
Japanese Patent No. 17 also discloses a technique of performing silicon trench etching using a Cl ₂ / N ₂ mixed gas. This technique also utilizes Si _x N _y , Si _x N _y Cl _z, etc. as the side wall protective material, but these are generated by the reaction of the etching reaction products SiCl _x and N ₂ . Therefore, the particle contamination can be further reduced as compared with the case where the depositable substance is generated in the gas phase due to the reaction between the constituent components of the etching gas as in the process using the SiCl ₄ / N ₂ mixed gas described above. It will be possible.

On the other hand, a typical etching process for polycrystalline silicon is gate processing. The pattern width of the gate electrode directly affects the channel length when the source / drain regions of the MOS-FET are formed in a self-aligned manner and the dimensional accuracy of the sidewall in the LDD structure. Therefore, this process also requires extremely high processing accuracy.

Conventionally, CFC11 has been used for processing the gate electrode.
CFC (chlorofluorocarbon) gas represented by 3 (C ₂ Cl ₃ F ₃ ) and the like has been widely used as an etching gas. Since CFC gas has F and Cl as constituent elements in one molecule, depending on the conditions, a radical reaction due to contributions of F ^* , Cl ^*, etc. and an ion-assisted reaction due to contributions of CCl _x ⁺ , Cl ⁺ etc. are balanced. It is possible to proceed with etching while controlling. Further, it is possible to achieve high anisotropy while protecting the side wall with the carbon-based polymer deposited from the gas phase.

However, it is known that CFC gas is one of the causes of the depletion of the ozone layer of the earth as well known, and the production and use thereof will be prohibited in the near future. Therefore, even in the field of dry etching, C
There is an urgent need to find alternatives to FC gas and establish effective ways to use them. Further, if the design rule of the semiconductor device is further miniaturized in the future, it is considered that carbon-based polymer deposited from the gas phase becomes a source of particle contamination, and from this point of view, countermeasures against CFC depletion are desired.

One of the promising technologies as one of the countermeasures against this CFC removal is a process of using a Br type chemical species as a main etching species. For example, Digest o
fPapers 1989 2nd MicroPro
cess Conference, p. 190 to H
Processing of n ⁺ type polycrystalline silicon gate electrodes using Br has been reported. Br has a large ionic radius and does not enter the crystal lattice or the crystal grain boundaries of the silicon-based material layer. Therefore, there is little possibility that the silicon-based material layer is spontaneously and isotropically etched like F ^* , and the ion
Anisotropic etching can be progressed by the assist mechanism. In addition, when the interatomic bond energies are compared, the Si-O bond (1077 kJ / mol) is Si-B.
As is clear from the fact that it is much larger than r-coupling (368 kJ / mol), high selectivity can be achieved for the gate oxide film made of SiO ₂ . Further, since the surface of the resist mask can be coated with CBr _x having a low vapor pressure, the point that the resist selectivity can be improved is also a great advantage of the Br-based chemical species.

On the other hand, a technique has been proposed in which high anisotropy is not achieved by the side wall protecting action of the carbon-based polymer as described above, but this is achieved by lowering the temperature of the substrate (wafer) to be etched. .. This is a so-called low temperature etching process, and the wafer temperature is reduced to zero.
By keeping the temperature below ℃, the radical reaction on the pattern side wall is frozen or suppressed while the etching rate in the depth direction is maintained at a practical level by the ion assist effect, and shape abnormalities such as undercut are prevented. It is a technology. For example, in the 35th Joint Lecture on Applied Physics (Spring Annual Meeting 1988) Proceedings, p. 495, page No. 28a-G-2, the wafer was cooled to -130 ° C. and SF ₆ gas was used. An example in which a silicon trench etching and an n ⁺ type polycrystalline silicon layer are etched has been reported.

[0012]

However, if the design rules of semiconductor devices continue to progress at a rapid pace, it will be necessary to reduce particle contamination at a higher level than ever before. From this viewpoint, in trench processing, S
The above-described process utilizing i _x N _y , Si _x N _y Cl _z, etc. for sidewall protection satisfies the current requirements but has not fundamentally avoided particle contamination. In addition, since trench processing generally requires a long process time and a large amount of depositable substances are produced, it is premised that such substances can be easily and completely removed after etching even if they are used for sidewall protection.

Even in the process of using HBr for processing the gate electrode, it is difficult to avoid particle contamination due to SiBr _x or the like.

On the other hand, low temperature etching removes CFC.
It is expected to be one of the effective measures, but if we try to rely only on freezing or suppressing the reaction of radicals to achieve high anisotropy, it will be necessary to cool at a low temperature that requires liquid nitrogen as described above. .. However, this causes problems in hardware such as the need for a large-scale special cooling device and the reduction in reliability of the vacuum sealing material. Also,
Since it takes time to cool the wafer and heat it to return it to room temperature, there is a concern that throughput may be reduced, and there is a great risk of impairing economic efficiency and productivity.

In view of the above, the present invention provides a silicon-based material layer which can satisfy various properties that are difficult to achieve at the same time, such as high anisotropy, high selectivity, low contamination, and low damage, at a high level and can be carried out in a practical temperature range. It is an object of the present invention to provide a dry etching method of

[0016]

The dry etching method of the present invention is proposed in order to achieve the above-mentioned object and uses at least an etching gas containing an etching gas containing carbonyl sulfide and a halogen-based compound. It is characterized in that the silicon-based material layer is etched while depositing the carbon-based polymer and sulfur on the sidewall surface of the pattern.

The present invention also relates to an etching / etching method in which carbonyl sulfide is added to a gas composition capable of generating a halogen-based chemical species and free sulfur in plasma under discharge dissociation conditions.
It is characterized in that the silicon-based material layer is etched while using a gas to deposit the carbon-based polymer and sulfur on at least the sidewall surface of the etching pattern.

The present invention also uses an etching gas containing carbonyl sulfide and a halogen-based compound, and substantially deposits the silicon-based material layer while depositing the carbon-based polymer and sulfur on at least the sidewall surface of the etching pattern. Using a just etching step of etching only the layer thickness, and an etching gas obtained by adding carbonyl sulfide to a gas composition capable of generating halogen-based chemical species and free sulfur in plasma under discharge dissociation conditions, And a carbon-based polymer and sulfur on at least a sidewall surface of the etching pattern while etching the remaining portion of the silicon-based material layer.

The present invention is further characterized in that after the etching is completed, at least the carbon-based polymer and the sulfur deposited on the sidewall surface of the etching pattern of the silicon-based material layer are removed by ashing.

[0020]

In order to achieve the above object, the present inventor has come to the conclusion that it is extremely effective to enhance the film quality of the carbon-based polymer forming the side wall protective film as compared with the conventional one and improve the etching resistance. It was This is because the following advantages can be expected in carbon-based polymer reinforcement.

First, since the side wall protection effect is improved, the incident ion energy required for anisotropic processing can be lowered. As a result, it is possible to suppress sputter removal of the etching mask and the gate oxide film, the selectivity for these is improved, and the damage is reduced. Secondly,
Since the deposition amount of the carbon-based polymer required to achieve high anisotropy and high selectivity can be reduced, particle contamination can be reduced as compared with the conventional technique. Further, since the extraction of O atoms from SiO ₂ by the C atoms constituting the carbon-based polymer is suppressed, the selectivity for the gate oxide film is improved when the gate electrode is processed.

Thirdly, by improving the side wall protection effect, F type chemical species and Cl type chemical species having high reactivity with Si can be utilized for etching, so that high anisotropy and high selectivity can be achieved. The etching rate is remarkably increased as compared with the case of relying only on the Br-based chemical species.

In the present invention, a mixed system containing carbonyl sulfide (COS) and a halogen-based compound is used as an etching gas capable of strengthening the carbon-based polymer. Here, needless to say, the halogen-based compound is added to supply the main etching species for the silicon-based material layer. On the other hand, COS has a linear molecular structure of O = C = S, and the carbonyl group in this molecule has a high polymerization promoting activity, thereby increasing the degree of polymerization of the carbon-based polymer and preventing the incidence of ions and radicals. Increase resistance to attacks. Moreover, when the above-mentioned functional group or a fragment derived from this is introduced into the carbon-based polymer, it is merely -CX.
Recent studies have also revealed that chemical and physical stability is higher than that of a conventional carbon-based polymer having a _2- (X represents a halogen atom) repeating structure.
When comparing the binding energies between two atoms, this is C-
O bond (1077 kJ / mol) is C—C bond (607
It is intuitively understood from the fact that it is much larger than kJ / mol). Furthermore, the introduction of the functional group as described above increases the polarity of the carbon-based polymer, and the electrostatic adsorption force to the wafer that is negatively charged during etching is also increased, which also contributes to the etching resistance of the carbon-based polymer. And the surface protection effect is improved.

Furthermore, COS can release S (sulfur) under discharge dissociation conditions. Although depending on the conditions, this S deposits on the surface of the wafer if the temperature of the wafer is controlled to be approximately room temperature or lower, and contributes to sidewall protection or surface protection. In addition, since S is easily sublimated by heating the wafer to approximately 90 ° C. or higher, S itself does not become a source of particle contamination.

As described above, in the present invention, the incident ions necessary for anisotropic processing are enhanced because the film quality of the carbon-based polymer itself is strengthened and the deposition of S can be expected.
Energy can be reduced, selectivity to a resist mask or a base material layer can be improved, and damage can be reduced. In addition, the amount of carbon-based polymer deposited can be relatively reduced, and particle contamination can also be reduced.

The present invention is based on the above idea, but proposes a method aiming at further reduction of pollution and damage. The method is to enhance the deposition of S by the presence of a compound capable of releasing S in addition to COS. In this case, S may be supplied from the same compound as the source of the halogen-based chemical species or may be supplied from another compound. In any case, since the deposition of S is enhanced as compared with the case where S is supplied only from COS,
Incident ions and energy can be further reduced, and high selectivity, low pollution, and low damage can be thoroughly achieved. In addition, the amount of carbon-based polymer deposited can be relatively reduced, and particle contamination can be more effectively reduced.

As described above, if a mixed system containing COS in the presence of a halogen-based chemical species or capable of further enhancing the deposition of S is used, basically one layer of the silicon-based material layer is used.
This makes it possible to perform stepwise etching, and it is possible to obtain a sufficient effect with respect to trench processing that does not require consideration of underlying selectivity. The present invention further proposes a method for improving high speed, low contamination, and underlayer selectivity in gate electrode processing which requires consideration of underlayer selectivity.
It is a two-step etching in which the gas composition is switched between just etching and over etching.

First, in the just etching step of etching the silicon-based material layer substantially by the thickness thereof,
An etching gas containing carbonyl sulfide and a halogen-based compound is used. At this stage, the reinforced carbon-based polymer and S are deposited. Next, in the over-etching step of etching the remaining portion of the silicon-based material layer, an etching gas in which carbonyl sulfide is added to a gas system that can generate halogen-based chemical species and free S is used. At this stage, the carbon-based polymer is of course deposited, but the deposition of S is enhanced. As a result, even if the incident ion energy is reduced in order to reduce damage during overetching, the sidewall protection effect is enhanced, so that a good anisotropic shape of the etching pattern of the silicon-based material layer is maintained. ..

In each of the above etchings,
The carbon-based polymer and S deposited on the side wall surface of the pattern can be removed by ashing. This ashing can also be performed by removing the resist mask if the process uses a resist mask. If the process uses an inorganic etching mask, such as deep trench processing, it is performed in a separate process. In any case, the amount of the carbon-based polymer deposited is much smaller than that in the conventional process, and therefore the removal is easy.
On the other hand, sulfur is easily sublimated by plasma radiant heat or reaction heat during ashing, and is also burned by O ₂ , so there is no possibility of causing particle contamination.

[0030]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 This example is an example in which the present invention is applied to shallow trench processing and a single crystal silicon substrate is etched using a COS / SF ₆ mixed gas. This process will be described with reference to FIG. First, as shown in FIG. 1A, a pad oxide film 2 and a polycrystalline silicon layer 3 were sequentially laminated on a single crystal silicon substrate 1, and a resist mask 4 patterned into a predetermined shape was formed. A sample wafer was prepared. Here, the polycrystalline silicon layer 3
Is formed by, for example, CVD to have a layer thickness of about 0.15 μm, and is provided as a buffer layer for preventing the recession of the edge of the resist mask 4 during etching from being reflected in the deterioration of the trench shape. The pad oxide film 2 is formed to have a layer thickness of 0.01 μm by, for example, thermal oxidation of the single crystal silicon substrate 1, and is a stopper layer for etching back the polycrystalline silicon layer 3 after the trench processing is completed. Is provided as. Further, the resist mask 4 is formed to a layer thickness of 0.7 μm by using a negative type three-component type chemically amplified negative type photoresist material (manufactured by Shipley Co .; trade name SAL-601). A first opening 5 having an opening diameter of 0.35 μm and a second opening 6 having an opening diameter of 1 μm are formed by laser lithography and alkali development.

Next, the above wafer was set on the wafer mounting electrode of the RF bias application type magnetic field microwave plasma etching apparatus. The wafer mounting electrode has a built-in cooling pipe, and the wafer can be cooled to a desired temperature by receiving an appropriate coolant supply from a cooling facility such as a chiller installed outside the apparatus. Here, ethanol was used as a coolant, and etching was performed under the following conditions as an example.

COS flow rate 10 SCCM SF ₆ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTorr) Microwave power 850 W (2.45 GHz) RF bias power 30 W (2 MHz) Wafer temperature -30 ° C.

In this process, F generated by dissociation from SF ₆ is produced.
^The radical reaction due to ^* etc. is C ⁺ , CO ⁺ , COS ⁺ ,
Etching progressed by a mechanism assisted by the incident energy of ions such as S ⁺ and SF _x ⁺ . At the same time, CF _x derived from decomposition products of the resist mask 6 is generated.
Was further produced, and further, a carbonyl group, a C—O bond, etc. were incorporated into the structure to produce a strong carbon-based polymer.
The carbon-based polymer is deposited on the side wall of the pattern, and the carbon-based polymer shown in FIG.
By forming the side wall protective film 7 as shown in (b), a high etching resistance was exhibited although the deposition amount was small, which contributed to anisotropic processing. The side wall protection film 7 also contains free S dissociated from COS. Moreover, in this embodiment, the radical reaction on the side wall surface of the pattern is suppressed by the effect of wafer cooling. As a result, the conventional CFC
Although the RF bias power is reduced by about 70% as compared with the process using gas, the shallow trenches 1a and 1b having a good anisotropic shape are formed, and the resist selectivity is about the same as that of the conventional one. Doubled.

If only the anisotropic etching of the single crystal silicon substrate 1 is intended, the etching gas of this embodiment may generate Cl ^* or Br ^* as a halogen-based chemical species. Should be good. However, in the shallow trench processing, it is usual that the polycrystalline silicon layer 3 and the pad oxide film 2 are also etched by a gas system having a common composition. Therefore, in order to remove the pad oxide film 2 without generating a residue, SF ₆ Is added to generate F ^* capable of etching the SiO ₂ -based material. This F ^* naturally contributes to speeding up of the shallow trench processing. This is also extremely effective in preventing the loading effect.

Generally, in the shallow trench processing, the area to be etched reaches 50% or more of the wafer area, and the area to be etched is an order of magnitude larger than that in the deep trench processing which is 5% or less. I won't. When the area to be etched increases in this way, the etching rate inevitably decreases due to the loading effect, and in some cases, the rate of decrease reaches nearly 50%. Therefore, in order to realize a practical process, it is essential to improve the etching rate. Therefore, the process in which F ^* can be used together and the anisotropy and the resist selectivity are not deteriorated as in this embodiment is extremely practical.

Finally, the wafer was transferred to a plasma ashing apparatus, and the resist mask 4 was removed by burning under the conditions of normal O ₂ plasma ashing. At this time, as shown in FIG. 1C, the side wall protective film 7 was also promptly removed. The sidewall protective film 7 is composed of the carbon-based polymer reinforced as described above and S. However, since the deposited amount of the carbon-based polymer is much smaller than that in the conventional process, the particle level is deteriorated. I didn't do it.

Example 2 This example is also an example of shallow trench processing, but a COS / S ₂ F ₂ mixed gas is used as an etching gas to enhance the deposition of S (sulfur) and select a resist. This is to further improve the property and reduce pollution. The wafer used as the etching sample in this example is the same as that shown in FIG. As an example, this wafer was etched under the following conditions.

COS flow rate 10 SCCM S ₂ F ₂ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850W (2.45GH)
z) RF bias power 20W (2MHz) Wafer temperature -30 ° C

The above S ₂ F ₂ is not only a source of F ^* , but also plays an important role of releasing S under discharge dissociation conditions. That is, in this example, in addition to CF _x reinforced by a carbonyl group or a C—O bond, S generated from both COS and S ₂ F ₂ can participate in the formation of the sidewall protective film 7. Due to these effects, favorable anisotropic processing could be performed despite the condition that the incident ion energy was lower than in Example 1. Further, since the amount of carbon-based polymer deposited could be further reduced by the amount of enhanced S deposition, particle contamination was significantly reduced.

When O ₂ plasma ashing was performed after the etching was completed, as shown in FIG. 1C, the resist mask 4 and the side wall protective film 7 were quickly removed.

Example 3 This example is an example in which the present invention is applied to deep trench processing and a single crystal silicon substrate is etched using COS / Cl ₂ . This process will be described with reference to FIG. First, as an example, as shown in FIG. 2A, a sample wafer was prepared in which an etching mask composed of a SiO ₂ pattern 12 and sidewalls 13 was formed on a single crystal silicon substrate 11. Here, the above-mentioned SiO ₂ pattern 12 is a novolak-based positive photoresist material (Tokyo Ohka Kogyo Co., Ltd.) that is patterned by g-line exposure and alkali development on a SiO ₂ deposited film having a layer thickness of 0.2 μm formed by CVD or the like. Product name: TS
An opening having a diameter of 0.5 μm is formed by etching through a mask made of MR-V3). Also, the sidewall 13 is formed on the entire surface of the wafer after removing the resist mask, as an example, by using TEOS.
A SiO ₂ deposited film is formed by CVD using (tetraethoxysilane) as a source gas, and the SiO ₂ deposited film is subjected to RIE.
It is formed by etching back by. In this way, the opening diameter of the opening 14 formed in the etching mask is reduced to 0.2 μm, exceeding the resolution limit of photolithography.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the single crystal silicon substrate 11 was etched under the following conditions. COS flow rate 10 SCCM Cl ₂ flow rate 10 SCCM Gas pressure 0.27 Pa (= 2 mTorr
r) Microwave power 850W (2.45GHz) RF bias power 50W (2MHz) Wafer temperature -30 ° C

In this etching process, the radical reaction due to Cl ^* generated from Cl ₂ causes C ⁺ , CO _x ⁺ , C
The single crystal silicon substrate 11 was etched by a mechanism assisted by the incident energy of ions such as OS ⁺ , S ⁺ and Cl _x ⁺ . At this time, a carbonyl group, a C—O bond, etc. are incorporated into the discharge dissociation product of COS to form a strong carbon-based polymer, which is deposited on the side wall surface of the pattern, as shown in FIG. 2B. The side wall protective film 15 was formed. That is, the COS also plays a role of supplying the fragment, which is the raw material of the carbon-based polymer, into the gas phase in the system where the carbon-based polymer is not supplied from the etching mask as in the present embodiment. Moreover, COS can also release S, which contributes to the formation of the sidewall protection film 15. The RF bias power is conventional, for example Cl ₂ /
Compared with the etching by the N ₂ mixed gas system, the etching rate is almost halved, and the selection ratio with respect to SiO ₂ could be improved to about twice that of the conventional etching. Furthermore, the mean free path of the ions is extended by greatly reducing the gas pressure, and a device for increasing the vertical incident component on the wafer surface has been devised. Due to these effects, the deep trench 11a having an anisotropic shape was formed.

After the completion of etching, O ₂ plasma ashing was performed on the wafer, and the sidewall protection film 15 was quickly removed as shown in FIG. 2 (c), causing any particle contamination. It never happened.

Example 4 This example is also an example of deep trench processing, but a COS / Cl ₂ / H ₂ S mixed gas was used as an etching gas. First, the wafer shown in FIG. 2A was set in a magnetic field microwave plasma etching apparatus, and etching was performed under the following conditions as an example.

COS flow rate 10 SCCM Cl ₂ flow rate 10 SCCM H ₂ S flow rate 5 SCCM Gas pressure 0.27 Pa (= 2 mTor)
r) Microwave power 850 W (2.45 GHz) RF bias power 50 W (2 MHz) Wafer temperature -30 ° C. In this example, Cl _{2 is} the source of Cl ^* , and S for the augmented amount.
Although H ₂ S is separately added as a source of
The mechanism for forming the side wall protective film 15 as shown in (b) is almost as described above in the third embodiment. Also in this example, the deep trench 11a having a good anisotropic shape was formed.

Example 5 In this example, the present invention is applied to processing a gate electrode, and COS
In this example, the polycrystalline silicon layer is just-etched using the / HBr mixed gas, and then overetched using the COS / S ₂ Br ₂ mixed gas. This process will be described with reference to FIG.

The wafer used as the etching sample in this example is as shown in FIG.
An n-type polycrystalline silicon layer 2 having a thickness of approximately 0.3 μm, which is formed by doping n-type impurities through a gate oxide film 22 having a thickness of approximately 0.01 μm and made of SiO ₂ on a single crystal silicon substrate 21.
3 is formed, and a resist mask 24 having a thickness of about 1 μm is further formed in a predetermined pattern on this.

This wafer was subjected to magnetic field microwave plasma
The n-type polycrystalline silicon layer 23 was etched under the following conditions by setting in an etching apparatus. COS flow rate 10SCCM HBr flow rate 10SCCM Gas pressure 0.67Pa (= 5mTo
rr) Microwave power 850W (2.45GH)
z) RF bias power 30 W (2 MHz) Wafer temperature −30 ° C. Br generated by dissociation from HBr in this etching process
Etching proceeds with ^* as the main etching species. At this time, CBr reinforced by a carbonyl group or C—O bond
_{Since the x-} based polymer and S supplied from COS were deposited to form the side wall protective film 25, the gate electrode 23a excellent in anisotropic shape was formed. However, since the surface of the resist mask 24 is also covered with the CBr _x polymer having a low vapor pressure, the selectivity to the resist mask 24 is high.

This etching was completed when the surface of the gate oxide film 22 was exposed, but the remaining portion 23b of the n-type polycrystalline silicon layer 23 was partially left in the etched region.

Therefore, the etching conditions were switched as follows by way of example, and over-etching for removing the residual portion 23b was performed. COS flow rate 10 SCCM S ₂ Br ₂ flow rate 10 SCCM Gas pressure 0.67 Pa (= 5 mTo
rr) Microwave power 850W (2.45GH)
z) RF bias power 15 W (2 MHz) Wafer temperature −30 ° C. At this stage, the total amount of deposited S is increased by S generated by dissociation from S ₂ Br _2, so that it is much lower than the just etching process. Biasing has become possible.
As a result, it was possible to completely remove the residual portion 23b as shown in FIG. 3C while maintaining extremely high selectivity with respect to the gate oxide film 22.

Finally, when the wafer after etching was transferred to an ashing device and O ₂ plasma ashing was performed, the resist mask 24 and the side wall protective film 25 were cleaned as shown in FIG. 3D. Was removed.

The present invention has been described above based on the five embodiments, but the present invention is not limited to these embodiments. For example, as the halogen compound used in combination with COS, NF ₃ , HCl, ClF ₃ or the like can be used in addition to SF ₆ , HBr, Cl ₂ described above. Compounds that can release free S into plasma under discharge dissociation conditions include H ₂ S, S ₂ F ₂ and S ₂ Br described above.
_In addition to ₂ , other sulfur fluoride such as SF ₂ , SF ₄ , S ₂ F ₁₀ , sulfur chloride such as S ₂ Cl ₂ , S ₃ Cl ₂ , SCl _{2 and} other sulfur such as S ₃ Br ₂ , SBr ₂ Sulfur bromide or the like can be used. In particular, sulfur fluoride, sulfur chloride,
When sulfur bromide is used, these compounds themselves can also serve as the source of halogen species.

The combination of the above compounds is optional, but particularly when shallow trench processing is performed, F ^* can be supplied under discharge dissociation conditions in order to enable rapid removal of the pad oxide film. It is desirable to use a gas system. A rare gas such as He or Ar may be added to the etching gas for the purpose of obtaining a sputtering effect, a cooling effect and a dilution effect.

The silicon material layer to be etched may be made of amorphous silicon in addition to the above-mentioned single crystal silicon and polycrystalline silicon. Further, it goes without saying that the etching apparatus used, the etching conditions, the wafer configuration, etc. can be changed as appropriate.

[0057]

As is apparent from the above description, in the present invention, S is deposited and carbon is deposited by using an etching gas containing carbonyl sulfide and a halogen compound in etching a silicon-based material layer. High anisotropy and high selectivity can be achieved even if the film quality of the carbon-based polymer is enhanced and the relative deposition amount of the carbon-based polymer is reduced. Moreover, these can be achieved in a practical wafer temperature range. Further, if the etching gas further contains a sulfur-based compound capable of releasing S under discharge dissociation conditions, the deposition of S will be enhanced, and further higher selectivity, lower pollution, and lower damage will be achieved. be able to.

The present invention is extremely suitable for manufacturing a semiconductor device which is designed based on a fine design rule and which requires high integration, high performance and high reliability. Particularly in the gate electrode processing, it can provide a promising measure against CFC removal.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to shallow trench processing in the order of steps, (a) showing a pad oxide film and a polycrystalline silicon layer on a single crystal silicon substrate. The state where the resist mask is formed, (b) shows the state where the sidewall trench is formed while forming the shallow trench, and (c) shows the state where the resist mask and the sidewall protective film are removed by ashing. ..

FIG. 2 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to deep trench processing in the order of steps, (a) showing a state where an etching mask made of SiO ₂ is formed on a single crystal silicon substrate. , (B) show a state in which the deep trench is formed while the side wall protective film is formed, and (c) shows a state in which the side wall protective film is removed by ashing.

FIG. 3 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to processing a gate electrode in the order of steps thereof,
(A) is a state where a resist mask is formed on the n-type polycrystalline silicon layer, (b) is a state where the n-type polycrystalline silicon layer is just-etched, and (c) is an over-type n-type polycrystalline silicon layer. Etched state, (d) shows a state in which the resist mask and the side wall protective film are removed by ashing.

[Explanation of symbols]

1,11,21 ・ ・ ・ Single crystal silicon substrate 1a, 1b ・ ・ ・ Shallow trench 2 ・ ・ ・ Pad oxide film 3 ・ ・ ・ Polycrystalline silicon layer 4,24 ・ ・ ・ Resist mask 7,15,25・ ・ ・ Sidewall protective film 11a ・ ・ ・ Deep trench 12 ・ ・ ・ SiO ₂ pattern 13 ・ ・ ・ Sidewall 22 ・ ・ ・ Gate oxide film 23 ・ ・ ・ n-type polycrystalline silicon layer 23a ・ ・ ・ Gate electrode

Claims (4)

[Claims] 1. An etching gas containing carbonyl sulfide and a halogen-based compound is used, and at least etching.
A dry etching method comprising etching a silicon-based material layer while depositing a carbon-based polymer and sulfur on a sidewall surface of a pattern. 2. An etching gas obtained by adding carbonyl sulfide to a gas composition capable of generating a halogen-based species and free sulfur in plasma under discharge dissociation conditions,
A dry etching method characterized by etching a silicon-based material layer while depositing a carbon-based polymer and sulfur on at least a sidewall surface of an etching pattern. 3. An etching gas containing carbonyl sulfide and a halogen-based compound is used, and at least etching.
Just etching process that etches the silicon material layer substantially by its thickness while depositing carbon-based polymer and sulfur on the side wall surface of the pattern, and halogen-based species and liberation in plasma under discharge dissociation conditions. Of the silicon-based material layer while depositing the carbon-based polymer and sulfur on at least the sidewall surface of the etching pattern by using an etching gas formed by adding carbonyl sulfide to a gas composition capable of generating sulfur and An over-etching step of etching the remaining portion, which is a dry etching method. 4. After the etching is completed, at least the carbon-based polymer and the sulfur deposited on the sidewall surface of the etching pattern of the silicon-based material layer are removed by ashing. Item 4. The dry etching method according to any one of items 3.