JPH06295887A - Dry etching method - Google Patents

Abstract

PURPOSE:To realize anisotropic machining of a thin silicon based material layer in which etching reaction products of sufficient quantity for protecting the side wall can not be produced. CONSTITUTION:A depositional substance is created in a plasma prior to etching and supplemented as a side wall protective substance during the etching operation. For example, when a polysilicon layer 3 as thin as 100nm is etched using a Br based etching species and an SOG mask 4 in the machining of a gate electrode, production of etching reaction product SiBrx having low vapor pressure and contributable to side wall protection is insufficient. Preliminary discharge is thereby conducted using a mixture gas HBr/SiBr4 to create SiBrx 5 in the plasma and then the polysilicon layer 3 is etched using HBr gas. This method allows formation of a sufficiently thick side wall protective film 6 thus providing a polysilicon gate electrode 3a having anisotropic profile.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied to a semiconductor process or the like, and particularly when the amount of etching reaction products is small such as the thickness and area of the material layer to be etched are small. The present invention relates to a method for protecting sidewalls and realizing favorable anisotropic processing.

[0002]

2. Description of the Related Art Among various processes for etching a Si-based material layer, the gate electrode processing of a MOS transistor for etching a polysilicon layer, a refractory metal silicide layer, and a polycide film requires a particularly high precision. is there. Moreover, in this case, the thickness of the gate oxide film forming the underlayer of the Si-based material layer has been thinned to around 10 nm in recent years due to the demand for high-speed operation. Maintaining is an important issue.

Needless to say, the technology that has played a leading role in anisotropic processing to date is RIE (reactive ion
Etching). However, in RIE, since accelerated reactive ions collide with the substrate to ensure high anisotropy by a mechanism that promotes reaction with active species, it is essentially difficult to achieve high base selectivity. Therefore, in dry etching for processing a gate electrode, research has been continuously performed to simultaneously achieve high anisotropy and high selectivity.

The etching gas that has been widely used for etching the Si-based material layer is not limited to the processing of the gate electrode, and is CFC (chlorofluorocarbon) -based gas commonly known as CFC gas. This is an isotropic radical reaction due to F ^* (fluorine radical), which causes CF _x ⁺ , CCl
It is a gas that can achieve an anisotropic shape while being assisted by incident ion energy such as _x ⁺ , and the main etching reaction product is SiF _x . However, as is well known, regulations on CFC-based gases are imminent from the standpoint of global environment protection, and they are no longer practical in the future.

Under these circumstances, C is used for processing the gate electrode.
l^*, Br^*It is suggested to apply etching species such as
Has been. For example, Proceedings of
Symposium on Dry Process,
(1988), II-4, the etching gas is SiC.
l _FourWhile cooling the wafer to around -30 ° C
Techniques for etching have been reported.

[0006] In addition, Digest of Paper
s, 1989 2nd MicroProcess C
onference, p. In 190, an example in which anisotropic etching of an n ⁺ type polycrystalline Si layer is performed by RIE using HBr is reported.

Major etching reactions in these technologies
The product is silicon chloride (SiCl _x) And silicon bromide
(SiBr_x). These products are CFC-based
SiF generated when using_xMuch more steam
The pressure is low. Therefore, the practical etching rate is impaired.
If the etching conditions are optimized within the range that does not
Part of the composition is deposited on the pattern side wall surface to protect the side wall.
Can be used.

Further, a gate oxide film (SiO 2_x) Against
It is also possible to secure high selectivity because Cl ^*And Br^*Is etch
This is a major reason why it is favored as a ling species. This is Hara
When comparing the bond energies between the children, Si-Cl bond
(402 kJ / mole) and Si-Br bond (36
8 kJ / mole) is Si-O bond (464 k
J / mole).

In particular, Br ^* is considered to be an essential etching species in the processing of the polycide / gate electrode in the future because it has a merit that it has a large atomic radius and does not spontaneously etch the Si-based material layer. .

However, the above-mentioned ultra-high selectivity is greatly deteriorated when carbon which exerts a reducing action on SiO _x intervenes. To prevent this, for example, the 36th Joint Lecture on Applied Physics (Spring Annual Meeting 1989), Proceedings Proceedings p. 572, Abstract No. 1p-L-7, and Monthly Semiconductor World (Published by Press Journal) 19
January 1990 issue, p. 81-84, a process of thoroughly removing carbon contamination from an etching reaction system, or an inorganic material mask such as an SOG (spin on glass) mask instead of a resist mask as an etching mask. It is effective to adopt.

As an example, FIG. 6 shows a gate electrode process for etching a polysilicon layer using an SOG mask. FIG. 6A is a schematic cross-sectional view showing a state of the wafer before etching. A polysilicon layer 23 having a thickness of about 300 nm is laminated on a Si substrate 21 with a gate oxide film 22 having a thickness of about 10 nm interposed therebetween. Further, an SOG mask 24 that follows the gate electrode pattern is formed thereon.

In this state, when the polysilicon layer 23 is etched by using a bromine-based gas such as HBr, a part of the reaction product SiBr _x is deposited on the side wall surface of the pattern in which the vertical incidence of ions does not occur in principle. Then, the sidewall protection film 25 is formed. As a result, as shown in FIG. 6B, the gate electrode 23a having an anisotropic shape can be formed.

[0013]

However, as the gate electrode layer becomes thinner as the design rules of semiconductor devices become finer, the amount of etching reaction products produced becomes insufficient, resulting in a sufficient sidewall protection effect. There are some cases where we cannot get it. This problem will be described with reference to FIGS. 7 and 8.

FIG. 7A is a schematic cross-sectional view showing the state of the wafer before etching, which is about 100 nm thick on the Si substrate 31 via the gate oxide film 32 having a thickness of about 10 nm.
The polysilicon layer 33 is laminated, and the SOG mask 34 following the gate electrode pattern is further formed thereon. The thickness of this polysilicon layer 33 is as shown in FIG.
It is about 1/3 of the thickness of the polysilicon 23 shown in FIG.

In this state, when the polysilicon layer 23 is etched by using a bromine-based gas such as HBr, anisotropic etching proceeds by the ion assist mechanism up to the just etching state, as shown in FIG. 7 (b). Thus, the gate electrode 33a having an anisotropic shape is formed. However, since the polysilicon layer 23 is thin, the sidewall protection film is hardly formed at this point.

When overetching is continued in this state, as shown in FIG. 7C, the gate electrode 33 is formed.
The cross-sectional shape of b is likely to deteriorate into an inverse tapered shape. this is,
Due to the extremely high selectivity for the gate oxide film 32, the excess Br ^* at the time of over-etching is the gate oxide film 3.
This is because lateral migration occurs on the surface of 2 and attacks the side wall surface of the gate electrode 33a which is not sufficiently protected. Such a side attack by Br ^* is also shown in FIG.
In some cases, notching 35 is generated at the bottom of the gate electrode 33c, as shown in FIG.

The deterioration of the cross-sectional shape of the gate electrode is M
The channel characteristics of the OS transistor are varied, or it is difficult to form sidewalls for the LDD structure or to uniformly cover the gate electrode with the interlayer insulating film, which has a great adverse effect on device characteristics. Such a shortage of the amount of etching reaction products generated is not limited to the case where the thickness of the layer to be etched is thin, and may similarly occur when the area to be etched is small.

Therefore, the present invention provides a dry etching method capable of realizing anisotropic etching even when the thickness or area of the layer to be etched is small and cannot supply a sufficient amount of etching reaction product. It is possible to provide.

[0019]

The dry etching method of the present invention is proposed in order to achieve the above-mentioned object, and an etching reaction product derived from the layer to be etched is formed on at least the sidewall surface of the pattern. When the layer to be etched is etched while being deposited, a depositable substance is generated in the vapor phase before the etching of the layer to be etched is started.

The present invention also comprises, as a method for producing the depositable substance, performing discharge dissociation of a predetermined source gas.

The present invention also provides, as a method of producing the depositable substance, etching back a consumable material layer which is laminated on the layer to be etched and which is capable of producing a depositable etching reaction product.

According to the present invention, the depositable substance is the same as the etching reaction product.

According to the present invention, the etching of the layer to be etched is performed using an inorganic material mask.

Further, the present invention is characterized in that the layer to be etched is made of a silicon material and at least one of SiCl _{x and} SiBr _x is produced as the etching reaction product and the depositable substance.

[0025]

The point of the present invention is that the material to be etched can be deposited on the substrate when it is expected that the material layer to be etched is thin or has a small area, and it is not possible to generate a sufficient amount of etching reaction product to perform sidewall protection. The point is to replenish various sedimentary substances from the gas phase. For this purpose, it is necessary to previously generate a depositable substance in the vapor phase before starting the etching of the layer to be etched. As a means for producing the same, it is practical to perform discharge dissociation of a predetermined source gas, or to stack a dummy material layer in advance on the material layer to be etched and etch back this material layer. .

The deposit material thus generated in the vapor phase is deposited on the surface of the substrate if the substrate is sufficiently cooled in the next etching step and the ion incident energy is sufficiently reduced, and side wall protection is performed. It is effective.

The depositable substance does not necessarily have to be the same substance as the etching reaction product as long as it can exert a desired side wall protection effect and can be easily removed after etching. However, from the viewpoint of minimizing the number of control parameters of the etching reaction, simplifying the etching procedure, preventing unnecessary contamination, and simplifying the process of removing the sidewall protective film, the two should be the same material. Is the best.

The present invention can be applied to dry etching using a resist mask, but is particularly effective when performed using an inorganic material mask. this is,
When a resist mask is used, the carbon-based polymer derived from the decomposition product may contribute to sidewall protection, but when an inorganic material mask is used, there is almost no such possibility. This is because the contribution of substances or sedimentary substances has an even more important meaning.

Note that when such an inorganic material mask is used in processing a gate electrode using a gate oxide film as a base, the base selectivity can be greatly improved.

By the way, the present invention is particularly effective in the process of etching a silicon-based material, as is clear from the example of processing the gate electrode. In this case, if chlorine gas is used as etching gas, S
If iCl _x and bromine gas are used, SiBr _x is produced as an etching reaction product. Therefore, at least one of these two should be generated in advance in the gas phase.

[0031]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 In this example, the present invention is applied to the processing of a polysilicon gate electrode, a preliminary discharge is performed using a HBr / SiBr ₄ mixed gas, and then a thin polysilicon layer is formed using HBr gas. This is an example of etching. This process will be described with reference to FIGS.

The wafer used as the etching sample in this embodiment is, as shown in FIG. 1A, a gate oxide film 2 having a thickness of about 10 nm and a thickness of about 100 nm on a Si substrate 1.
nm polysilicon layer 3 is sequentially laminated, and an SOG mask 4 following the gate electrode pattern is selectively formed thereon.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, preliminary discharge was performed under the following conditions. HBr flow rate 50 SCCM SiBr ₄ flow rate 50 SCCM Gas pressure 1.0 Pa Microwave power 850 W (2.45 GH
z) RF bias power 0 W Wafer mounting electrode temperature −10 ° C. (using alcohol-based coolant) Discharge time 20 seconds By this preliminary discharge, the depositable substance 5 was generated in the plasma. In FIG. 1A, the depositable substance 5 is drawn in the form of particles for the sake of schematic illustration, but the substance is mainly SiBr _x in the form of radicals.

Of the chemical species present in the plasma, Br ^* can be an etching species of the polysilicon layer 3. However, the surface of the polysilicon layer 3 at this time is covered with a natural oxide film (not shown), and since the RF bias is not applied and the ion assist mechanism does not work, the polysilicon layer 3 is not operated. Etching does not proceed.

Of the above conditions, the flow rate of SiBr ₄ is further increased, the temperature of the wafer mounting electrode is further lowered, or the discharge time is extended.
As shown in FIG. 2, the SiBr _x layer 7 may be thinly deposited on the entire surface of the wafer.

Next, the discharge conditions were changed as follows, and the polysilicon layer 3 was etched. HBr flow rate 50 SCCM Gas pressure 1.0 Pa Microwave power 850 W (2.45 GH
z) RF bias power 40 W (2 MHz) Wafer mounting electrode temperature −10 ° C. (using alcohol-based coolant) Here, by applying RF bias power, removal of natural oxide film (breakthrough) is included. The etching of the polysilicon layer 3 has proceeded. Etching reaction product SiBr generated from the thin polysilicon layer 3
The amount of _x is small, and by itself, an anisotropic shape cannot be achieved. However, in this embodiment, since SiBr _x generated by the previous preliminary discharge is deposited from the vapor phase, the side wall protection film 6 as shown in FIG. The silicon gate electrode 3a could be formed. Even if overetching was performed as it was, the anisotropic shape was not deteriorated.

Since no resist mask serving as a carbon supply source is used in this embodiment, the selectivity with respect to the gate oxide film 2 at the time of over-etching was maintained high.

By the way, etching is performed from the above-mentioned preliminary discharge.
To reach 426 nm SiBr_x ^*Luminescence of
It monitors based on the spectrum intensity. This place
In this case, the application of the present invention makes this observation much easier.
It was The reason for this will be described with reference to FIG. Figure 3
Is SiBr on the vertical axis_x ^*Emission intensity, etching on the horizontal axis
It is a graph that takes time (all are arbitrary scales).
The polysilicon layer that is the etching target
If the temperature is relatively hot, the etch
Large amount of SiBr during ching_xIs the etching reaction product
Generated by the
End point E₂Is also easy to determine. On the other hand, the thin policy as described above
When the recon layer 3 is directly etched, SiB
r_xSince the amount of production is small, the change in emission intensity is a solid line graph
As a result, the etching end point E ₁
The determination error of is likely to be large.

On the other hand, in this embodiment, since SiBr _x is supplied into the plasma before the etching is started,
As shown by the one-dot chain line graph, the apparent emission intensity can be increased, and the end point determination becomes easy.

At the time of the above-mentioned preliminary discharge and etching, in order to efficiently deposit the depositable substance generated in the gas phase on the wafer surface during the etching, the inner wall surface of the etching chamber may be a wall-embedded heater. It is particularly effective to heat using, for example.

Example 2 In this example, similarly, in the processing of the polysilicon gate electrode, a preliminary discharge was performed using a Cl ₂ / SiBr ₄ mixed gas, and then a thin polysilicon layer was etched using Cl ₂ gas. . First, the same wafer as the wafer shown in FIG. 1A was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, preliminary discharge was performed under the following conditions.

Cl ₂ flow rate 50 SCCM SiCl ₄ flow rate 50 SCCM Gas pressure 1.0 Pa Microwave power 850 W (2.45 GH
z) RF bias power 0 W Wafer mounting electrode temperature −20 ° C. (using alcohol-based refrigerant) Discharge time 20 seconds By this preliminary discharge, SiCl _x was generated in the plasma as the depositable substance 5. Since this SiCl _x has a higher vapor pressure than SiBr _x described in Example 1, the temperature of the wafer mounting electrode is slightly lowered here.

Next, the discharge conditions were changed as follows, and the polysilicon layer 3 was etched. Cl ₂ flow rate 50 SCCM gas pressure 1.0 Pa microwave power 850 W (2.45 GH
z) RF bias power 30 W (2 MHz) Wafer mounting electrode temperature −20 ° C. (using alcohol-based coolant) Also in this embodiment, the sidewall protection film 6 made of SiCl _x.
While the film was being formed, good anisotropic etching proceeded.

[0045] Example 3 This example of the present invention tungsten (W) - is applied to a polycide gate electrode processing, after completion of the etching of the upper tungsten silicide (WSi _x) layer, H
This is an example in which preliminary discharge was performed using a Br / SiBr ₄ mixed gas, and the lower polysilicon layer was etched using HBr gas. This process will be described with reference to FIG.

The wafer used as an etching sample in this embodiment is, as shown in FIG. 4A, a gate oxide film 12 having a thickness of about 10 nm and a thickness of about 2 on a Si substrate 11.
A W-polycide film 15 having a thickness of 00 nm is sequentially laminated, and an SOG mask 16 that follows the gate electrode pattern is selectively formed thereon. The W-polycide film 15 is formed by stacking a polysilicon layer 13 having a thickness of about 100 nm and a WSi _x layer 14 having a thickness of about 100 nm in this order from the lower layer side.

This wafer was set in an RF bias application type magnetic field microwave plasma etching apparatus, and as an example, the WSi _x layer 14 was etched under the following conditions. Cl ₂ flow rate 50 SCCM O ₂ flow rate 10 SCCM Gas pressure 0.4 Pa Microwave power 850 W (2.45 GH
z) RF bias power 40 W (2 MHz) Wafer mounting electrode temperature 0 ° C. (using alcohol-based coolant) For etching a material layer containing W, fluoride of W (WF) was used.
_Since a vapor pressure of _x ) is low, a fluorine-based gas is usually used as an etching gas, but W can be volatilized and removed in the form of oxychloride (WCl _x O _y ) according to the above gas composition. . In this process, Cl _x ⁺ , O _x ⁺
As a result of the ion assist effect such as described above, a WSi _x pattern 14a having an anisotropic shape as shown in FIG. 4B was obtained.

In the case of etching the polycide film,
When etching the silicon layer 13, WSi_xLayer 14
Stronger side wall protection is required compared with etching. So
Here, HBr / SiCl_FourExample 1 using mixed gas
Pre-discharge is performed under the same conditions, and as shown in FIG.
And SiBr as the depositable substance 17 in the gas phase. _xIs generated
Let

Further, the polysilicon layer 13 was etched using HBr gas under the same conditions as in Example 1. In this etching process, the etching progresses while the sidewall protective film 18 is formed by the deposition material 17 in the vapor phase to form the polysilicon pattern 13a having an anisotropic shape, and has the anisotropic shape as a whole. The polycide gate electrode 15a is formed. This anisotropic shape did not deteriorate during overetching.

Fourth Embodiment In the first to third embodiments, the replenishment of the depositable material by the preliminary discharge has been described, but in the present embodiment, the replenishment of the depositable material is carried out on the polysilicon layer which becomes the gate electrode. A method of replenishing through another polysilicon etch-back will be described with reference to FIG. Note that the reference numerals in FIG. 5 are partially common to those in FIG.

The wafer used as an etching sample in this example is shown in FIG. This covers the entire surface of the wafer shown in FIG. 1 (a) and has a thickness of about 100 nm.
Of the consumable polysilicon layer 8 of FIG. This wafer was set in a magnetic field microwave plasma etching apparatus, and as an example, etching was performed under the following conditions.

HBr flow rate 50 SCCM Gas pressure 1.0 Pa Microwave power 850 W (2.45 GH
z) RF bias power 40 W (2 MHz) Wafer mounting electrode temperature −10 ° C. (using alcohol refrigerant)

During the above etching process, the step until the SOG mask 4 and the polysilicon layer 3 are exposed as shown in FIG. 5B is the etching back of the consumable polysilicon layer 8. During this time, SiBr _x is supplied from the consumable polysilicon layer 8 into the plasma as the depositable substance 5.
At the end of the etch back, the residue 8a of the consumable polysilicon layer 8 remains on the side wall surface of the SOG mask 4.

The subsequent process is just etching and over etching of the polysilicon layer 3 using the SOG mask 4. Just etching is shown in Figure 5.
This is the stage until the gate oxide film 2 begins to be exposed as shown in (c). The etching up to this point proceeds while the side wall protective film 6 is formed by SiBr _x supplied from the gas phase, and the polysilicon gate electrode 3a having an anisotropic shape is almost completed. However, the residue 3b of the polysilicon tank 3 was generated following the pattern of generation of the residue 8a.

Over-etching was performed to remove the residue 3b, but the sidewall protective film 6 continues to be formed during this period, so that the anisotropy of the polysilicon gate electrode 3a as shown in FIG. The shape was maintained.

Although the present invention has been described based on the four examples, the present invention is not limited to these examples, and the structure of the wafer, the type of the etching apparatus used, and the pre-discharge conditions are not limited thereto. The etching conditions, the combination of the etching reaction product and the deposition material in the vapor phase, etc. can be changed as appropriate.

[0057]

As is apparent from the above description, according to the present invention, even in a system in which the thickness or area of the layer to be etched is small and it is not possible to expect a sufficient amount of side wall protection by itself, a good anisotropic property is obtained. It is possible to perform sexual processing.
Therefore, for example, it is possible to form a fine and highly reliable gate electrode.

The present invention provides a very useful dry etching technique in the field of semiconductor device manufacturing, where design rules are becoming finer and finer in the future.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to processing a polysilicon gate electrode in the order of steps, and (a) shows a state in which a depositable substance is generated in a gas phase by preliminary discharge. , (B) show the state in which the polysilicon gate electrode is completed by etching the polysilicon layer while forming the sidewall protection film through the SOG mask.

FIG. 2 is a schematic cross-sectional view showing a state in which a SiBr _x layer is deposited and formed on the entire surface of the wafer by the preliminary discharge as a modified example of the process.

FIG. 3 is a graph illustrating the principle of facilitating the determination of the etching end point based on the emission spectrum by applying the present invention.

FIG. 4 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to processing a polycide gate electrode in the order of steps, (a) showing a state in which an SOG mask is formed on a W-polycide film, (b). Is a state in which the WSi _x layer is etched, (c) is a state in which a depositable substance is generated in the vapor phase by preliminary discharge, and (d) is a polycide gate in which the polysilicon layer is etched while forming a sidewall protective film. Each of the completed electrodes is shown.

FIG. 5 is a schematic cross-sectional view showing another process example in which the present invention is applied to the processing of a polysilicon gate electrode, in the order of the steps, and (a) shows an SOG mask on a polysilicon layer to be a gate electrode. A consumable polysilicon layer is stacked between the two, (b) is a state where the consumable polysilicon layer is etched back, (c) is a state where the polysilicon layer is just etched, and (d) is an overetched state of the polysilicon layer. The respective gate electrodes are shown as completed.

FIG. 6 is a schematic cross-sectional view showing a conventional gate electrode processing in the order of steps, (a) showing a state in which an SOG mask is formed on a thick polysilicon layer, and (b) showing a sufficient amount of sidewall protective film. The states in which a polysilicon gate electrode having an anisotropic shape is formed while being formed.

7A and 7B are schematic cross-sectional views for explaining problems of conventional gate electrode processing, FIG. 7A is a state in which an SOG mask is formed on a thin polysilicon layer, and FIG. 7B is anisotropic by just etching. 3C shows a state in which a gate electrode having a uniform shape is formed, and FIG. 7C shows a state in which the cross-sectional shape of the gate electrode is deteriorated into an inverse taper shape by overetching.

FIG. 8 is a schematic cross-sectional view showing a state in which notching has occurred in a gate electrode due to over-etching in conventional gate electrode processing.

[Explanation of symbols]

1, 11 ・ ・ ・ Si substrate 2,12 ・ ・ ・ Gate oxide film 3,13 ・ ・ ・ Polysilicon layer 3a ・ ・ ・ Polysilicon gate electrode 4,16 ・ ・ ・ SOG mask 5,17 ・ ・ ・ Deposition Material 6,18 ・ ・ ・ Sidewall protective film 7 ・ ・ ・ SiBr _x layer 8 ・ ・ ・ Consumable polysilicon layer 15 ・ ・ ・ W-polycide film 15a ・ ・ ・ Polycide gate electrode

Claims (6)

[Claims] 1. A dry etching method of etching an etching target layer while depositing an etching reaction product derived from the etching target layer on at least a side wall surface of a pattern, in a vapor phase before starting the etching of the etching target layer. A dry etching method, which comprises depositing a depositable substance on a substrate. 2. The dry etching method according to claim 1, wherein the depositable substance is generated in a gas phase by discharging and dissociating a predetermined source gas. 3. The depositable material is provided in the gas phase by etching back a consumable material layer which is deposited on the layer to be etched and which can produce a deposition etching reaction product. Claim 1 or claim 2 characterized
The dry etching method described in. 4. The dry etching method according to claim 1, wherein the depositable substance is the same substance as the etching reaction product. 5. The dry etching method according to claim 1, wherein the etching of the etching target layer is performed using an inorganic material mask. 6. The layer to be etched is made of a silicon-based material, and the etching reaction product and the depositable substance are at least one of silicon chloride and silicon bromide. 5. The dry etching method according to any one of 5 above.