JPS61256725A - Dry etching method - Google Patents

Dry etching method

Info

Publication number
JPS61256725A
JPS61256725A JP9773285A JP9773285A JPS61256725A JP S61256725 A JPS61256725 A JP S61256725A JP 9773285 A JP9773285 A JP 9773285A JP 9773285 A JP9773285 A JP 9773285A JP S61256725 A JPS61256725 A JP S61256725A
Authority
JP
Japan
Prior art keywords
gas
vacuum chamber
etching
ammonia
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9773285A
Other languages
Japanese (ja)
Inventor
Kazunori Tsujimoto
和典 辻本
Shinichi Taji
新一 田地
Takeshi Ninomiya
健 二宮
Keizo Suzuki
敬三 鈴木
Sadayuki Okudaira
奥平 定之
Shigeru Nishimatsu
西松 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9773285A priority Critical patent/JPS61256725A/en
Publication of JPS61256725A publication Critical patent/JPS61256725A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To enable the process according to the mask size by introducing ammonium gas into a vacuum chamber alternately with a halogen gas when the gas including a halogen element is introduced in the vacuum chamber to produce a plasma and the etched material is subjected to dry etching therein. CONSTITUTION:In the vacuum chamber 6 comprising a discharge tube 4 projecting to the upper side and having electromagnets 5 arranged on its periphery, a sample table 11 provided with a permanent magnet 12 arranged on the lower side is arranged. On that table, the sample to be etched 10 which is easy to produce side etching such as W, Mo, and Ti is placed. Next, a halogen gas such as SF6 is introduced into the vacuum chamber 6 from a gas source 9 through a pipe 7 and at the same time, a microwave from a microwave oscillator 1 connected to a power source 2 is made incident into the discharge tube 4 through a waveguide 3. At that time, NH3 gas is also contained in the gas source 9 nd these gasses are introduced alternately while a flow control valve 8 controlled by a controller 13 is actuated to prolong the time for the NH3 gas.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、LSI製造プロセスにおけるドライエツチン
グ方法に係り、特に微細パターンを高精度に形成するの
に好適なエツチングガス導入法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a dry etching method in an LSI manufacturing process, and particularly to an etching gas introduction method suitable for forming fine patterns with high precision.

〔発明の背景〕[Background of the invention]

ドライエツチングにおいて寸法精度の向上を図る方法に
は、従来、ソリッド・ステイト・テクノロジー(Sol
id 5tate Technology) 1984
年4月第235〜242頁のように、2種以上のガスを
同時に真空室内に導入する方法があった。この場合、W
シリサイドとポリシリコンの2層ゲート(ポリサイドゲ
ートとも言う)を、SF、 +C2C1”。
Traditional methods for improving dimensional accuracy in dry etching include solid state technology (Sol).
id 5tate Technology) 1984
There is a method of introducing two or more gases into a vacuum chamber at the same time, as shown in April 2013, pages 235-242. In this case, W
SF, +C2C1'' is a two-layer gate of silicide and polysilicon (also called polycide gate).

(フレオン115)の2種類の混合ガスのプラズマ中で
ドライエツチングし、エツチング形状の制御、特にサイ
ドエッチの抑制を行っている。Wシリサイド、およびポ
リシリコンはいずれもSF。
Dry etching is performed in a plasma of a mixture of two types of gases (Freon 115) to control the etching shape, particularly to suppress side etching. Both W silicide and polysilicon are SF.

単独ガスプラズマ中でエツチングが可能であるが、この
場合にはサイドエッチ量が非常に大きくなる欠点がある
。そこで、前記引例ではサイドエッチを抑制するための
混合ガスとしてC,CM F、を用い、SF、とC2C
l2F、の混合比率を最適化することに′よってWシリ
サイド、およびポリシリコンのサイドエッチ量を減少さ
せている。
Etching can be performed in a single gas plasma, but in this case there is a drawback that the amount of side etching becomes very large. Therefore, in the cited example, C and CMF are used as a mixed gas to suppress side etching, and SF and C2C are used as a mixed gas to suppress side etching.
By optimizing the mixing ratio of l2F, the amount of side etching of W silicide and polysilicon is reduced.

Wゲートのドライエツチングにおいても、そのエツチン
グ主ガスとしてSF、ガスを用いることができる。この
場合、前記ポリサイドのエツチングと同様にサイドエツ
チング量が片側0.2〜0.3  μmと大きいことが
欠点である。筆者らは、Wのサイドエッチを抑制するた
めの混合ガスとして、C2CΩF、を始め各種ガスをS
F、に加える方法を検討したが、前記引例のポリサイド
の場合とは異なり、サイドエッチ抑制効果は認められな
かった。
In the dry etching of the W gate, SF gas can also be used as the main etching gas. In this case, the disadvantage is that the amount of side etching is as large as 0.2 to 0.3 .mu.m on one side, similar to the etching of polycide. The authors used S as a mixed gas to suppress side etching of W, including C2CΩF.
A method of adding F. was investigated, but unlike the case of polycide in the cited reference, no side etch suppressing effect was observed.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、前記のようにサイドエッチを生じゃす
いW、 M o 、 T iおよびこれらのシリサイド
のドライエツチングにおいて、サイドエッチ量を大巾に
減少させ、はぼマスク寸法通りの高精度加工を達成でき
るエツチング方法を提供することにある。
The purpose of the present invention is to greatly reduce the amount of side etching in the dry etching of W, Mo, Ti and their silicides, which cause side etching as described above, and to achieve high accuracy according to the mask dimensions. The object of the present invention is to provide an etching method that can accomplish the processing.

〔発明の概要〕[Summary of the invention]

Wのサイドエッチを抑制する1つの方法として、Wの側
壁にエツチングされにくい物質を形成する方法が考えら
れる。W側壁に形成できるエツチングされにくい物質と
して、Wの酸化物、窒化物。
One possible method for suppressing side etching of W is to form a substance that is difficult to be etched on the side walls of W. W oxides and nitrides are materials that can be formed on the W sidewalls and are difficult to etch.

あるいは炭素化合物系の重合膜等が考えられるが、これ
らの中でWの窒化物がアンモニアガスプラズマ中で効率
良く形成できることを見い出した。一方、窒素プラズマ
中でのWの窒化も検討したが、はとんど窒化物は形成で
きなかった。
Alternatively, a carbon compound-based polymer film may be considered, but it has been found that among these, W nitride can be efficiently formed in ammonia gas plasma. On the other hand, nitriding of W in nitrogen plasma was also considered, but nitrides could hardly be formed.

以上のような実験結果に基づいて、Wエツチング中に、
W側壁にアンモニアガスプラズマによってW窒化物を形
成しながら、マスクの下の横方向へのエツチングを抑制
し、サイドエッチの少ないエツチングを達成することを
考えた。これを実際に行うためには、SF、 とアンモ
ニアを交互に真空室内に導入し、SF、のプラズマを発
生させている間にWのエツチングを進行させ、アンモニ
アDプラズマの発生中にWの側壁を窒化させるとい)方
法をくり返せば良い、アンモニアのプラズマ中では、W
の側壁も平面部も窒化されるが、皐面部に形成された窒
化膜は次のサイクルのSF、プラズマ中のイオン照射に
よって除去される。一方、W側壁ではほとんどイオン照
射がないためW窒化膜は除去されにくい。
Based on the above experimental results, during W etching,
The idea was to suppress etching in the lateral direction under the mask while forming W nitride on the W sidewalls using ammonia gas plasma, thereby achieving etching with less side etching. To actually do this, SF and ammonia are alternately introduced into the vacuum chamber, and while the SF plasma is being generated, the etching of W is progressing, and while the ammonia D plasma is being generated, the W sidewall is being etched. In ammonia plasma, W
Both the sidewalls and the flat surface are nitrided, but the nitride film formed on the rough surface is removed by the next cycle of SF and ion irradiation in plasma. On the other hand, since there is almost no ion irradiation on the W sidewall, the W nitride film is difficult to remove.

また、SFGとアンモニアを同時に真空室内に導入し、
これらの混合ガスプラズマ中でWのエツチングを行った
が、この場合にはWの窒化膜が形成されにくく、Wのサ
イドエッチを抑制する効果はほとんどなかった。
In addition, SFG and ammonia were introduced into the vacuum chamber at the same time,
Although W was etched in these mixed gas plasmas, it was difficult to form a W nitride film, and there was almost no effect of suppressing side etching of W.

〔発明の実施例〕[Embodiments of the invention]

以下1本発明の詳細な説明する。 Hereinafter, one aspect of the present invention will be explained in detail.

[実施例1] 第1図は本発明を用いたプラズマエツチング装置の一構
成例である。プラズマ発生手段は有磁場マイクロ波放電
であり、被エツチング材料はWである。ガス源9はSF
、とアンモニアの2系統とした。ガス流量はガス流量調
整弁8で調整し、コントローラ13によってSF、とア
ンモニアを間欠的に供給できるようになっている。
[Example 1] FIG. 1 shows an example of the configuration of a plasma etching apparatus using the present invention. The plasma generating means is magnetic field microwave discharge, and the material to be etched is W. Gas source 9 is SF
, and ammonia. The gas flow rate is adjusted by a gas flow rate adjustment valve 8, and a controller 13 allows SF and ammonia to be supplied intermittently.

第2図は、SFGとアンモニアを流す時間、およびガス
流量の変化量を示したものである。SF。
FIG. 2 shows the time for flowing SFG and ammonia, and the amount of change in the gas flow rate. SF.

およびアンモニアのガス流量は真空室6内の分圧でそれ
ぞれI X 10−3Torrとした。SF、とアンモ
ニアを真空室内に導入する時間は、1周期25secの
中でそれぞれ5 secおよび20secとした。
The gas flow rates of ammonia and ammonia were each set to I.times.10@-3 Torr as a partial pressure in the vacuum chamber 6. The times for introducing SF and ammonia into the vacuum chamber were 5 sec and 20 sec, respectively, within one cycle of 25 sec.

第3図(a)は第2図に示した条件でエツチングした場
合のWゲートの断面を模式的に示した図であるが、W側
壁へW窒化膜21が形成されサイドエッチが抑制された
ため、はぼマスク寸法通りにエツチングされた。
FIG. 3(a) is a diagram schematically showing a cross section of a W gate when etched under the conditions shown in FIG. , the mask was etched according to the dimensions.

第3図(b)は、第2図に示したものと同一のガス流量
で、SF、とアンモニアを真空室内に導入する時間を1
周期25secの中でそれぞれ20secおよび5 s
ecとした場合のエツチング後のWゲート断面図である
。この場合には顕著なサイドエッチ抑制の効果は認めら
れない。
Figure 3(b) shows the introduction of SF and ammonia into the vacuum chamber for 1 time at the same gas flow rate as shown in Figure 2.
20 sec and 5 s in a period of 25 sec, respectively.
FIG. 3 is a sectional view of the W gate after etching in the case of ec. In this case, no significant side etch suppression effect is observed.

[実施例2] 実施例1で第2図に示した条件を第4図のように変えた
場合も、Wのサイドエッチが低減できた。
[Example 2] Even when the conditions shown in FIG. 2 in Example 1 were changed as shown in FIG. 4, side etching of W could be reduced.

ただし、Wのニッチ速度は30〜40%程度、減少した
However, the niche velocity of W decreased by about 30-40%.

[実施例3コ 実施例1で第1図に示したマイクロ波プラズマエツチン
グ装置の替わりに、第5図に示したような通常の反応性
スパッタ装置を用いた場合にも、Wのサイドエッチ抑制
効果が認められた。ただし、アンモニアガスの解離効率
がマイクロ波プラズマエツチング装置よりも低いためW
の窒化の効率も減少し、実施例1よりも若干サイドエッ
チが増大した。
[Example 3] Even when a normal reactive sputtering device as shown in FIG. 5 is used in place of the microwave plasma etching device shown in FIG. 1 in Example 1, side etching of W can be suppressed. The effect was recognized. However, since the dissociation efficiency of ammonia gas is lower than that of microwave plasma etching equipment, W
The efficiency of nitriding also decreased, and side etching increased slightly compared to Example 1.

[実施例4コ 実施例1に示したWの替わりに、Ti、Ta。[Example 4 Instead of W shown in Example 1, Ti and Ta were used.

Si、あるいはW、Ti、TaのSi化合物を被エツチ
ング材料とした場合にも同様のサイドエッチ抑制効果が
認められた。ただし、それぞれの材料における窒化の効
率が異なるため、SF、とアンモニアのガス流量をそれ
ぞれの材料で若干変更する必要があった。
A similar side etch suppression effect was observed when Si or a Si compound of W, Ti, or Ta was used as the material to be etched. However, since the nitriding efficiency of each material differs, it was necessary to slightly change the gas flow rates of SF and ammonia for each material.

[実施例5] 実施例1に示したS F g の替わりに、SF、。[Example 5] Instead of SF g shown in Example 1, SF.

NF、等の弗素を含むガスを用いた場合も、同様のサイ
ドエッチ抑制効果が認められた。
A similar side etch suppression effect was also observed when a gas containing fluorine such as NF was used.

[実施例6] Siエツチングにおいて、CCQ、とアンモニアを実施
例1のごとく交互に真空室内に導入してエツチングを行
った。この場合もSi@壁に窒化Siが形成され、サイ
ドエッチ抑制効果が認められた。
[Example 6] In Si etching, CCQ and ammonia were alternately introduced into the vacuum chamber as in Example 1. In this case as well, Si nitride was formed on the Si@ wall, and the effect of suppressing side etch was observed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、弗素を含むガスでドライエツチングし
た場合に特にサイドエッチを生じやすい、W、Ti、T
a、Siあるいは、それらの化合物の高精度エツチング
ができるので、0.8  μm〜0゜5 μm領域の極
微細配線パターンの形成を可能にできる効果がある。
According to the present invention, W, Ti, and T
Since highly accurate etching of a, Si, or their compounds can be performed, it is possible to form ultra-fine wiring patterns in the range of 0.8 μm to 0.5 μm.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に用いるマイクロ波プラズマエツチング
装置の概略図、第2図はSF、 とアンモニアを交互に
流す時間間隔、およびガス流量の設定値を説明する図、
第3図(a)は第2図に余した条件でエツチングした場
合のWゲート断面の模式図、第3図(b)はSF、とア
ンモニアを交互に流す時間間隔が不適当な場合のWゲー
ト断面の模式図、第4図はアンモニアを連続的に供給す
る場合の説明図、第5図は本発明に用い得る反応性スパ
ッタ装置の概略図。 1・・・マイクロ波発振器、2・・・マイクロ波発振器
用電源、3・・・導波管、4・・・放電管、5・・・電
磁石、6・・・真空室、7・・・配管、8・・・ガス流
量調整弁、9・・・ボンベ、1o・・・試料、11・・
・試料台、12・・・永久磁石、13・・・コントロー
ラ、14・・・エツチングマスク、15・・・タングス
テン(W)、16・・・シリコン酸化膜、17・・・下
部電極、18・・・上部電極、19・・・ブロッキング
コンデンサ、2o・・・高周波電源、21・・・W窒化
膜。 f 1 図 菖 2 図 及f!叶圏
FIG. 1 is a schematic diagram of the microwave plasma etching apparatus used in the present invention, and FIG. 2 is a diagram illustrating the time interval for alternately flowing SF and ammonia, and the set value of the gas flow rate.
Figure 3(a) is a schematic diagram of the cross section of the W gate when etched under the conditions left in Figure 2, and Figure 3(b) is a schematic diagram of the W gate cross section when etching is performed under the conditions remaining in Figure 2. FIG. 4 is an explanatory diagram of a case where ammonia is continuously supplied, and FIG. 5 is a schematic diagram of a reactive sputtering apparatus that can be used in the present invention. DESCRIPTION OF SYMBOLS 1... Microwave oscillator, 2... Power supply for microwave oscillator, 3... Waveguide, 4... Discharge tube, 5... Electromagnet, 6... Vacuum chamber, 7... Piping, 8...Gas flow rate adjustment valve, 9...Cylinder, 1o...Sample, 11...
- Sample stage, 12... Permanent magnet, 13... Controller, 14... Etching mask, 15... Tungsten (W), 16... Silicon oxide film, 17... Lower electrode, 18... ... Upper electrode, 19... Blocking capacitor, 2o... High frequency power supply, 21... W nitride film. f 1 Illustrated iris 2 Illustrated f! leaf area

Claims (1)

【特許請求の範囲】 1、真空室内に少なくともハロゲン元素を含むガスを導
入しガスプラズマを発生させそのプラズマ中で被エッチ
ング材料をドライエッチングする方法において、エッチ
ング中に前記ハロゲン元素を含むガスとアンモニアガス
とを交互に真空室内に導入し、前記被エッチング材料が
ハロゲン元素を含むガスプラズマと、アンモニアガスプ
ラズマに交互にさらされることを特徴とするドライエッ
チング方法。 2、特許請求の範囲第1項に記載のハロゲン元素を含む
ガスとアンモニアガスとを真空室内に導入する時間は、
少なくとも周期的であり1周期の時間の中でアンモニア
を導入する時間の方が、ハロゲン元素を含むガスを導入
する時間よりも長いことを特徴とするドライエッチング
方法。
[Claims] 1. In a method of introducing a gas containing at least a halogen element into a vacuum chamber to generate gas plasma and dry etching a material to be etched in the plasma, the gas containing the halogen element and ammonia are mixed during etching. A dry etching method characterized in that the material to be etched is alternately exposed to a gas plasma containing a halogen element and an ammonia gas plasma, by alternately introducing a gas into a vacuum chamber. 2. The time for introducing the halogen element-containing gas and ammonia gas according to claim 1 into the vacuum chamber is:
A dry etching method that is at least periodic and is characterized in that the time for introducing ammonia in one cycle is longer than the time for introducing a gas containing a halogen element.
JP9773285A 1985-05-10 1985-05-10 Dry etching method Pending JPS61256725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9773285A JPS61256725A (en) 1985-05-10 1985-05-10 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9773285A JPS61256725A (en) 1985-05-10 1985-05-10 Dry etching method

Publications (1)

Publication Number Publication Date
JPS61256725A true JPS61256725A (en) 1986-11-14

Family

ID=14200065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9773285A Pending JPS61256725A (en) 1985-05-10 1985-05-10 Dry etching method

Country Status (1)

Country Link
JP (1) JPS61256725A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01215986A (en) * 1988-02-24 1989-08-29 Hitachi Ltd Dry etching method
JPH04247619A (en) * 1991-02-04 1992-09-03 Nippon Telegr & Teleph Corp <Ntt> Method for dry-etching metal with high melting point
JPH0513383A (en) * 1990-07-30 1993-01-22 Sony Corp Dry etching method
WO2003030239A1 (en) * 2001-09-28 2003-04-10 Sumitomo Precision Products Co., Ltd. Silicon substrate etching method and etching apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01215986A (en) * 1988-02-24 1989-08-29 Hitachi Ltd Dry etching method
JPH0513383A (en) * 1990-07-30 1993-01-22 Sony Corp Dry etching method
JPH04247619A (en) * 1991-02-04 1992-09-03 Nippon Telegr & Teleph Corp <Ntt> Method for dry-etching metal with high melting point
WO2003030239A1 (en) * 2001-09-28 2003-04-10 Sumitomo Precision Products Co., Ltd. Silicon substrate etching method and etching apparatus

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