JPH02309631A - Plasma etching method - Google Patents

Plasma etching method

Info

Publication number
JPH02309631A
JPH02309631A JP13088389A JP13088389A JPH02309631A JP H02309631 A JPH02309631 A JP H02309631A JP 13088389 A JP13088389 A JP 13088389A JP 13088389 A JP13088389 A JP 13088389A JP H02309631 A JPH02309631 A JP H02309631A
Authority
JP
Japan
Prior art keywords
etching
discharge
power
plasma etching
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13088389A
Other languages
Japanese (ja)
Inventor
Atsushi Koshio
古塩 淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP13088389A priority Critical patent/JPH02309631A/en
Publication of JPH02309631A publication Critical patent/JPH02309631A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control a taper angle of an etching shape by performing etching by periodically repeatedly producing and interrupting rf discharge. CONSTITUTION:After a semiconductor substrate 4 is placed on a lower electrode 3, mixture gas such as SF6 and CCl4 is introduced into a chamber 1, and then rf power from a rf power supply 7 is applied across the electrodes 2 and 3 and switched on and off periodically. Once the rf power is interrupted after a plasma state formed, residence time of neutral molecules such as SF2, SFCl, SCl2 and the like in the chamber 1 is made longer to be about several times of seconds, while radicals have shorter residence time differing from the neutral molecules but exist at a state where the rf power is interrupted. Accordingly, discharge time can be controlled by the repeated production and interruption of the rf discharge. Hereby, a taper angle of an etching shape can be controlled.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、反応性ガスを用いて平行平板型のプラズマエ
ツチング装置を用い、半導体装置面上の多結晶シリコン
膜のエツチングを行なうプラズマエツチング方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a plasma etching method for etching a polycrystalline silicon film on a semiconductor device surface using a parallel plate type plasma etching apparatus using a reactive gas. It is.

従来の技術 従来、反応性ガスを用いる平行平板型のプラズマエツチ
ング装置を用い、半導体装置の多結晶シリコン膜をエツ
チングする場合、対向配置された電極間に高周波放電を
連続に生起しエツチングを行なっている。
Conventional Technology Conventionally, when etching a polycrystalline silicon film of a semiconductor device using a parallel plate type plasma etching apparatus using a reactive gas, etching is performed by continuously generating high-frequency discharge between electrodes placed opposite each other. There is.

発明が解決しようとする課題 このような従来方法においては、反応性ガス。Problems that the invention aims to solve In such conventional methods, reactive gases.

エッヂング圧力、高周波電力など、いくつかのエツチン
グパラメータを操作することによってエツチング形状は
異なってくる。例えば、反応性ガスとしてSFsを用い
てエツチングをした場合、SFsはラジカルを多く生成
可能のため、その形状は等方的エツチングとなり、非常
に大きなアンダーカットが生じる。またSFeにCCe
4を添加した場合は、エツチングマスクであるレジスト
との反応による生成物のCHX SY CQzによる側
壁保護の形成速度とラジカルの側壁への到達速度が平衝
して、食刻形状が垂直形状となる。
The etched shape varies by manipulating several etching parameters such as etching pressure and high frequency power. For example, when etching is performed using SFs as a reactive gas, SFs can generate a large number of radicals, so the shape becomes isotropic etching, resulting in a very large undercut. Also, CCe in SFe
When 4 is added, the rate of formation of sidewall protection by CHX SY CQz, which is a reaction product with the etching mask resist, and the rate of radicals reaching the sidewall are balanced, and the etched shape becomes a vertical shape. .

しかし、前記エツチングパラメータの操作のみでは、上
記以外・の形状は難しく、エツチング形状のテーパ角を
コントロールすることは困難であった。本発明は、この
ような問題を解決するプラズマエツチング方法を提供す
るものである。
However, it has been difficult to produce shapes other than those described above, and it has been difficult to control the taper angle of the etched shape by only manipulating the etching parameters. The present invention provides a plasma etching method that solves these problems.

課題を解決するための手段 この問題を解決するために本発明は、高周波放電を周期
的に繰り返し生起、停止させながらエツチングを行なう
プラズマエツチング方法である。
Means for Solving the Problems In order to solve this problem, the present invention is a plasma etching method in which etching is carried out while periodically repeatedly generating and stopping high-frequency discharge.

作用 反応性ガスSFs 、cce4を用い、高周波電力を印
加し、プラズマ状態を形成した後、高周波電力を切って
からのエツチング反応室内のラジカルおよび中性分子の
滞在時間変化は、SF2゜5FCe 、SCf! 2 
といった中性分子の滞在時間は、排気能力にも影響する
が、一般に数十秒程度は必要とする。ラジカルは中性分
子と異なり、滞在時間は短いが、高周波電力を切った状
態においても存在する。また、当然ながら、高周波電力
を切った状態においては、電荷を保持している電子、イ
オン等は存在しない。よって、高周波放電の生起、停止
を同期的に繰り返し行なうと供に、放電の生起時間をコ
ントロールすることにより、エツチング形状のテーパ角
をコントロールすることが可能となる。
After forming a plasma state by applying high-frequency power using the active reactive gas SFs, CCE4, the residence time changes of radicals and neutral molecules in the etching reaction chamber after the high-frequency power is turned off are as follows: SF2°5FCe, SCf ! 2
The residence time of neutral molecules such as these influences the exhaust capacity, but generally several tens of seconds are required. Unlike neutral molecules, radicals have a short residence time, but they exist even when high-frequency power is turned off. Furthermore, as a matter of course, when the high frequency power is turned off, there are no electrons, ions, etc. that hold charges. Therefore, it is possible to control the taper angle of the etching shape by repeatedly causing and stopping the high-frequency discharge synchronously and by controlling the generation time of the discharge.

実施例 第1図は、多結晶シリコン膜をエツチングするための平
行平板型のプラズマエツチング装置の断面構造図である
。チャンバー1内には、一対の電極2,3が対向配置さ
れている。
Embodiment FIG. 1 is a cross-sectional structural diagram of a parallel plate type plasma etching apparatus for etching a polycrystalline silicon film. Inside the chamber 1, a pair of electrodes 2 and 3 are arranged facing each other.

半導体基板4が、下部電極3に載置された後、チャンバ
ー1内には、5Fs80s e cm、CCe 45 
s e cm、の混合ガスがガス導入口5より導入され
ると供に、圧力コントロールバルブ6により、チャンバ
ー内は、圧力100mTo r rに保持される。次に
設定圧力で電極2.3間に高周波電力源7より高周波電
力50Wが5秒間隔で周期的にオン、オフを繰り返され
、被エツチング量の50%をエツチングした後は、残り
の被エツチング量を連続生起しエツチングする。
After the semiconductor substrate 4 is placed on the lower electrode 3, the chamber 1 contains 5Fs80s e cm, CCe 45
A mixed gas of s cm is introduced from the gas inlet 5, and the pressure inside the chamber is maintained at 100 mTorr by the pressure control valve 6. Next, 50 W of high-frequency power is periodically turned on and off from the high-frequency power source 7 at a set pressure between the electrodes 2 and 3 at 5 second intervals, and after etching 50% of the amount to be etched, the remaining amount to be etched is removed. Continuously generate and etch a large amount.

発明の効果 以上のように本発明によれば、多結晶シリコン膜のエツ
チングに際し、エツチング形状のコントロールが容易に
可能であり、多層構造を有する半導体装置の製造を可能
とする。
Effects of the Invention As described above, according to the present invention, when etching a polycrystalline silicon film, the etched shape can be easily controlled, and a semiconductor device having a multilayer structure can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、プラズマエツチング装置の一部断面構造図で
ある。 1・・・・・・チャンバー、2・・・・・・上部電極、
3・・・・・・下部電極、4・・・・・・半導体基板、
5・・・・・・ガス導入口、6・・・・・・圧力コント
ロールバルブ、7・・・・・・高周波電力源。 代理人の氏名 弁理士 粟野重孝 ほか1名/−−−チ
インハ゛− ?・−上節ta S−一一下部覧抛 4 ・・−牟痺イネ、L!、坂 5−・−冑゛ズ埠入口
FIG. 1 is a partial cross-sectional structural diagram of a plasma etching apparatus. 1... Chamber, 2... Upper electrode,
3... Lower electrode, 4... Semiconductor substrate,
5...Gas inlet, 6...Pressure control valve, 7...High frequency power source. Name of agent: Patent attorney Shigetaka Awano and one other person・-Upper Section ta S-11 Lower List 4 ・--Munumia rice, L! , Saka 5--Kuzubu Entrance

Claims (2)

【特許請求の範囲】[Claims] (1)反応性ガスを導入して互いに対向配置された一対
の平板状電極間に高周波放電を生起し、前記一方の電極
上で半導体装置面上の多結晶シリコン膜を、プラズマエ
ッチングするに際し、前記高周波放電の生起、停止を周
期的に繰り返して、エッチングすることを特徴とするプ
ラズマエッチング方法。
(1) Introducing a reactive gas to generate a high frequency discharge between a pair of flat electrodes arranged opposite each other, and plasma etching the polycrystalline silicon film on the surface of the semiconductor device on the one electrode, A plasma etching method characterized in that etching is performed by periodically repeating the generation and termination of the high-frequency discharge.
(2)前記反応性ガスがSF_6、CCl_4であるこ
とを特徴とする請求項(1)記載のプラズマエッチング
方法。
(2) The plasma etching method according to claim 1, wherein the reactive gas is SF_6 or CCl_4.
JP13088389A 1989-05-24 1989-05-24 Plasma etching method Pending JPH02309631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13088389A JPH02309631A (en) 1989-05-24 1989-05-24 Plasma etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13088389A JPH02309631A (en) 1989-05-24 1989-05-24 Plasma etching method

Publications (1)

Publication Number Publication Date
JPH02309631A true JPH02309631A (en) 1990-12-25

Family

ID=15044929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13088389A Pending JPH02309631A (en) 1989-05-24 1989-05-24 Plasma etching method

Country Status (1)

Country Link
JP (1) JPH02309631A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513383A (en) * 1990-07-30 1993-01-22 Sony Corp Dry etching method
US5268070A (en) * 1991-01-22 1993-12-07 Sony Corporation Dry etching method
JP2000299312A (en) * 1991-04-04 2000-10-24 Hitachi Ltd Plasma treatment method and manufacture of semiconductor device
JP2000299311A (en) * 1991-04-04 2000-10-24 Hitachi Ltd Plasma processing system
JP2002050611A (en) * 1999-07-23 2002-02-15 Applied Materials Inc Method for supplying pulsed plasma in portion of semiconductor wafer process
US6417013B1 (en) 1999-01-29 2002-07-09 Plasma-Therm, Inc. Morphed processing of semiconductor devices
JP2007324165A (en) * 2006-05-30 2007-12-13 Mitsubishi Electric Corp Surface treatment method of silicon substrate and fabrication process of solar cell

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513383A (en) * 1990-07-30 1993-01-22 Sony Corp Dry etching method
US5268070A (en) * 1991-01-22 1993-12-07 Sony Corporation Dry etching method
JP2000299312A (en) * 1991-04-04 2000-10-24 Hitachi Ltd Plasma treatment method and manufacture of semiconductor device
JP2000299311A (en) * 1991-04-04 2000-10-24 Hitachi Ltd Plasma processing system
US6417013B1 (en) 1999-01-29 2002-07-09 Plasma-Therm, Inc. Morphed processing of semiconductor devices
JP2002050611A (en) * 1999-07-23 2002-02-15 Applied Materials Inc Method for supplying pulsed plasma in portion of semiconductor wafer process
JP2007324165A (en) * 2006-05-30 2007-12-13 Mitsubishi Electric Corp Surface treatment method of silicon substrate and fabrication process of solar cell
JP4652282B2 (en) * 2006-05-30 2011-03-16 三菱電機株式会社 Silicon substrate surface treatment method and solar cell manufacturing method

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