GB2338105A - A method of making a thin-film transistor - Google Patents
A method of making a thin-film transistor Download PDFInfo
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- GB2338105A GB2338105A GB9905015A GB9905015A GB2338105A GB 2338105 A GB2338105 A GB 2338105A GB 9905015 A GB9905015 A GB 9905015A GB 9905015 A GB9905015 A GB 9905015A GB 2338105 A GB2338105 A GB 2338105A
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- metal layer
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- film transistor
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- 239000010409 thin film Substances 0.000 title abstract description 63
- 238000004519 manufacturing process Methods 0.000 title abstract description 44
- 229910052751 metal Inorganic materials 0.000 abstract description 232
- 239000002184 metal Substances 0.000 abstract description 232
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 46
- 238000005530 etching Methods 0.000 abstract description 41
- 238000000034 method Methods 0.000 abstract description 38
- 239000000758 substrate Substances 0.000 abstract description 35
- 238000000151 deposition Methods 0.000 abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 abstract description 16
- 238000000059 patterning Methods 0.000 abstract description 16
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 11
- 229910052715 tantalum Inorganic materials 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 9
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 296
- 238000009740 moulding (composite fabrication) Methods 0.000 description 37
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 31
- 239000004065 semiconductor Substances 0.000 description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 229910017604 nitric acid Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 102000020897 Formins Human genes 0.000 description 1
- 108091022623 Formins Proteins 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 241000206607 Porphyra umbilicalis Species 0.000 description 1
- DTQVDTLACAAQTR-UHFFFAOYSA-N Trifluoroacetic acid Chemical compound OC(=O)C(F)(F)F DTQVDTLACAAQTR-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A method of making the gate 49 of a thin film transistor includes the steps of: depositing a first metal layer such as Al, Cu or Au 43 on a substrate 41, depositing a second metal layer 45 such as Mo, Ta or Co directly on the first metal layer 43; forming a single photoresist 47 on the second metal layer 45; patterning the second metal layer 45 by isotropic etching using the photoresist as a mask; patterning the first metal layer 43 by means of an anisotropic etching using the phororesist as a mask, the first metal layer 43 being etched to be wider than the second metal layer by about 1 to 4 Ám, thus forming a gate 49 having a laminated, stepped structure of the first 43 and second metal layers 45; and removing the photoresist. Alternatively, both layers 43,45 can be anisotropically etched and the second layer 45 subsequently isotropically etched to form the gate. Another method mentioned uses a single isoptropic etching step, the different etching rates of the layers 43,45 producing a stepped gate. Such a gate structure prevents hillocks.
Description
0 2338105 1 THIi-FILM TRANSISTOR AND METHOD OF MAKING SA-NIE The present
invention relates to a transistor of a lia'U.'d crystal dis-j'av and, more particularly, to a thin-film - L - - - -1 - -.1. - - --- transistor having a gate including a double-layered metal structure and a method c--- making such a double-layered metal gate.
An LCD (Liquid Crystal Display) includes a switching device as a driving element, and a pixel-arranged matrix structure havin transparen L or light-re-flecting pixel electrodes as its basic units. The sw; .I.tch-4n(i device is a thin-film transistor having gate, source and drain regions.
The gate of' the thin-film transistor is made of alum--,num to reduce its wiring resistance, but an aluminum gate may cause defects such as hillock.
A double-layered metal gate, i.e., molybdenum- coated 2 aluminum gate is considered as a substitute for the aluminum gate to overcome the problem of the hillock.
To fabricate a double-layered gate, metals such as aluminum and molybdenum are sequencially deposited, followed by a patterning process carried out by photolithography to form resulting metal films which have the same width. Although the double-layered gate is desirable to overcome the problem of THockj. the resulting. deposited metal films forming the doublelayered gate are so thick that a severe single step is created by a thickness difference between the metal films and a substrate, thereby causing a single step difference between the substrate and the doublelayered gate which deteriorates the step coverage of a later formed gate oxide layer. The source and drain regions formed on the gate oxide layer may have disconnections between areas of the source and drain regions which are overlapped and non-overlapped with the gate, or electrically exhibit short circuits as a result of contact with the gate.
Accordinj to another method of forming the gate, each,of the metal layers of Al and Mo form a double step difference with the substrate so as to improve the step coverage of the late oxide layer.
r 1 1 3 FIGS.!A ',-hrougr, 1-7 are dacrrams illustrating the process,or Ioab-- "camng a t:h-,i-zi'm transisco- of a -,,iet',-od w-ich is related to the invention described and claimed in the present !-A-IF is not believed to recently discovered met-hod related to the invention described and claimed in the present a=lication.
Refe.rring to FIG. -!A, aluminum is deposited on a substratle 11 to form a first metal layer 13. A first ohotoresist 15 is demosited on the first metal layer 13. The foirst iDhotores-ist 15 4s exposed and develoned so as to have a certain width wi extending along the first metal layer 13.
Referring to FIG. 13, the first metal layer 13 is patterned by wet etching us-ing the first photores-ist 15 as a mask so that the L-;irs-L metal layer 13 has a certain width wi. AJEter the first photoresist iS is removed, a second metal layer 17 is formed by depositing mc, Ta, or Cc on the substrate 11 so as to cover the first metal layer 13. A second photcresist 19 is then deposited on the second metal layer 17. The second photoresist 19 _Js e=osed and develoned so as to have a certain width w2 extending along the second -metal layer 17 and located above the first metal Layer!3. 1 - aonlication. T-e method s'lnown in Figs be zublished prior art but- is -merely a
4 Referring to FIG.!C, the second metal layer 17 is by a wet etching process us-Lng the second photoresist mask such that the second metal!aver 17 has a certain which is narrewer than t'-e widti, wi of the. 1-i--st metal formation of the gate 21, the second.
p-notores:s' removed.
Thus, the matterned first and second metal!avers 13 and 17 form a gate 21 having a double-layered metal structure that provides a double steo difference between the double-layered metal gate structure 21 and the substrate 11. The formation a! the gate 21 as described above and shown, in Figs. 1A-1C requires the use of two photoresists 15, 19 and two iDhotoresist stens.
in the gate 21 shown in Fig. IC t4-.e second metal layer 17 is mreferably centrally located an the first metal layer 13. Although there is no specific information available regarding a relationship of wi to w2 of this related method, based on their understanding of this related method resulting in the structure shown in Fig. JC the inventors of the invention described and claimed in the present application assume that the width difference wl-w2 between the first and second metal layers 13 and patterned 19 as a,,,;id.-.h w2 layer 13. 19 is 17 is larger than or equal to 4 gm, that is, wl-w2 2: 4 gm.
Ref-erring to FIG.!D, a first insulating!aver 23 -Js formed by _depositing S4'4COn Oxide 5'()2 or silicon nitride Si3N4 as a single- layered or double-lavered structure on the gate 21 and substrate!l. Semiconductor and ohmic contact layers 25 and 27 are for-med by sequencially depositing undoped polvc--ys--ail-Jne silicon and heavily doped silicon on the first insulating layer 23. The semi-conductor and ohmic contact layers 25 and 27 are patterned to expose the first insulating layer 23 by photolithography.
Referr-ing to FIG.!E, conductive metal such as aluminum is laminated on the insulating and ohmic contact layers 23 and 27. The conductive metal is patterned by photo! ithography so as to form a source electrode 29 and a drain electrode 31. A portion of the ohmic contact layer drain electrodes 29 and 31 drain electrodes 29 and 31 as masks.
Referring to FTG. 1--, silicon oxide or silicon nitride is dec)osited on the entire surface of the structure to form, a second insulating layer 33. The second insulating layer 33 is etched to expose a designated portion of the drain electrode 31, thus form-ing a contact hole 35. By depositing transparent and 27 exposed between the source and is etched by using the source and 6 conductive material on the second insulating layer 33 and patterning it- via photol ithography, a pixell electrode 37 is c so as to be e'.eczr-ically connected to the drain electrode 31 through the contact hole 35.
Accordina to the method of -fabricat"g a thin-film transistor as described above and shown in Figs. LP-L-1.71 respective first and second metal layers are formed through photo! ithography using different masks so as to form the gate with a double-laye-ed metal structure, resulting in double step differences between the gate and substrate.
As a result of the double step difference between the gate 21 and the substrate 11 shown in Fig. 1C, a hillock often occurs on both side portions of the first metal layer!3 which have no oortion of the second metal layer 17 deposited therean when the c first metal layer 13 is wide.r than the second metal layer 17 as in Fig. IC. Anothe_r problem with this related method is that the process for forming a wate is complex and requires two photoresists 15, 19 and two steps of deposition and photolithography. As a result, the contact resistance between the first and second metal layers may be increased.
Another method of forminS a double metal layer gate 7 st:ructure is described in "Low Cost, High Quality TFT= Process", SOCI-EM7Y FOR -7'-.\-F^JRYL:T7-ON D7SP7JS EUIR.0 DISPLAY 96, Proceedings of the 10'h international- Dsi,,lav Research Conference, B- irm-inc-ha,-n,, England, October 1, 1996, pages 591-59-1. On nage 592 of thIs publication, a method of forming a double metal gate structure includes the process of depositing two metal layers f-irst and then patterning the two metal layers--to thereby eliminate an additional photoresist step. However, with this method, process difficulties during the one step photoresist process for 'Lorm.ing-the double metal layer gate resulted in the tor) layer being wider than the bottom layer causing an overhang condition in which- the ton layer overhangs the bottom layer. This difficulty may result in poor step coverage and disconnection. This problem was solved by using a three-step etching process in which the photoresist had to be baked before each of the three etching steps to avoid lift-off or removal of the photoresist during etching. This three- ster) etching process and required baking of the photoresist significantly increases the complexity and steps of the gate forming method.
1 8 To overcome embodiments the problems discussed above, the preferred of the present invention provide a thin-film transistor which prevents a hillock and deterioration of step coverage of a later formed gate oxide layer on a double metal layer late.
The preferred embodiments of the present invention also provide a method of fabricating a thin-film transistor that simplifies the process for forming a double metal layer gate.
The preferred embodiments of the present invention further provide a method of fabricating a thinfilm transistor that reduces the contact resistance between the first and second metal layers constituting a gate.
Additional features and set forth in the description apparent:"from the description, the invention. Che obiectives advantales of the invention will be which follows, and in part will be or may be learned by practice of and other advantages of the. attained by the structure written descrintion and claims invention will be realized and particularly pointed out in the hereof, as well as, the appended drawings.
To achieve these and other advantages and in accordance with 9 the purpose of nhe preferred ehoodiments of the present invencion, as embodied and broadly described, a thin-film transistor cre-ferably comprises a substrate, and a gate including a double-layered structure of first and second.metal layers disnosed an the substrate, the first metal layer being wider than the second metal layer by about 1 to 4 gm, and a method of making such a thin-film transistor preferably comprises the steps of: depositing a first metal layer on a substrate, depositing a second metal layer directly on the first metal layer; forming a photoresist having a desixed width on the second metal layer; patterning the second metal layer via an isotropic etching using the photoresist ds a mask; patterning the first metal layer via an anisocropic etching using the photoresist as a mask, the first metal layer being etched to have a desired width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
For a better understanding of the present invention, embodiments will now be described by way of example, with reference to the accompanying drawings, in which:
FIGS. M through 1F are diagrams illustrating a process for fabricating a Chinfilm transistor according to a method which is related to the embcdiments of the present invention; FIG. 2 is a top view of a thin-film transistor according to a preferred embodiment of the present invention; FIG. 3 is a crOss-sectional view taken along line X-X of FIG. 2; and FIGS. 4A through 4F are diagrams illustrating a process for fabricating a thin-film transistor of preferred embodiments of the present invention.
11 FIC, 2 is a toe view of a thin-film transistor according to a mre-ferred embodiment ofF the cresent invention. FIG. 3 is a cross-sectional view allong line x-x of FIG. 2.
The tra-sistor comwises a gate 49 having a double-lavered structure of a first metal!aye-- 43, a second .. eta! layer 45 disposed on a substrate 41, a first insulating layer 51, a second layer 61, a semiconductor layer 53, an chmic contact layer 55, a source electrode 57, a drain electrode 59, and a pixel electrode 65.
The gate 49 has a double-layered structure including the and second metal layers 43 and 45 dlsposed on the substrate,-1. The first metal layer 43 is preferably formed from a ccnductive metal such as A!, Cu, or Au deposited to have a certain width wl. The second metal layer 45 is preferably formed from a refractory metal such as Mo, Ta, or Co deposited to have a certain width w2.
The present inventors have discovered that: a relationship between the width of the first metal layer and the width of the second metal layer of a double metal layer gate electrode is critical to mreventing deterioration of step coverage of a later 12 tormed gate oxide layer in such a structure having a double s d-1,-10. 1erence betwee-r the substrate and the c-ate. More snecifically, the present inventors determined that a structure wherein the -'irs metal!aye- - 43 is wider than the second metallayer 45 by about 1 to 4 gm, for example, 1 um < wl-w2 < 4 gm, provides maximum prevention of deterioration of step coverage of a later formed aate oxide layer in such a structure having a double steo difference between the substrate and the cate.
To achieve the best results, the second metal layer 45 is preferably positioned substantially in the middle of the first metal, layer 45, so that both side po.-y-t-ions of the first metal layer 43 which have no portion of the second metal layer 45 disposed thereon have substantially the same w-.'dth as each other. The width of each of the side portions is preferably larger than about 0.5 gm but less than about, 2 gm.
The first insulating layer S! is preferably formed by. depositing single layer of silicon oxide S02 or silicon nitride Sj ' on the substrate including the gate 419. 3 "J4 The semi-conductor and ohmic contact layers 53 and 55 are for- J_ I- med on the portion of the first insulating layer 51 corresnondr-a to the cate 49 by sequentially depositinST undoped t ep 1 1 13 amorphous silicon and heavily doped amorphous silicon and patterning the two silicon layers. The semicond.-ctor layer 53 s used as the active region of an element, thus formling a channel by means of a voltage applied to the gate 49. The ohmic contact layer 55 provides an ohmic contact between the sem-Lconductor,aver 53 and the source and drain electrodes 57 and 59. The ohmic contact layer 55 is not formed in the portion that becomes the channel of the semiconductor layer 53.
The source and drain electrodes 57 and 59 are in contact with the ohmic contact layer 55, and each electrode 57, 59 extends to a designated portion on -the first insulating-layer 51.
The second insulating layer 61 is formed by depositing J-sulat-4.-9 material such as silicon oxide 5i02 silicon nitride 5j 3N4 to cover the source and drain electrodes 57 and 59 and the first insulating layer 51. The second insulating layer 61 on the drain electrode 59 is removed to form a contact ho-le 63. The pixel electrode 65 is formed from trans arent and conductive p material such as ITO (Indium Tin Oxide) or Tin oxide Sn02, SO that it is connected to the drain electrode 59 through the contact hole 63.
In the first and second metal layers 43 and 45 constituting 14 the gate 49, each side nortion of the LO-J--st-- metal layer 43 having no portion of the second metal layer 45 Lhereon has a width that is preferably larger than about 0.5 Am and less than about 2 Because the first metal layer 43 is wider than the second metal layer 45 by about i.0 Am to 4.0 gm, double step differences determined according to the relationship between the width of the first: metal layer and the width of the second metal layer are formed between the Sate 49 and substrate 41. The double step differences determined accordilng to the novel features c- Lc the preferred e-.,Loodiments of the present invention prevent (or reduce) deterioration of the coverage of the first insulating layer 51 which deterioration occurs in prior art devices. The hilicck -ithe first metal layer 43 is also avoidable because the width difference between the first and second metal!avers 43 and 45 1's between about 1 gm to 4 gm.
FIGS. 4A through 4F are diagrams illustrating the process for fabricating the thin-film transistor of the preferred embed-Lments of the present invention.
ReferrinS to FIG. 4A, metal such as Al, Cu, or Au is demosited on a substrate so as to form a first metal layer 43. A second metal!ayer 45 is formed from Mo, Ta, or Co and denosited on the metal!aver 43 without performing a masking step between the stem cl' depes'ting the metal layer and the seo o-f de-oosi4Li,-4a the second metal layer. 7711--- first and second metal layers 43 and 45 are sec-uen---'a-lly deposited so as to preferably have a thickness as larce as about 500-4000A and 500-2000A, resnectivelv, by means of sputterina or chemical vapor deposition (here inafter, referred to as CVD) without breaking a vacuum staUe. As a result, the contact resistance between the first and second metal layers 43 and 45 is reduced.
According to the preferred embodiments of-the present invention, a single phocaresist step is used to pattern both the first metal layer 43 and the second metal layer 45 simultaneously. in the single photoresist stem, a photoresist 47 is deposited on the second metal layer 45 and then the photoresis-k- 47 is patterned through exposure and development to have the width wl- on a designated portion of the second metal layer 45.
Referring to FIG. 43, the second metal layer 45 is patterned with an etching solution preferably prepared with a mixture of phosphoric acid F3P04, acetic acid CF3COOH and nitric acid F-N03, by means of a wet etching using 'the photoresist 47 as a mask.
16 metal layer 43, that is, about u m < w 1 - w 2 < 4 creferably has a larzer than a--ou: 0.5 g-,n and less than about 2 gm. That is, two side mortions OLE the second metal laver 45 cc-iered with the phocoresist 47 are preferably etched to have substantially the same width as each other.
The lateral surfaces of the second metal layer 45 are preferably etched 'to have a substantially rectangular or inclined shape.
Refe=ing to FIG. 4C, the -first metal layer 43 is patte_-:1_ed via a dryetching having anisOtrOPic etching characteristic such as reactive ion etching (hereinafter, referred to as RIE) by using the photcres-ist 47 as a mask. Wher. etching the L'-'irst metal layer 43 other than the portion of the layer 43 covered with the Photores-ist 47, the first metal layer 43 preferably has the same width wi of the photores-iSt: 47. Thus, patterning of the first and second metal layers 43, 45, respectively, only reauires two 17 etching ste-ps and does not require baking cZE "-he nhotores-isL be-fore each step of etching. Also, the relation between the firs- and second metal layers 43 and 45 also may be represented by about 1 gm < wl-w2 < 4 um.
The first and second metal layers 43 and 45 -resulting from the single photoresist step process described above f-orm, a gate 49 having a doublelayered metal structure. The gate 4-9 has the second metal layer 115 positioned substantially in the middle of the first metal 'Layer 43 so that the each side portion of the first metal layer 43 having no second metal layer 45 _thereon is wider than about 0.5 gm but narrower than about 2 im. The chotoresist 47 remaining on the second metal layer 45 is removed af-er the two etching steps are completed.
Referring to FIG. 4D, a first insulating layer 51 is formed by depositing a single layer or. double layers of silicon oxide 5i02 or silicon nitride Si3N4 on the gate 49 and substrate 41 by CVD. Because each side portion of the first metal layer 43 having no second metal layer 45 thereon is wider than about 0.5 gm, double step differences formed between the substrate and gate can urevent the coverage of the first insulating layer 51 from being deteriorated as in prior art devices. The hillock in the first
18 "I meta. layer 43 is also avoidable because a width of a portion of the first metal layer 43 which is exposed is less than about 2 M-m.
A-,norz)hous si-licon wn-ich is undoped and heavily doped amor-chous silicon are sequencially deposited on the.1=irst insulating layer contact layers 53 layers 55 and 53 ex.nese the fIrst 41 by CVD, thus forming semiconductor and ohmic and. 55. The ohmic contact and semiconductor are patterned by means of photolithography to insulating layer 51- Referrina to FIG. 4E, conductive metal such as Al or er is laminated an the insulating and ohmic contact layers 51 and 55 and patterned by photo! ithography to form source and drain electrodes 57 and 59. The ohmic contact layer 55 exposed betweenthe source and drain electrodes 57 and 59 is etched by using the source drain electrodes 57 and 59 as masks.
Referring to FIG. 4F, a second insulating layer 61 is formed by depositing insulating material such as silicon oxide or silicon nitride by CVD on the entire surface of the abovestructure. The second insulating layer is removed by photolithography to expose a designated portion of the drain electrode 59 and thus form a contact hole 63. Once transparent 19 and conductive material such as!TO (Indium Tin Oxide) or Tin oxide Sn02 is deposited on the second insulating layer 61 via spucterinS and patterned by photo li thography, a pixel electrode 65 is formed so that it is electrically connected to the drain electrode 59 through t.he contact hole 63.
In another preferred embodiment of the present invention, the first and second metal layers 43 and 45 are first etched by a dry etching having anisotropic etching cl-a-acterJstic means of such as RIE by using the photo-resist 47 as a mask. The gate 49 is formed by etching the second metal layer 45 under the - photoresist 47 with an etching solution prepared with a mixture of phosphoric acid H3P01, acetic acid CH3COOH and nitric acid 3 - In still another zreferred embodiment of the present invention, the gate 49 is formed through a single etch-ing step process for etching the first and second metal layers 43 and 45 simultaneously and by a single etching step, where the second metal layer 45 is etched more quickly than the first metal layer 43 with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH3COCH and nitric acid R-IN-03. Because of the etch-Ing material and metals used for the first and second metal layers of the gate, only a single etching step is required. Despite the fact that a single etching step is used, it is still possible to obtain the relationship between the widths wi and M of. the first and second metal layers described above. ' in this process, the first and second metal layers forming the gate 49 are formed and patterned with a single photo resist step as described above and a single etching step.
As described above, in the preferred embodiments of the present invention, the first and second metal layers are sequentially deposited on the substrate without performing a masking step between the step of depositing the first metal layer and the second metal layer, followed by forming a photoresist that covers a designated portion of the second metal layer. in one preferred embodiment, the second metal layer is wet etched by using the photoresist is a mask but the first metal layer is dry etched. As a result, the double-metal gate is formed. In another preferred embodiment, a single etching step is used to form the double- metal gate wherein both the first metal layer and the second metal layer are wet etched, but the different in etching rates of the first and second metal layers produces different etching affects which result in the desired double-step 1 21 structure.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
The present application is a divisional application, related to parent United Kingdom patent application number 9804417.5. The parent application as originally filed included the following claims, which are not claims of the present application, but the subject matter of which is relevant to the present divisional application:
A thin-film transistor comprising:
a substrates; and a gate including a double-layered structure having a first metal layer and a second metal layer disposed on the substrate, the first metal layer being wider than the second metal layer by substantially 1 to 4 lim.
2. The thin-film transistor as claimed in claim 1, wherein the second metal layer is located in a middle portion of the first metal layer so that two side portions of the first metal layer having no second metal layer disposed thereon have the same width as each other.
22 3. The thin-film transistor as claimed in claim 1 or 2, wherein the first metal layer includes at least one of Al, Cu, and Au.
4. The thin-film transistor as claimed in claim 1, 2 or 3, wherein the second metal layer includes at least one of Mo, Ta, and Co.
5. A thin-film transistor comprising: a substrates; a gate including a double-layered structure having a first metal layer and a second metal layer disposed on the substrate, the first metal layer being wider than the second metal layer by substantially 1 to 4 pm; a first insulating layer disposed on the substrate including the gate; a semiconductor layer disposed on a portion of the insulating layer at a location corresponding to the gate; an ohmic contact layer disposed on two sides of the semiconductor layer; a source electrode and a drain electrode disposed on the ohmic contact layer and extending onto the first insulating layer; and a second insulating layer covering the semiconductor layer, the source and drain electrodes and the first insulating layer.
6. The thin-film transistor as claimed in claim 5, wherein the second metal layer is located in a middle portion of the first metal layer so that two side 23 portions of the first metal layer having no second metal layer thereon have the same width as each other.
7. The thin-film transistor as claimed in claim 5 or 6, wherein the first metal layer includes at least one of Al, Cu, and Au.
8. The thin-film transistor as claimed in claim 5, 6 or 7, wherein the second metal layer includes at least one of Mo, Ta, and Co.
24 CIaims:
1. A method of making a thin-film transistor, comprising the steps of: depositing a first metal layer on a substrate; depositing a second metal layer on the first metal layer directly after the step of depositing the first metal layer; forming a single photoresist having a predetermined width on the second metal layer; patterning the second metal layer using the single photoresist as a mask; patterning the first metal layer using the photoresist as a mask, the first metal layer being etched to have a width greater than a width of the second metal layer thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist; wherein the steps of patterning the second metal layer and the first metal layer each comprise a single etching step.
2. The method of making a thin-film transistor as claimed in claim 1, wherein the step of patterning the second metal layer includes the step of isotropic etching using the single photoresist and the step of patterning the first metal layer includes the step of anisotropic etching using the single photoresist as a mask, the second metal layer being etched to be wider than the photoresist by about 1 to 4 m.
3. The method of making a thin-film transistor as claimed in claim 1 or 2, further comprising the steps of: forming a first insulating layer on the substrate including the gate; forming a semiconductor layer and an ohmic contact layer on a portion of the first insulating layer at a location corresponding to the gate; forming a source electrode and a drain electrode extending onto the first insulating layer on two sides of the ohmic contact layer, and removing a portion of the ohmic contact layer exposed between the source and drain electrodes; and forming a second insulating layer covering the semiconductor layer, the source electrode, the drain electrode and the first insulating layer.
4. The method of making a thin-film transistor as claimed in claim 1, 2 or 3, wherein the first and second metal layers are sequentially deposited via sputtering or chemical vapour deposition method without breaking a vacuum state.
5. The mefhod of making a thin-film transistor as claimed in claim 1, 2, 3 or 4, wherein the first metal layer includes Al, Cu or Au.
6. The method of making a thin-film transistor as claimed in claim 1, 2,3, 4 or 5, wherein the first f 26 metal layer has a thickness of substantially 500 to 4000 A.
7. The method of making a thin-film transistor as claimed in any one of claims 1 to 6, wherein the second metal layer includes Mo, Ta or Co.
8. The method of fabricating a thin-film transistor as claimed in any one of claim 1 to 7, wherein the second metal layer has a thickness of substantially 500 to 2000 A.
9. The method of making a thin-film transistor as claimed in any one of claims 1 to 8, wherein the second metal layer is etched with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH3COOH and nitric acid HN03.
10. The method of making a thin-film transistor as claimed in any one of claims 1 to 9, wherein the f irst metal layer is removed via a dry etching process.
11. The method of making a thin-film transistor as claimed in any one of claims 1 to 10, wherein two side portions of the first metal layer having no second metal layer deposited thereon have substantially the same width as each other.
12. A method of making a thin-film transistor, comprising the steps of: depositing a first metal layer on a substrate; 27 depositing a second metal layer on the first metal layer without forming a photoresist on the first metal layer beforehand; forming a photoresist having a predetermined width on the second metal layer; anisotropically etching the first and second metal layers such that the first metal layer and the second metal layer have the same width of the photoresist by using the photoresist as a mask; isotropically etching the second metal layer such that the second metal layer is narrower than the first metal layer by about 1 to 4 pm using the photoresist as a mask, thus forming a gate having a double-layered structure including the first and second metal layers; and removing the photoresist.
13. The method of making a thin-film transistor as claimed in claim 12, further comprising the steps of: forming a first insulating layer on the substrate including the gate; forming a semiconductor layer and an ohmic contact layer on a portion of the first insulating layer at a location corresponding to the gate; forming a source electrode and drain electrode extending onto the first insulating layer on two sides of the ohmic contact layer, and removing a portion of the ohmic contact layer exposed between the source and drain electrodes; and 28 forming a second insulating layer covering the semiconductor layer, the source electrode, the drain electrode and the first insulating layer.
14. The method of making a thin-film transistor as claimed in claim 12 or 13, wherein the first metal layer includes Al, Cu or Au.
15. The method of making a thin-film transistor as claimed in claim 12, 13 or 14, wherein the second metal layer includes Mo, Ta or Co.
16. The method of making a thin-film transistor as claimed in claim 12, 13, 14 or 15, wherein the first and second metal layers are removed by a dry etching method.
17. The method of making a thin-film transistor as claimed in claim 12, 13, 14, 15 or 16, wherein the second metal layer is etched with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH3COOH and nitric acid HN03.
18. A method of making a thin-film transistor, comprising the steps of: depositing a first metal layer on a substrate; depositing a second metal layer on the first metal layer without forming a photoresist on the first metal layer beforehand; forming a single photoresist having a predetermined width on the second metal layer; 29 patterning the first and second metal layers simultaneously in a single etching step using the single photoresist as a mask; and removing the photoresist.
19. The method of making a thin-film transistor as claimed in claim 18, wherein the second metal layer is etched to be wider than the first metal layer by about 1 to 4 lim.
20. The method of making a thin-film transistor as claimed in claim 18 or 19, further comprising the steps of: forming a first insulating layer on the substrate including the gate; forming a semiconductor layer and an ohmic contact layer on a portion of the first insulating layer at a location corresponding to the gate; forming a source electrode and a drain electrode extending onto the first insulating layer on two sides of the ohmic contact layer, and removing a portion of the ohmic contact layer exposed between the source and the drain electrodes; and forming a second insulating layer covering the semiconductor layer, the source electrode, the drain electrode and the first insulating layer.
21. The method of making a thin-film transistor as claimed in claim 18, 19 or 20, wherein the first and second metal layers are sequentially deposited via sputtering or chemical vapour deposition method without breaking a vacuum state.
22. The method of making a thinfilm transistor as claimed in claim 18, 19, 20 or 21, wherein the first metal layer includes Al, Cu or Au.
23. The method of making a thin-film transistor as claimed in claim 18, 19, 20, 21, or 22, wherein the first metal layer has a thickness of substantially 500 to 2ooo A.
24. The method of making a thin-film transistor as claimed in any one of claims 18 to 23, wherein the second metal layer includes Mo, Ta or Co.
25. The method of making a thin-film transistor as claimed in any one of claims 18 to 24, wherein the first metal layer has a thickness of substantially 500 to 2ooo A.
26. The method of making a thin-film transistor as claimed in any one of claims 18 to 251 wherein the second metal layer is etched with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH3COOH and nitric acid HN03.
27. The method of making a thin-film transistor as claimed in any one of claims 18 to 26, wherein the first metal layer is removed via a dry etching process.
31 28. The method of making a thin-film transistor as claimed in any one of claims 18 to 27, wherein two side portions of the first metal layer having no second metal layer deposited thereon have substantially the same width as each other.
29. A method of making a thin-film transistor substantially as hereinbefore described with reference to and/or as illustrated in FIGS. 2 to 4F of the accompanying drawings.
32- Amendments to the claims have beenfiled as follows 1. A method of making a thin-film transistor. comprising the steps of:
depositing a first metal layer on a substrate; depositing a second metal layer on the first metal layer without forming a photoresist on the first metal layer beforehand; forming a single photoresist having a predetermined width on the second metal layer; patterning the first and second metal layers simultaneously in a single etching step using the single photoresist as a mask; and removing the photoresist.
2. The method of making a thin-film transistor as claimed in claim 1, wherein the second metal layer is etched to be wider than the first metal layer by 1 to 4 im.
3. The method of making a thin-film transistor as claimed in claim 1 or 2, further comprising the steps of:
forming a first insulating layer on the substrate including the gate; forming a semiconductor layer and an ohmic contact layer on a portion of the first insulating layer at a location corresponding to the gate; forming a source electrode and a drain electrode extending onto the first insulating layer on two sides of the ohmic contact layer, and removing a portion of the ohmic contact layer exposed between the source and the drain electrodes; and forming a second insulating layer covering the semiconductor layer, the source electrode, the drain electrode and the first insulating layer.
4. The method of making a thin-film transistor as claimed in claim 1, 2 or 3, wherein the first and second metal layers are sequentially deposited via sputtering or chemical vapour deposition method without breaking a vacuum state.
5. The method of making a thin-film transistor as claimed in claim 1, 2, 3 or 4, wherein the first metal layer includes Al, Cu or Au.
6. The method of making a thin-film transistor as claimed in claim 1, 2, 3, 4, or 5, wherein the first metal layer has a thickness of substantially 500 to 4000 A.
7. The method of making a thin-film transistor as claimed in any one of claims 1 to 6, wherein the second metal layer includes Mo, Ta or Co.
8. The method of 'making a thin-film transistor as claimed in any one of claims 1 to 7, wherein the second metal layer has a thickness of substantially 500 to 2000 A.
9. The method of making a thin-film transistor as claimed in any one of claims 1 to 8, wherein the first metal layer and the second metal layer are etched with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH3COOH and nitric acid HN03.
10. The method of making a thin-film transistor as claimed in any one of claims 1 to 9, wherein two side portions of the first metal layer having no second metal layer deposited thereon have substantially the same width as each other.
11. A method of making a thin-film transistor substantially as hereinbefore described with reference to and/or as illustrated in FIGS. 2 to 4F of the accompanying drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970007010A KR100248123B1 (en) | 1997-03-04 | 1997-03-04 | Thin-film transistor and method for manufacturing thereof |
| GB9804417A GB2322968B (en) | 1997-03-04 | 1998-03-02 | Thin-film transistor and method of making same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9905015D0 GB9905015D0 (en) | 1999-04-28 |
| GB2338105A true GB2338105A (en) | 1999-12-08 |
| GB2338105B GB2338105B (en) | 2000-04-12 |
Family
ID=26313208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9905015A Expired - Lifetime GB2338105B (en) | 1997-03-04 | 1998-03-02 | Method of making a thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2338105B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4220706A (en) * | 1978-05-10 | 1980-09-02 | Rca Corporation | Etchant solution containing HF-HnO3 -H2 SO4 -H2 O2 |
| EP0301571A2 (en) * | 1987-07-30 | 1989-02-01 | Sharp Kabushiki Kaisha | Thin film transistor array |
| JPH01222448A (en) * | 1988-03-01 | 1989-09-05 | Nec Corp | Manufacture of semiconductor device |
| WO1992006504A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| GB2253742A (en) * | 1990-10-05 | 1992-09-16 | Gen Electric | Device self-alignment by propagation of a reference structure's topography |
| GB2254187A (en) * | 1990-10-05 | 1992-09-30 | Gen Electric | Positive control of the source/drain-gate overlap in self-aligned tfts via a top hat gate electrode configuration |
| EP0602315A2 (en) * | 1992-12-16 | 1994-06-22 | Matsushita Electric Industrial Co., Ltd. | Method of making thin film transistors |
| GB2307597A (en) * | 1995-11-21 | 1997-05-28 | Lg Electronics Inc | Controlling the generation of hillocks in liquid crystal devices |
| EP0812012A1 (en) * | 1996-06-07 | 1997-12-10 | Lucent Technologies Inc. | Method for etching to produce metal film structures having tapered sidewalls |
-
1998
- 1998-03-02 GB GB9905015A patent/GB2338105B/en not_active Expired - Lifetime
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4220706A (en) * | 1978-05-10 | 1980-09-02 | Rca Corporation | Etchant solution containing HF-HnO3 -H2 SO4 -H2 O2 |
| EP0301571A2 (en) * | 1987-07-30 | 1989-02-01 | Sharp Kabushiki Kaisha | Thin film transistor array |
| JPH01222448A (en) * | 1988-03-01 | 1989-09-05 | Nec Corp | Manufacture of semiconductor device |
| WO1992006504A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| GB2253742A (en) * | 1990-10-05 | 1992-09-16 | Gen Electric | Device self-alignment by propagation of a reference structure's topography |
| GB2254187A (en) * | 1990-10-05 | 1992-09-30 | Gen Electric | Positive control of the source/drain-gate overlap in self-aligned tfts via a top hat gate electrode configuration |
| EP0602315A2 (en) * | 1992-12-16 | 1994-06-22 | Matsushita Electric Industrial Co., Ltd. | Method of making thin film transistors |
| GB2307597A (en) * | 1995-11-21 | 1997-05-28 | Lg Electronics Inc | Controlling the generation of hillocks in liquid crystal devices |
| EP0812012A1 (en) * | 1996-06-07 | 1997-12-10 | Lucent Technologies Inc. | Method for etching to produce metal film structures having tapered sidewalls |
Non-Patent Citations (1)
| Title |
|---|
| Patent Abstracts of Japan, Vol 13, No 541 [E-854] 7 JP-A-1 222 448 * |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9905015D0 (en) | 1999-04-28 |
| GB2338105B (en) | 2000-04-12 |
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| COOA | Change in applicant's name or ownership of the application | ||
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Expiry date: 20180301 |