JPS5873132A - Semiconductor device using polyimide for isolating insulation and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor@1 and a method for manufacturing a semiconductor device. The present invention relates to a semiconductor device and a method of manufacturing the same that can provide improved electrical connections between adjacent components.

Numerous methods have been proposed for electrically isolating multiple pockets of semiconductor material, each of which can form 111 or more circuit elements. (U.S. Pat. No. 3,117,260 to Noyce, issued January 7, 1964) using a biased PN junction, using a combination of a PN junction and regions of intrinsic and non-intrinsic semiconductor material; Things (1)
Noyce U.S. Patent No. 3, issued September 22, 964,
150,299), those using insulation isolation (No. 196
Frescura U.S. Patent No. 3, issued July 2, 1988.
, No. 391, 023), and those using mesa etching (I'eSCura, published January 13, 1970).
U.S. Special FF No. 3,489,961). 1
7 ucker and 3 issued on May 29, 913
U.S. Pat. No. 3,736,193 to Arry discloses the concept of using selectively doped polysilicon to separate islands of single crystal silicon from which circuit elements can be formed. ing.

After forming a pocket of electrically isolated semiconductor material, active circuitry and passive circuitry may be placed in and on the pocket using techniques well known in the semiconductor art.
! form a cord. Such techniques include, for example, Hoern
i U.S. Patents 3,025,589Q and 3,064
, 16'7@. After forming the desired circuit elements in the semiconductor material in this manner, a conductive lead pattern is formed on the insulating layer and the selected active and passive circuit elements are interconnected to form the desired circuit. ing. It is noted that additional passive circuit elements can be formed on the insulating layer and interconnected to the circuit. Such techniques are described, for example, in No.
yce, US Pat. No. 2,981,877.

Several problems exist when manufacturing integrated circuits. First, the wafer area required to provide isolation regions between adjacent pockets of semiconductor material occupies a significant portion of the total wafer area. Large isolation areas reduce the number of devices that can be placed within a wafer, reducing the "integration" of circuit elements formed on the wafer. Second, if the leads are formed on the insulating layer on the wafer, cracks may occur on the surface of the wafer or at the steps existing in the insulating layer of F. Such steps are often steep. Third, some isolation techniques introduce significant parasitics into the integrated circuits being constructed. At low frequencies, capacitances introduced in this way do not significantly affect circuit operation, but at high frequencies, such capacitances can significantly affect circuit performance. There is. Fourth, the separation techniques used in the manufacture of conventional integrated circuits require relatively high concentrations, thus displacing the PN junctions formed in previous steps; Therefore, the accuracy in measuring the characteristics of the semiconductor device finally constructed is reduced. As semiconductor devices become smaller and smaller, this excellent effect becomes even more important.

No. 3,404,451, issued October 8, 1968, to J.J.So.
＠ proposes to remove such portions of the insulating layer from the surface of T during the manufacturing process. A technique has also been proposed in which the edge of the I8 edge cover of the contact window is sloped. As a gastric method, “Local oxidation of silicon and its application to semiconductor device technology (L0cat Q
X1d2tj01 or 5i1icOIl
an,j ijs AppliCajiOI+
ir+ Sea+1conductor-D ev
philips research report 25. 118
Page (1970), J.A., ApDθIS, et al., there is a technique disclosed in the literature, in which a groove is etched in the semiconductor wafer adjacent to the #4 area where the PN junction is to be formed. Then, there is b.

The material exposed by these grooves is then thermally saponified. If the process is properly controlled, the oxide surface and the semiconductor material surface will lie approximately on the same plane.

As highlighted by Appels et al., an additional advantage of this method is that the portion of the semiconductor wafer into which the impurity is diffused is obsolete if it has a mesa-like shape. The resulting PN base-]rector junction is substantially planar and has a higher breakdown voltage than a dish-type PN junction, but is still susceptible to oxidation for pansivation, as in the Brehner process. Something that comes into contact with things.

Yet another method was published on March 7, 1971.
ltZ13r, US Pat. No. 3,648.125. The PE+TZER patent involves forming a thin silicon epitaxial layer on a silicon substrate and adding an oxide region (
These oxidized regions extend laterally through the taxial layer. PN junction for separation (11 PN junction)
It is formed by oxidation until it reaches (called ). Therefore, each silicon pocket has a separate P
It is separated by a part of the N junction and the oxidized part of the Ill region. Each such pocket can be formed with active devices, passive devices, or both. A low resistance cross-under region is formed in the substrate and at least one oxide lI! It is possible to interconnect regions that are separated by I@ areas.

■ The upper surface of the bitaxial layer and the upper surface of the oxidized isolation region are substantially in the same plane, thus creating an undesirable height change between the isolation oxide and the rest of the wafer surface, i.e. This reduces the occurrence of "level differences".

In order to form isolated pockets of epitaxial silicon, in the Peltzer patent, a trench is formed in the silicon to a depth of about 50% of the depth of the oxidized isolation region. (also known as a place). Note that when forming the groove, the remainder of the silicon surface on which the active device is to be formed is covered with an insulating layer (e.g., silicon nitride) that is not substantially affected by the silicon etching agent used to form the groove. Protecting.

The epitaxial silicon exposed by forming the trench is then oxidized down to the underlying isolating PN junction, thus making it possible to isolate the silicon portions in which the active device is to be formed.

All of these isolation techniques consume a significant portion of the semiconductor material area and/or involve forming one or more PN junctions within the device followed by a 14 concentration process. When high temperatures are used, the position of the PN junction shifts, reducing the accuracy in predicting the characteristics of the final device. -This is not desirable, especially in very large scale integrated circuits (VLSI).

Other references regarding the use of polyimide in semiconductor devices include L, B, R0Lbian.
“Properties of polyimide lIM (prope
rties or Tt+In Po1yiii
de F 11m5)”, Journal of the Electrochemical Society: Solid-State Science Ant Chic/cl>-, Vol.
127. No. 10゜October 1980,
2216-2220 and contributions from S. J. and Rhode S. “Multilayer metallization technique #I for ultra-LSI high-speed bipolar circuits (Mt1 day 11 ayer Met
Alization Techniques f
or V L S IHIgh Speed
31polar C1rcuits)”, Semiconductor International, March 1981.

Pages 65-70 and contributions from 3.3aiki et al. ゛2-
A new transistor with level metal electrodes (A'
New Transistor with T'
wo-LeVelMetal E Ielectrode
s), published by Hitachi Kasuzakusho Central Technical Research Laboratory, and Polyimide COatrnQS, published by IllVt Education in Engineering, University of California, Berkeley. for
Microelectronlcs with A
Applications), August 1981, 4-5. Valo Alto, California, et al.

The present invention has been made in view of the above points, and provides an improved technique capable of isolating pockets of semiconductor material within an integrated circuit from a viewpoint different from the prior art as described above. The purpose is to provide. That is, there are many benefits (lower cost) by eliminating one or more high temperature processing steps.

The present invention utilizes a relatively low-temperature process to form isolated pockets of semiconductor material within an integrated circuit, resulting in more accurately predictable device characteristics (e.g., device characteristics). ing.

According to the present invention, a trench formed in a semiconductor layer made of a semiconductor material is filled with polyimide to provide electrical isolation between adjacent devices in a semiconductor device formed from the semiconductor material, and a polyimide is applied to the top surface. It is possible to provide a substantially planar surface for the conductive interconnects to be formed. These grooves are formed, preferably by etching, in the depth direction of the layer of semiconductor material. If the semiconductor device has an epitaxial silicon layer formed on a silicon substrate, this groove is formed straight through the epitaxial layer until it reaches the silicon substrate located below. When the semiconductor material is silicon,
Oxidizing the surface of the etch removal and the surface of the semiconductor material layer to provide electrical isolation between the various semiconductor regions exposed by the etch removal and to provide good adhesion to polyramide chips. . The oxidized etched areas are then filled with polyimide to create an extremely smooth device surface. Therefore.

llA for electrical connection is placed on a smooth device surface with no steep steps even above the etching removal area for separation.
t8! It becomes possible to form i.

Although polyimide itself is conventionally known and is described, for example, in U.S. Pat. No. 4,273,886, the use of polyimide in the present invention provides several unique effects. is possible.

For example, since polyimide is deposited at a relatively low temperature, it is possible to more accurately predict the position of the PN junction, and it is possible to more accurately predict the device characteristics of the final product. . The soil surface of the polyimide layer is smooth and relatively flat, eliminating abrupt changes in height or "steps" that can cause cracks. The step of depositing jlζ liimide is performed at a relatively high rate of 4J1iff, and thus does not adversely affect yield.

Polyimide is used in many GLs in the manufacture of semiconductor devices. For example, U.S. Patent No. 3,978,
According to No. 578M, polyimide is used for binding a protective film on the upper surface of a semiconductor chip. That is, after maintaining the semiconductor chip within the package and connecting the bonding wires between the semiconductor chip and the external leads, the device and the bonding wires are coated with a second polyimide layer, and the upper surface of the semiconductor chip is coated with the bonding wires. This protects both sides of the bonding wire.

Another way to use polyimide in semiconductor technology is to
U.S. Patent Nos. 3,801,880 and 3,846,16
No. 6, No. 4,001,870, No. 4,040,083
No. 4,060.828, these patents disclose that a first layer of electrical interconnect formed on the surface of a substrate is used to A polyimide layer is used to electrically insulate the second layer for electrical connections formed above the first layer.

It should be noted that none of the references listed above propose the use of polyimide to electrically isolate active regions of semiconductor devices.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows both types of conventional NPN t-transistors.

The NPN transistors 10 & shown in FIG. 1 include P-type 1 & 100 which are silicon in mulberry type but can be composed of other semiconductor materials such as germanium, and N-type buried layer 1O1 which functions as a collector. , N-type epitaxial layer 102, P-type base fi4 region 103, N-type emitter @ra104, and N-type collector contact 10.5.
It has Such bipolar transistors can be constructed using conventional methods, such as those disclosed in U.S. Pat. No. 3,025,589. Bipolar integrated circuits include a plurality of such or similar devices, each typically electrically isolated from adjacent islands of semiconductor material. It is formed within an island of independent semiconductor material.

In one embodiment of the present invention when using a silicon epitaxial layer on a silicon substrate, as shown in FIG. 106(“
Before forming these grooves, active device areas such as the base 103, the transmitter 104, the collector contact 105, etc. are etched using known stamping or hardening techniques. The groove 106 is formed by
Preferably, it is formed by anisotropically etching a silicon wafer having a <100> crystal plane using, for example, KOH as a chemical etchant.

The use of such anisotropic etching to form "V" shaped trenches in silicon layers is described, for example, in U.S. Pat.゛Silicon anisotropic etching
pic Etching of 5ilicon
)”, Journal of Applied Physics, Vol.

40, No, 11. October 1965,
4569-4574 negative literature, and R, M, Fln
“Water-Amine Complexing Agent System for Etching Silicon (A.
Water Am1ne Coiplexin
g A gent Systes
for Etchir+g3111con)
”, Journal of the Electrochemical
Society, Solid State Science, 1
Described in September 967, 965-970 true literature. On the other hand, it is possible to use CF4 plasma etching to form trenches in silicon wafers with crystal planes <100> or <111>. In general, the etched notch resulting from m-reduction need not be "V" shaped, so any technique for forming a separation notch or groove into the epitaxy 1! area 102 can be used. If a separation groove with a shape other than a "v" shape is used, a wider notch will be formed at the base of the full 106, so that it can be used to define the 1106. It is a tool that makes it easy to align masks. Preferably,
Grooves 106 are etched completely through epitaxial layer 102 to form P-type substrate 100, as shown in FIG.
It is said to have a configuration that allows some penetration into the interior. In the completed device, these isolation grooves are used to separate the epitaxial 1110
2 are formed from conductive material to provide electrical isolation between adjacent islands. For example, 106-
1 and 106-3, the base region 10
3. The emitter region 104 and the collector contact 105 are electrically separated from an adjacent device (not shown) formed by being included in another silicon island formed from the epitaxial layer 1027.

Next, the surface of the epitaxial layer 102 exposed by the isolation trench 106 is oxidized to form an insulator 11107. The insulating layer 107 includes the etching notch 106 and insulates the surface of the epitaxial cell layer 102, and therefore stays on the surface of the isolation groove 106 to prevent leakage current from occurring between the semiconductor regions. There is. The insulating layer 107 also connects the epitaxial layer 102 and the first electrical interconnect [119
0 is insulated. The use of oxides on the surface of isolation trenches is known, for example, in U.S. Pat. No. 3,391.0.
It is disclosed on 23@. Insulating layer 107 with oxide
For example, about 850 to 950°C! ! The oxide layer 107 can be formed by thermal oxidation in steam for about 30 minutes at 30°C, resulting in an oxide layer 107 about 300 to 1,000 thick. on the other hand.

Insulating layer 107 may comprise an oxide formed using low pressure CVD techniques to a thickness of about 300 to 1,000 A at a temperature of about 800 to 900°C. Preferably, insulating layer 107 comprises silicon nitride, for example about 8
It can be formed by using low pressure CVD techniques to thicknesses of about 300 to 1,000 nm at temperatures of 0.000 to 900°C. On the other hand, the insulator 11107 may include both an oxide and a nitride.

In the conventional technology of forming silicon nitride on a wafer, an oxide layer 1i is placed between the silicon wafer and silicon nitride.
It was necessary to form 111.

This is because such a configuration alleviates stress that may occur at high temperatures due to the difference in thermal expansion coefficients between silicon and silicon nitride. On the other hand, according to the present invention, the long-term and high-degree thermal oxidation process is eliminated, thus eliminating the need for a stress-relieving oxide layer between the silicon wafer and the silicon nitride. None. Therefore, when silicon nitride is used as the insulating layer 107, the step of forming silicon oxide as an intermediate layer is not necessary, and therefore the stress-relieving oxide layer is removed from the area of the wafer that does not require a stress-relieving oxide layer. There is no need to carry out any process to remove the oxide layer.

Via conductors are then formed through the insulating layer 107 for electrically connecting the underlying regions to the electrical interconnects Ill 90 to be formed later. Through conductors 122 are formed within insulation 11107 using known photolithography and etching techniques. At that time,
A portion of the oxide insulation 11107 is etched away using, for example, HF. Meanwhile, a portion of the insulation 1190 containing nitride is etched away using, for example, CFa plasma.

A first electrical interconnect layer 190 is then deposited on the surface of the wafer.
and patterning to form the desired electrical interconnects. Electrical interconnect layer 190 is typically 11
．． It has polysilicon formed by low pressure CVD technology to a thickness of about 500 to 000 seconds.

Polysilicon layer 190 is then patterned using, for example, known photolithography techniques and etching techniques using CFa plasma. FIG. 2 shows electrical interconnect layer 190 thus patterned in contact with collector contact 105. FIG.

A polyimide layer 108 is then applied over the entire surface of the wafer, approximately 2
It is formed to a thickness of "d", which is a thickness of 4u to 4u. In order to provide good adhesion between the insulating layer 107 and the polyimide layer 108 to be formed thereon, a coating coupler is formed on the surface of the wafer. As a coated coupler, ゛'P sold by Hitachi Co., Ltd.
IQ couplers containing 3°'' are preferred. Approximately 3 to 5 grams of coupler is applied to a 4-inch wafer, and the wafer is then spun for approximately 30 seconds at a rotation speed of approximately 4,000 rpm to form a thin, uniform A layer of coupler is formed. The coupler is then cured by baking the wafer for about 30 minutes in dry air or in a dry atmosphere at a temperature of about 350°C.
A coupler with a thickness of 0.00 to .150 A is formed.

The polyimide material used in the present invention is preferably ``PI013'' polyimide commercially available from Hitachi, Ltd. A 4-inch wafer is coated with about 2 to 6 grams of PIQ13 and the wafer is heated for about 30 seconds. Approximately 3,000
Spin at a rotational speed of 3.500 to 3.500 rρ. This forms a thin, substantially uniform layer of PIQ13 material on the surface of the wafer.

The wafer is then placed in dry nitrogen for about 1 hour at about 100%
Pl, Q1 by baking at a temperature of 200°C and then baking in dry nitrogen for about 1 hour at a temperature of about 200°C.
Harden the three substances. Then, PIQ1 was applied to the surface of the wafer.
A second layer of 3 materials is formed, in this case about 2 to 6 grams of PIQ13 material is applied to the wafer. The wafer is then heated at about 3,000 to 3,500 rpm for about 30 seconds.
and beta the wafer at about 100° C. ms in dry nitrogen for about 1 hour, then at about 1 F.
The second layer of PIQ, 13 material is cured by baking at a temperature of about 200 DEG C. in dry nitrogen for fI and then baking at a temperature of about 350 DEG C. in dry nitrogen for about 1' hour.

This results in a polyimide layer 1 having a thickness of approximately 1.5 to 4p.
08 is formed.

The polyimide layer 108 thus formed adheres well to the couplers (not shown) formed on the insulating layer 107 and is suitable for forming the interconnect lead pattern necessary to complete the integrated circuit. It provides a solid foundation for depositing the conductive interconnect materials used.

The polyimide layer 108 is formed to a thickness of about 1.5 to 4μ, so that the isolation ring 106 having a depth of about 1 to 1.5JIII is filled with polyimide, and the surface of the polyimide layer 108 is smooth and smooth. substantially flat; The substantially planar surface of the polyimide layer 108 allows for a smooth separation 106 when subsequently formed electrical interconnects (typically formed of aluminum) are deposited on the surface of the wafer. This makes it possible to form an interconnection layer without the presence of a steep "step" above. When forming an interconnection layer, such a steep "step" does not exist. Quality and reliability issues typically arise in cases where such steps are present, since the thickness of the interconnect layer at the step is typically very thin. Therefore, there is a high probability that the interconnect layer will be cut, resulting in the formation of an open circuit.Furthermore, if the polyimide layer 108 is not used, the interconnect I1 layer to be formed later will is deposited on the surface of the insulation 11107,
In that case, an electrical short circuit will be formed between the interconnect layer and the semiconductor region through the defects or "pinholes" present in the insulating layer 107. The use of polyimide 11108 eliminates the problems associated with such pinholes.

Channel stop regions 190-1 and 190-2 are formed in substrate 100 by known methods to provide electrical isolation between adjacent transistor regions.

As shown in FIG. 2, the channel stop area 190-
1 and 190-2 provide electrical isolation between a buried layer collector region [101, a base region 103, an upper transmitter region 104, and a collector contact 105] and an adjacent device (not shown). . Substrate 10
In the case of a 0# P-type root, the channel stop region can be ion-implanted with P-type doban (typically boron) to a density of approximately 10'4 atoms/'CI'.
It is formed as a 111% doped P+ region.

As shown in FIG. 3, contact openings are formed in the polyimide layer 108 and the insulating layer 107 below which are to be electrically contacted by the later formed electrical interconnect layer 111. Existing areas are exposed. As an example, FIG. 3 shows a contact opening 120 formed to expose the base region 103;
A contact opening 121 formed to expose the emitter region 104 is shown. Polyimide 1i110
The remainder of 8 electrically isolates interconnect 11111 from the underlying active device area.

When forming the contact openings 120 and 121, it is possible to use, for example, any suitable photolithographic masking technique known in semiconductor technology,
For example, 97% tetramethyl ammonium hydroxide and 3
% ethylenediamide to etch away the unwanted portions of polyimide layer 108, and then etching insulating layer 190 as described above. still,
As the polyimide 108, it is desirable to use photosensitive polyimide. A photosensitive polyimide is formed on the surface of a semiconductor wafer, and selected areas of the polyimide layer are exposed to actinic radiation (typically ultraviolet radiation) through a contact mask. The polyimide 108 is then edged, fixing the actinically irradiated areas and removing all other areas with a solvent to form contact openings 120 and 1.
A permanent polyimide 11108 with holes 21 is formed.

After forming the contact opening, an electrically conductive material (
A layer (typically aluminum) is formed on the surface of the wafer to make electrical contact with the areas exposed by the contact openings described above. interconnect layer 11
If an aluminum metallization is used as 1, it is possible to form the metallization by known methods at a sufficiently low weight so as not to damage the polyimide layer 108 (e.g. U.S. Patent No. 3.1
08,359). The aluminum metallization 11111 is then patterned using known techniques. For example, selective areas of the aluminum layer 111 are etched away to form contact openings by masking with photoresist and using a known aluminum etchant such as a mixture of acetic acid, nitric acid, phosphoric acid, or silicon tetrachloride C plasma etching. A plurality of electrical interconnects are formed on the wafer surface interconnecting the desired exposed areas by doing so.

It is important to note that the step of forming the isolation groove 106,
Forming the compound layer or insulation H107, forming the polyimide layer 108, and electrical interconnect layer 111
The total separation process including the process of forming
This means that it is carried out at a temperature lower than ℃. In prior art separation processes, thermal oxides are used as the separation means, so that after forming the buried layer collector 101, the wafers are treated at temperatures in the range of approximately 800 to 1,000 degrees Fahrenheit for an extended period of time. It is necessary to do so. In such prior art, the dopant present in the buried layer flefter 101 is redistributed during the growth process of the thermal oxide separation layer, and the dopant in the buried layer is diffused upward into the epitaxial layer. to invade. Such upward diffusion occurs in the buried layer collector 1.
01 and the base 103, thus reducing the breakdown voltage between the collector and base (this increases the current gain (βII) of the transistor and increases the capacitance between the collector and base). Along with letting
Decrease the switching speed of the transistor.

On the other hand, according to the present invention, there is no need to form an insulating oxide formed by thermal oxidation, and therefore the buried layer collector region 101 is not subjected to long-term treatment at high temperatures. . Therefore, in one layer of the semiconductor device according to the present invention, when forming isolation means such as the isolation trenches 106-1 to 106-3 and the polyimide layer 108, the dopant diffusion distribution remains substantially unchanged. It is possible to maintain it. On the other hand, since the prior art uses thermal oxidation, unlike the present invention, the wafer is treated at a constant temperature of 14°C. Thus, in the present invention, the fact that the diffusion distribution red remains substantially unchanged means that the separation grooves 1o6
-i to 106-3 are particularly important. 5
By using the isolated fJA region formed according to the present invention, it is possible to maintain the diffusion distribution unchanged, which means that it is possible to manufacture semiconductor devices with a shallower diffusion v4 band. This means that in a device so constructed, the PN junction terminates at the surface of the isolation trench, and as in prior art devices, thermal oxidation does not occur. The redistribution of dopants during the process is different from the one in which the PN junction terminates at some distance inward from the isolation thermal oxide. For these reasons, the present invention has a lower leakage current and therefore a more stable current gain (βI) compared to the prior art.
It means a skewer that can manufacture semiconductor devices with Furthermore, in the configurations made in accordance with the present invention, the stray capacitance is reduced and the diffusion region is made narrower (X) so that the transition distance for current carriers is -M. It is shorter and therefore has improved switching speed compared to conventional devices.

Although the specific configuration of the present invention has been explained in detail above,
The present invention is not limited to these specific examples; it goes without saying that various modifications can be made without departing from the technical scope of the present invention.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional semiconductor wafer having a plurality of components, and FIG. 2 is a sectional view showing a semiconductor wafer having a separation etching removal section and polyimide constructed according to the present invention. Figure 3 shows that an interconnection pattern is formed in the apparatus shown in Figure 2 by drilling through the polyimide membrane and having openings for the contacts and optionally interconnecting the reluctant parts of the various devices. FIG. (Explanation of symbols) 1002 Substrate 101: Buried layer 102: Epitaxial layer 103: Base region 104: Emitter v4 region 105: Collector contact 106: Isolation groove 107: Insulating layer 108: Polyimide layer 111.190: Mutual contact Vt11120. 121
, 122: Penetrating conductor 190: Channel stopper

Claims (1)

[Claims] 1. A semiconductor device comprising a plurality of conductive regions formed in a semiconductor substrate and isolation regions formed between the conductive regions, and the isolation #4 region is A semiconductor device comprising a groove formed in the substrate, an insulating layer being formed on the surface of the groove and filled with polyimide to provide a substantially smooth substrate surface. 2. A semiconductor@W has a wafer provided with a semiconductor material layer, and a groove is formed on the upper surface of the semiconductor layer to form an island-shaped portion made of the semiconductor material from the wafer; Each island of semiconductor material is laterally separated from an adjacent island of semiconductor material by a groove formed in the surface of the semiconductor layer, and includes a surface of the groove and a surface of the semiconductor layer. an insulating layer is formed, a polyimide layer is formed on the upper surface of the insulating layer formed on the semiconductor layer and the trench to fill the trench, and an island-shaped portion consisting of the trench and the semiconductor material; A device characterized in that it provides a substantially smooth upper surface above the. 3. The device according to item 2 above, wherein the insulating layer formed on the surface of the semiconductor layer including the surface of the groove includes an oxide of the semiconductor material. 4. The device according to item 2 above, wherein the insulating layer formed on the surface of the semiconductor layer including the surface of the groove includes a nitride of the semiconductor material. 5. In item 2 above, the insulating layer formed on the surface of the semiconductor layer including the surface of the structure includes an oxide layer of the semiconductor material and a nitrided layer of the semiconductor material formed thereon. A device characterized by having a material layer. 6. The device of claim 2, further comprising a first interconnection grid pattern previously formed between the insulating layer and the polyimide layer. 7. In paragraph 6 above, a first set of through conductors are formed through selected portions of the insulating layer, and from the first interconnect lead pattern are formed within the island of semiconductor material. A device characterized by making it possible to contact a selected diffusion region. 8. In the above item 2 or 7, a second set of through conductors is formed through selected portions of the polyimide layer and an underlying insulating layer, and is formed within the semiconductor material island. 1. A device for forming a contact region to a selective diffusion region. 9. In item 8 above, a second interconnection lead pattern is formed on the upper surface of the device, interconnecting selected areas formed within the semiconductor material island via the through conductor. A device characterized in that it forms an integrated circuit. 10. The device according to item 9 above, wherein the polyimide layer formed on the upper surface of the island-shaped portion has a thickness of 4- or less. 11. The device according to item 6 above, wherein the semiconductor material comprises silicon. 12. The device of claim 6, wherein the first interconnect lead pattern is polysilicon. 13. The device of claim 9, wherein the second interconnect lead pattern comprises aluminum. 14. The device according to item 2 above, wherein a highly doped region is provided below the bottom of a selected one of the trenches, and the highly doped region functions as a channel stop wA region. 15. In a method of manufacturing a semiconductor device, a selectively doped region is formed on an upper surface of a semiconductor layer, and a groove is formed surrounding a selected portion of the upper surface of the semiconductor layer and extending to a selected depth of the semiconductor layer. A method characterized by forming an insulating layer on the upper surface of the groove and the semiconductor layer, and forming a polyimide layer on the upper surface of the insulating layer formed on the pre-groove and the semiconductor layer. . 16. In item 15 above, an opening is formed in a selected region of the insulating layer to expose a selected selectively doped region of the underlying semiconductor layer, and the method is performed on the insulating layer and through the opening. forming an interconnect lead pattern extending to the underlying selectively doped regions to form an integrated circuit. 11. In the above item 15, forming an opening through the polyimide layer and a selected region of the insulating layer existing below the selected doped region of the semiconductor layer below the polyimide layer. A method of forming an integrated circuit by exposing and forming an interconnect lead pattern on the upper surface of the polyimide layer and reaching the underlying selectively doped regions through the opening. 18. The method according to item 16 or 17 above, wherein the semiconductor material is silicon. 19. The method of claim 16, wherein the interconnect lead pattern comprises polysilicon. 20. The method of item 17 above, wherein the interconnect one-node pattern comprises aluminum.