JPS5984576A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5984576A JPS5984576A JP19547882A JP19547882A JPS5984576A JP S5984576 A JPS5984576 A JP S5984576A JP 19547882 A JP19547882 A JP 19547882A JP 19547882 A JP19547882 A JP 19547882A JP S5984576 A JPS5984576 A JP S5984576A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter
- film
- arsenic
- dopos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000001020 plasma etching Methods 0.000 claims abstract description 5
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 4
- 239000011344 liquid material Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 abstract description 14
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910052909 inorganic silicate Inorganic materials 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- DWSWCPPGLRSPIT-UHFFFAOYSA-N benzo[c][2,1]benzoxaphosphinin-6-ium 6-oxide Chemical compound C1=CC=C2[P+](=O)OC3=CC=CC=C3C2=C1 DWSWCPPGLRSPIT-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910018949 PtAu Inorganic materials 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、拡散源として不純物を含む多結晶シリコンを
用いるマイクロ波トランジスタあるいはマイクロ波ＩＯ
の製法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a microwave transistor or a microwave IO using polycrystalline silicon containing impurities as a diffusion source.
Concerning the manufacturing method.
マイクロ波トランジスタでは高周波動作を行なうため、
ベース拡散層・エミッタ拡散層は半導体表面より極めて
浅く、エミッタ・ベース接合は０．１μｍ以下になるこ
とが多い。接合の深さがこの程度になると、エミッタ拡
散層とエミッタ電極とのオーミック接合をとる場合に、
配線部材の金属あるいは金属間化合物と半導体基板のシ
リコンとの共融体がエミッタ・ベース接合まで進入し、
エミッタ・ベース短絡故障が続発する。そのため砒素等
の不純物を含むポリシリコン（ｄｏｐｅｃｌ ｐｏｌｙ
ｓｉ−１ｉｃｏｎ、以下ＤＯＰＯ８という）層を拡散源
として用イ、エミッタ電極とエミッタ・ベース接合トの
距離を大きくすることによって、エミッタ・ベース短絡
を防ぐ手段がとられている。Because microwave transistors operate at high frequencies,
The base diffusion layer and emitter diffusion layer are extremely shallow than the semiconductor surface, and the emitter-base junction is often 0.1 μm or less. When the junction depth reaches this level, when making an ohmic junction between the emitter diffusion layer and the emitter electrode,
The eutectic of the metal or intermetallic compound of the wiring member and the silicon of the semiconductor substrate enters the emitter-base junction,
Emitter-base short circuit failures occur one after another. Therefore, polysilicon containing impurities such as arsenic (dopecl polysilicon)
si-1icon (hereinafter referred to as DOPO8) layer as a diffusion source, measures are taken to prevent emitter-base shorting by increasing the distance between the emitter electrode and the emitter-base junction.
上記の手段で、エミッタ・ベース短絡事故が防止できる
が、マイクロ波トランジスタではエミッタ領域とベース
コンタクト部との距離が極めて近いことから、エミッタ
電極とベース電極との短絡事故が生じ易くなる欠点が生
ずる。The above measures can prevent emitter-base short circuit accidents, but in microwave transistors, the distance between the emitter region and the base contact part is extremely close, so there is a drawback that short circuit accidents between the emitter electrode and the base electrode are likely to occur. .
以下第１図により従来のＤＯＰＯ８層を有するマイクロ
波トランジスタの製造方法についての問題点を説明する
。第１図で（ａ）はｎ型の半導体基板２にｐ型のベース
層５を形成した後、半導体基板２上のシリコン酸化膜１
にエミツタ開口部３ベースコンタクト開口部４を形成し
た状態である。（ｂ）は次の工程で半導体表面に砒素Ｄ
ＯＰＯ８層６とその上にｃＶＤ法により生成した５ｉｎ
２膜（以下では０ＶＤ−８ｉｎ２膜という）７を形成し
た状態である。Hereinafter, problems with the conventional method of manufacturing a microwave transistor having eight DOPO layers will be explained with reference to FIG. In FIG. 1(a), after forming a p-type base layer 5 on an n-type semiconductor substrate 2, a silicon oxide film 1 is formed on the semiconductor substrate 2.
This is a state in which an emitter opening 3 and a base contact opening 4 are formed. In (b), arsenic D is added to the semiconductor surface in the next step.
OPO 8 layer 6 and 5 inch layer formed on it by cVD method
This is a state in which two films (hereinafter referred to as 0VD-8in2 films) 7 are formed.
（ｃ）は公知の写真蝕刻技術にょ９、ＯＶ］）−８ｉｎ
２膜７とＤＯＰＯ８層６をエミッタ開口部３近傍にのみ
残して除去した後、熱拡散によｐＤＯＰＯ８（エミッタ
開口部に残ったＤＯＰＯ８層）８の砒素が拡散してエミ
ッタ開口部３の位置にｎ形エミッタ領域を形成した状態
である。（ｄ）はエミッタ領域形成後、ＤＯＰＯ８８上
（７） ＯＶ Ｄ Ｓ ｉ ０２膜を除去し、周知の
方法でエミッタ電極９Ｉ、およびベース電極９．を形成
した状態である。この電極としては非常に浅いｐｎ接合
のコンタクトに有効なＰｔＳｉ −Ｔｉ −ＰｔＡｕ構
造としている。以上説明し′た方法でエミッタ電極９．
はＤＯＰＯ８８を介してエミッタ領域と接し、また電極
部材もＰｔＳｉ −Ｔｉ −Ｐｔ−Ａｕ構造としである
ので、エミッタ・ベース接合短絡を防止できる。(c) is a known photo-etching technique 9,OV])-8in
After removing the pDOPO8 layer 6 and leaving it only in the vicinity of the emitter opening 3, the arsenic in the pDOPO8 (the DOPO8 layer remaining in the emitter opening) 8 is diffused by thermal diffusion to the position of the emitter opening 3. This is a state in which an n-type emitter region is formed. (d) After forming the emitter region, the OV D Si 02 film (7) on the DOPO 88 is removed, and the emitter electrode 9I and base electrode 9. It is in a state where it has been formed. This electrode has a PtSi--Ti--PtAu structure which is effective for very shallow pn junction contact. Emitter electrode 9.
is in contact with the emitter region via the DOPO 88, and the electrode member also has a PtSi-Ti-Pt-Au structure, so emitter-base junction short circuits can be prevented.
しかしマイクロ波トランジスタでは寸法は微細であり、
エミッタ開口部３とベースコンタクト開口部４との間隔
は２〜３μｍ、エミッタ開口部３の幅は０．５〜１．０
μｍ程度であり、第１図（ｃ）のエミッタ開口部３にの
み０ＶＤ−８１０２膜、ＤＯＰＯ８層をのこす写真蝕刻
技術では目合せによるズレを考慮して設計上エミッタ開
口部３のＱｆｌｉｉよりかなり広く２倍以上の幅の層を
のこす。従っｃＤｏｐｏｓ８はエミッタ・ベース間の酸
化層の上に、エミッタ開口部３の端からかなりの距離ま
で延び、ＤＯＰＯ８８とベース電極９２の間隔は設計上
０．５〜１．５μｍ ｌｄ度になる。製造工程中マスク
目金せを数回行い、その結果０．５μｎ１稈度の間隔を
得るのは見合せ精度を考慮すると製造プロセス上非常に
困難であり、ＤＯＰＯ８−ベース電極短絡不良が多発し
製造歩留りを低下させる。However, the dimensions of microwave transistors are minute;
The distance between the emitter opening 3 and the base contact opening 4 is 2 to 3 μm, and the width of the emitter opening 3 is 0.5 to 1.0 μm.
It is about μm, and is considerably wider than the Qflii of the emitter opening 3 due to the design, taking into account misalignment due to alignment, in the photo-etching technique that leaves the 0VD-8102 film and the DOPO 8 layer only in the emitter opening 3 in Fig. 1(c). Leave a layer at least twice as wide. Therefore, the cDopos 8 extends a considerable distance from the end of the emitter opening 3 on the oxide layer between the emitter and the base, and the distance between the DOPO 88 and the base electrode 92 is designed to be 0.5 to 1.5 μm ld degrees. During the manufacturing process, mask fitting is performed several times, and as a result, it is very difficult to obtain a spacing of 0.5 μn 1 culm degree in terms of the manufacturing process, considering the alignment accuracy, and there are many short-circuit defects between the DOPO8 and base electrodes, which reduces the manufacturing yield. decrease.
本発明の目的は上記の欠点を除去し、微細パターンを有
し、拡散源としてＤＯＩ）Ｏ８層を用いるマイクロ波ト
ランジスタ、ＩＯ等の半導体装ｊδにおいて、ＤＯｌ）
Ｏ８をセルフ・アライメント釦形成するととにより、製
造歩留を向上させる製造方法を提供することにある。The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to improve semiconductor devices such as microwave transistors and IOs that have a fine pattern and use a DOI)O8 layer as a diffusion source.
It is an object of the present invention to provide a manufacturing method that improves the manufacturing yield by forming O8 into a self-alignment button.
以下本発明を図面を参照して詳しく説゛明する。The present invention will be explained in detail below with reference to the drawings.
第２図は本発明の一実施例で、第１図のマイクロ波トラ
ンジスタに適用した場合を示す。FIG. 2 shows an embodiment of the present invention, which is applied to the microwave transistor of FIG. 1.
第２図（Ｒ）はベース層５を半導体基板２に形成した後
、半導体基板２上のシリコン酸化膜１にエミッタ開口部
３．ベースコンタクト開口部４を形成した状態である。FIG. 2(R) shows that after a base layer 5 is formed on a semiconductor substrate 2, an emitter opening 3 is formed in a silicon oxide film 1 on the semiconductor substrate 2. This is the state in which the base contact opening 4 has been formed.
（ｂ）は次の工程で砒素ＤＯＰＯ８層６とその上に０Ｖ
Ｄ−８ｉｎ２膜７を形成した状態である。前者は２０ｏ
ＯＸ、後者は１００ＯＸ程度の厚みとする。次に半導体
表面に例えばホトレジスト層１０をスピンコーテイング
後ベーキングした状態を（ｃ）に示す。液体ホトンジス
トは流動性に富むから、エミッタ開口部３．ベースコン
タクト開口部４上は多少凹状になるが半導体表面は略し
平坦にホトレジスト層１０で覆われる。この状態で酸素
プラズマエツチングを行な゛う。ホトレジスト層１０は
灰化され、次第にエツチングへれる。ｃＶＤ。(b) In the next step, the arsenic DOPO8 layer 6 and the 0V
This is a state in which a D-8in2 film 7 is formed. The former is 20o
OX, and the latter has a thickness of about 100 OX. Next, a photoresist layer 10, for example, is spin-coated on the semiconductor surface and then baked, as shown in FIG. Since the liquid photonist has high fluidity, the emitter opening 3. Although the top of the base contact opening 4 is somewhat concave, the semiconductor surface is covered flat with the photoresist layer 10. Oxygen plasma etching is performed in this state. The photoresist layer 10 is ashed and gradually etched. cVD.
−８ｉｎ、、膜７６が各開口部３，４をのぞき露出され
た時にエツチングを停止した状態が（ｄ）である。図に
示すように各開口部３，４にのみホトレジスト層１１が
残る。この状態で希釈弗酸中に侵し１．露山部の０ＶＤ
−８ｉｎ２層７′をエツチングし、さらに間部の砒素Ｄ
ＯＰ Ｏ８層６′をＨＦ ： ：ＥＩＮ Ｏｎ ’ Ｏ
■■５０００Ａの混合液中にてエツチングする。この工
程の後ホトレジスト層１１を除去した状態を（ｅ）に示
す。エミッタ開口部３．ベースコンタクト開口部４にの
み、０ＶＤ−８ｔ０４層、砒素ＤＯＰＯ８層が残ってい
る。次にエミッタ開口部３内のみに砒素ＤＯＰＯ８層を
残すため、エミツタ開口部３上部のみに選択的にホトレ
ジスト層１２を形成した状態が（ｆ）である。次にベー
スコンタクト開口部４のＯＶＤ ８ｉ０＋層、砒素Ｄ
ＯＰＯ８層を前記エツチング液で除去した後、熱拡散に
よりエミッタ開口部３のＤＯＰＯ８８から砒素拡散を行
ないエミッタ領域を形成する。以下公知の方法によ！１
ｌＯＶＤ−８ｉ０４層の除去、各電極９．．９□の形成
を行ない（ｇ）に示す構造のトランジスタを得ることが
できる。この製造方法によればエミッタ不純物拡散源で
あるＤＯＰＯ８８はセルフアライメント（自己整合的）
にエミッタ開口部３にのみ存在し、従来の方法による第
１図（ｄ）に示すようなエミッタ・ベース間の酸化層上
の延長部は全くない。-8 inches, the state in which the etching is stopped when the film 76 is exposed except through the openings 3 and 4 is shown in (d). As shown in the figure, the photoresist layer 11 remains only in each opening 3,4. In this state, immerse it in diluted hydrofluoric acid.1. 0VD in the open mountain area
- Etch the 8 inch 2 layer 7' and further arsenic D in between.
OP O8 layer 6' HF: :EIN On 'O
■■ Etching in a mixed solution of 5000A. The state in which the photoresist layer 11 is removed after this step is shown in (e). Emitter opening 3. The 0VD-8t04 layer and the arsenic DOPO8 layer remain only in the base contact opening 4. Next, in order to leave the arsenic DOPO8 layer only inside the emitter opening 3, a photoresist layer 12 is selectively formed only on the upper part of the emitter opening 3, as shown in FIG. Next, OVD 8i0+ layer of base contact opening 4, arsenic D
After removing the OPO 8 layer with the etching solution, arsenic is diffused from the DOPO 88 in the emitter opening 3 by thermal diffusion to form an emitter region. Follow the known method below! 1
Removal of lOVD-8i04 layer, each electrode 9. ．． By forming 9□, a transistor having the structure shown in (g) can be obtained. According to this manufacturing method, the emitter impurity diffusion source DOPO88 is self-aligned.
There is no extension on the oxide layer between emitter and base as shown in FIG. 1(d) in the conventional method.
以上説明したように本発明によれば、不純物を含む多結
晶シリコンを半導体基板上の酸化層の特定の開口部９本
例ではエミッタ開口部、にのみセルフアライメントに形
成し、これを拡散源とするから、薄いｐｎ接合での電極
生成による接合破壊。As explained above, according to the present invention, polycrystalline silicon containing impurities is formed in self-alignment only in specific openings (in this example, the emitter opening) of an oxide layer on a semiconductor substrate, and this is used as a diffusion source. Therefore, junction breakdown occurs due to electrode formation in a thin pn junction.
隣接する電極との短絡故障が生じない。従って本発明の
製造方法によって、微細パターンを有する半導体装置を
歩留よく製造することができる。No short-circuit failure with adjacent electrodes occurs. Therefore, by the manufacturing method of the present invention, semiconductor devices having fine patterns can be manufactured with high yield.
なお実施例では液状のホトレジストを第２図（ｃ）で用
いだが、流動性のある物質であればよく、ポリイミド樹
脂、液状シリカフィルムでもよい。まだ前記物質のプラ
ズマエツチングは酸素ガスにより行ったが、フレオン系
ガスによってもよい。Although liquid photoresist is used in the embodiment as shown in FIG. 2(c), any material with fluidity may be used, such as polyimide resin or liquid silica film. Although plasma etching of the above-mentioned material was performed using oxygen gas, it may also be performed using Freon gas.
第１図は従来の製造方法を示す図、第２図は本発明の一
実施例を示す図である。
１・・・・・・シリコン酸化膜、２・・・・・・半導体
基板、３・・・・・・エミッタ開口部、４・・・・・・
ベースコンタクト開口部、５・・・・・・ベース層、６
．６’・・自・・砒素ＤＯＰＯ８層、７．７’−・”０
ＶＤ−８ｔｏ２層、８・・・・・・ＤＯＰＯ８（エミッ
タ開口部に残ったＤＯＰＯ８層）、９ｍ・９２・・・・
・・エミッタ電極・コレクタ電極、１０，１２°°゛・
・・ホトレジスト層、１１・・・・・・開口部に残った
ホトレジスト層。FIG. 1 is a diagram showing a conventional manufacturing method, and FIG. 2 is a diagram showing an embodiment of the present invention. 1...Silicon oxide film, 2...Semiconductor substrate, 3...Emitter opening, 4...
Base contact opening, 5...Base layer, 6
．． 6'...Auto...Arsenic DOPO8 layer, 7.7'-・”0
VD-8 to 2 layers, 8...DOPO8 (DOPO8 layer remaining in the emitter opening), 9m/92...
・・Emitter electrode/Collector electrode, 10, 12°°゛・
... Photoresist layer, 11... Photoresist layer remaining in the opening.
Claims (1)
基板において、拡散源として不純物を含む多結晶シリコ
ン膜およびＯＶＤ法によるシリコン酸化膜よりなる複合
膜を形成する第１工程。 液状物、質を基板表面に平坦に塗布し同物質による膜を
形成する第２工程、プラズマエツチングにより、一様に
開口部以外のシリコン酸化膜上の複合膜が露出するまで
エツチングする第３工程。 露出された複合膜をエツチング後、第２工程による膜を
除去する第４工程、拡散を行なわない開口部に形成され
た第１工程の複合膜をエツチングする第５工程、拡散を
行なう開口部にて拡散領域を形成し、且つ電極を形成す
る第６エ程よりなることを特徴とする半導体装置の製造
方法。 ２、前記液状物質がホト・レジスト、ポリイミド樹脂、
液状シリカフィルムであることを特徴とする特許請求の
範囲第１項記載の半導体装置の製造方法。 ３、前記プラズマエツチングは酸素ガスアルイハフレオ
ン系ガスによるものであることを特徴とする特許請求の
範囲第２項記載の半導体装置の製造方法。[Claims] 1. A first step of forming a composite film consisting of a polycrystalline silicon film containing impurities as a diffusion source and a silicon oxide film by OVD method in a semiconductor substrate having a silicon oxide film with an opening formed therein. . The second step is to apply a liquid material evenly onto the surface of the substrate to form a film of the same material, and the third step is to use plasma etching to uniformly etch the composite film on the silicon oxide film except for the openings until it is exposed. . After etching the exposed composite film, the fourth step is to remove the film from the second step, the fifth step is to etch the composite film formed in the first step in the opening where diffusion is not performed, and the fifth step is to remove the film in the opening where diffusion is to be performed. A method for manufacturing a semiconductor device, comprising a sixth step of forming a diffusion region and forming an electrode. 2. The liquid substance is photoresist, polyimide resin,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a liquid silica film. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the plasma etching is performed using an oxygen gas or an alihafreon gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19547882A JPS5984576A (en) | 1982-11-08 | 1982-11-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19547882A JPS5984576A (en) | 1982-11-08 | 1982-11-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5984576A true JPS5984576A (en) | 1984-05-16 |
Family
ID=16341749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19547882A Pending JPS5984576A (en) | 1982-11-08 | 1982-11-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984576A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2374368A1 (en) * | 1976-12-16 | 1978-07-13 | Gen Electric | POLYESTER REINFORCED THERMOPLASTIC COMPOSITION |
| US5071789A (en) * | 1985-08-02 | 1991-12-10 | Kabushiki Kaisha Toshiba | Method for forming a metal electrical connector to a surface of a semiconductor device adjacent a sidewall of insulation material with metal creep-up extending up that sidewall, and related device |
-
1982
- 1982-11-08 JP JP19547882A patent/JPS5984576A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2374368A1 (en) * | 1976-12-16 | 1978-07-13 | Gen Electric | POLYESTER REINFORCED THERMOPLASTIC COMPOSITION |
| US5071789A (en) * | 1985-08-02 | 1991-12-10 | Kabushiki Kaisha Toshiba | Method for forming a metal electrical connector to a surface of a semiconductor device adjacent a sidewall of insulation material with metal creep-up extending up that sidewall, and related device |
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