JPS6315475A - Manufacture of field effect semiconductor device - Google Patents

Abstract

PURPOSE:To form easily an asymmetrical recess/T shaped gate electrode by forming a recess with the use of the first resist mask and in addition to laminating the second resist as well as the third resist that has sensitivity higher than that of the second resist, thereby opening a pattern for forming a T shaped gate. CONSTITUTION:A recess-forming pattern having an opening 7 is formed on a first resist coating 6 on a semiconductor substrate 1 and the recess 8 is formed by using the above pattern as a mask. A second resist coating 9 is formed and pre-baked, and then a third resist coating 10 more sensitive than the coating 9 is pre-baked is formed and pre-baked. Furthermore, an exposure 11 to a position close to the source electrode 4 from the middle of the recess 8 of the pattern corresponding to a gate length and the exposure 12, in which a dose to the pattern corresponding to size where a gate electrode is enlarged to a T shape is lower than that of the pattern corresponding to the gate length, are carried out according to an optional order. Then, the second and third resists 9 and 10 are treated with a development process to open gate-forming patterns 13a and 13b, through which gate metal 14' is applied to form a T-shaped gate electrode 14.

Description

[Detailed Description of the Invention] [Summary] When manufacturing a field effect semiconductor device, the present invention forms a recess in a first resist mask, and uses a second resist and a third resist with higher sensitivity. A pattern corresponding to the gate length is exposed to light at a position close to the source electrode, and a pattern corresponding to the enlarged size of the gate electrode is exposed to light at a lower dose than this, and then developed and T.
The asymmetric recess/T-shaped gate electrode can be easily formed by opening the pattern for forming a shaped gate and depositing gate metal to form a T-shaped gate electrode.

(Industrial Field of Application) The present invention relates to a method of manufacturing a field effect semiconductor device, and more particularly to a method of manufacturing a field effect semiconductor package having an asymmetric recessed T-shaped gate electrode.

■-V such as gallium arsenide (GaAs) with high electron mobility
Although progress is being made in improving the cutoff frequency and other characteristics of field-effect transistors, the structure of the gate electrode and recess greatly controls the characteristics of field-effect transistors, and improvements in the manufacturing method are required. has been done.

[Conventional technology]

Schottky barrier field effect transistors (MES FETs), which use GaAs as the half-body material, are already widely used in microwave bands, etc., and have achieved even higher mobility through spatial separation doping and making electrons into a two-dimensional state. The practical use of high electron mobility field effect transistors (HEMTs) has begun.

In order to improve the characteristics of these FETs, the following measures have been conventionally taken for gate electrodes and recess structures, for example.

■ Shortening the gate length: Since the cutoff frequency is inversely proportional to the square of the gate length, the latest microfabrication technology is used to shorten the gate length as much as possible.

■ T-shaped gate: Gate resistance (
In order to prevent an increase in the conductor resistance of the gate electrode, the cross-sectional shape of the gate electrode is made into a T-shape to increase the cross-sectional area.

■ Reduction of recess length: Reduce source resistance (series resistance between source and gate) to increase transfer conductance g1, etc.

■ Asymmetrical recess: In order to prevent the drain breakdown voltage from decreasing due to the shortening of the recess length, the depletion layer on the drain side is and decrease the electric field strength.

Many manufacturing methods have already been provided for the above-mentioned (1) and (2), and for example, the present inventor has previously provided a manufacturing method for (1) and (3) in Japanese Patent Application No. 57-163063.

According to the invention, a semiconductor active layer 23 is formed on a substrate 21 and a resist 2 is deposited on the semiconductor active layer 23, as shown in FIG.
6 is coated, main exposure treatment 27 is performed on the resist layer 26 according to the gate electrode pattern, and auxiliary exposure 28 biased toward the drain electrode 25 side is performed after or before the exposure treatment 27. The resist layer 26 subjected to the exposures 27 and 28 is developed to form a resist hole 29 having an asymmetric cross section, and the semiconductor active layer 23 is selectively etched using the resist layer 26 as a mask. A recess 30 is formed in the recess 30, and the recess 30 is further formed using the resist layer 26 as a mask.
A gate electrode 34 is formed on the surface of the substrate. Note that 22 is a buffer layer, 24 is a source electrode, and 34 is a gate metal layer.

[Problem that the invention seeks to solve]

According to the invention, an asymmetric recess with a shortened recess length can be formed, and a T-shaped gate electrode has also been manufactured.
It is difficult to form an asymmetric recess and a T-shaped gate electrode at the same time, and this has not yet been realized, and there is a need for a manufacturing method that makes this possible.

[Means for solving problems]

The above problem is solved by coating the semiconductor substrate with a first resist, opening a recess formation pattern, forming a recess using the pattern as a mask, coating the semiconductor substrate with a second resist, and pre-baking. A third resist with higher sensitivity than the second resist is coated and prebaked, and a pattern corresponding to the gate length is exposed from the center of the recess to a position near the source electrode, and a pattern corresponding to the size to expand the gate electrode into a T-shape is applied. The second and third resists are developed to open a T-shaped gate forming pattern, and then the gate metal is exposed to light at a lower dose than the pattern corresponding to the gate length. This problem is solved by a method for manufacturing a field-effect semiconductor device according to the invention, in which a T-shaped gate electrode is deposited.

[For production]

According to the present invention, two layers of, for example, a positive resist for electron beam exposure are laminated on a semiconductor device in which a recess is formed, and a pattern corresponding to the gate length and a pattern corresponding to the size for enlarging the gate electrode into a T-shape are formed. Perform exposures in any order.

However, the lower layer resist has lower sensitivity than the upper layer resist and has a thickness corresponding to the height of the portion of the T-shaped gate electrode having a smaller cross-sectional dimension.

In addition, exposure of a pattern corresponding to the gate length is done at a dose that provides the required exposure amount for the resist layer below, and exposure for a pattern corresponding to the size that expands into a T-shape is set at a dose that provides the required exposure amount for the resist layer above. do. Note that the exposure of a pattern corresponding to at least the gate length is performed at a position close to the source electrode from the center of the recess.

When these two layers of resist are developed, an opening with a pattern of enlarged dimensions is formed in the upper resist, and an opening with a pattern of the desired gate length is formed in the lower resist, and the gate metal is deposited and lifted off. A T-shaped gate electrode is thereby formed.

〔Example〕

The present invention will be specifically explained below using examples.

FIGS. 1(a) to 1(a) are schematic side sectional views in the order of steps showing an embodiment of the present invention relating to a MES FET.

See Figure 1 fa): On the semi-insulating GaAs base Fi1,
For example, a non-doped GaAs buffer layer 2 with an impurity concentration of 2 to 3 x 10"cm-3 and a thickness of 200 to 300 nm.
After epitaxially growing an n-type GaAs active layer 3 of about 100 mL and performing device isolation (not shown), a source electrode 4 and a drain electrode 5 are provided using, for example, gold germanium/gold (AuGe/Au). .

On this semiconductor substrate, a positive resist for electron beam exposure such as CMR manufactured by Fujitsu is applied to a thickness of 0.3 to 0.5 mm.
A resist layer 6 is formed by coating the resist layer 6 to a thickness of about 100 mm, and after prebaking, exposure and development are performed to form an open lower pattern corresponding to the recess length. Using this as a mask, etching is performed using, for example, a hydrofluoric acid (HF) solution to form a recess 8. Form. Note that the thickness of the active layer 3 under the recess 8 is, for example, approximately 70 to 100 m.

See FIG. 1(b): First, a resist layer 9 is applied onto this semiconductor substrate. However, in this embodiment, the resist layer 6
The same resist, such as Fujitsu's CMR, is coated over the resist layer 9 without removing it. The height is high.

After prebaking the resist layer 9, a positive resist having a higher sensitivity, such as EBR-9 manufactured by Toshi Co., Ltd., is applied to a thickness of, for example, 0.5 μm to form a resist layer 10, and prebaking is performed.

FIG. 1 (see C1) The resist layers 9 and 10 are exposed to light in an arbitrary order with a pattern corresponding to the gate length and a pattern corresponding to the size to enlarge the gate electrode into a T shape, for example, as shown below.

Exposure 11 of a pattern corresponding to the gate length is performed at a dose of, for example, about 1.5 x 10-'C/cm'' to provide the necessary exposure amount to the resist layer 9, and on the other hand, exposure of a pattern corresponding to the size of expanding into a T-shape is performed. 12 is the dose amount, for example 7X 10
-'C/cm'', the necessary exposure amount is applied only to the resist N10.The exposure 11 of the pattern corresponding to at least the gate length is set at a position close to the source electrode 4 from the center of the recess 8.

See FIG. 1Cd): The resist layers 10 and 9 are developed. Through this development process, the resist layer 10 has openings 13.
b. An opening 13a is formed in the resist layer 9.

Refer to Figure 1 (tel): For example, aluminum (At) is deposited as a gate metal in a vacuum. This gate metal is deposited in the opening 13b as shown in the figure, and the T-shaped gate electrode 14 is deposited inside the opening 13b.
is formed. Note that a gate metal layer 14' is deposited on the resist layer 10.

Refer to FIG. 1(f): When the resist layers 10.9 and 6 are stripped and removed, the gate metal layer 14' is also removed.

This example uses MES FET as an example, but IIEM
The present invention can be similarly applied to T'4- to easily realize an asymmetric recess/T-shaped gate electrode structure.

〔Effect of the invention〕

As described above (according to the present invention), the asymmetric recess/T-shaped gate electrode structure simultaneously realizes many improvements in the characteristics of a field effect type semiconductor device, and has a great effect on its progress.

[Brief explanation of drawings]

FIG. 1 (al to (fl) is a schematic diagram of the process order of the embodiment of the present invention. FIG. 2 (al to (el) is a schematic side sectional view of the process order of the conventional example. In the figure, 2 is a GaAs buffer layer, 3 is an n-type GaAs active layer, 4 is a source electrode, 5 is a drain electrode, 6 is a resist layer, 7 is a recess pattern, 8 is a recess, 9 is a low-sensitivity resist layer, 10 is a high-sensitivity resist layer Sensitivity resist layer, 11 is exposure of a pattern corresponding to the gate length, 12 is exposure of a pattern corresponding to the size expanding into a T shape, 13a is an opening in the resist layer 9, 13b is an opening in the resist NIO, 14 is a T-shaped gate electrode , 14' shows the gate metal deposition on the resist layer.

Claims (1)

[Claims] A first resist is coated on a semiconductor substrate, a recess formation pattern is opened, a recess is formed using the pattern as a mask, a second resist is coated and prebaked, and then a recess formation pattern is opened. A third resist with higher sensitivity than the second resist is coated and prebaked, and a pattern corresponding to the gate length is exposed from the center of the recess to a position near the source electrode, and the gate electrode is expanded into a T-shape. Exposure at a lower dose than the pattern corresponding to the gate length of the corresponding pattern is performed in any order, the second and third resists are developed to open a T-shaped gate forming pattern, and then the gate metal is exposed. 1. A method of manufacturing a field effect semiconductor device, comprising depositing a T-shaped gate electrode.