JPS58103123A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the redistribution by the surface deposition of Cr and by heat diffusion caused by the stress of a protective film interface by a method wherein an impurity ion is accelerated at a high electric field and is implanted into a compound semiconductor substrate provided with epitaxial growth and heat treatment (annealing treatment) is applied after forming an insulating protective film on the surface of the substrate. CONSTITUTION:After implanting <28>Si<+> of an N-conductive type impurity ion into the surface of a Cr dope semiinsulating GaAs substrate at an accelerating energy of 100keV, SiH4-NH3-H2 group gas is introduced in the substrate from an infrared heating-type nitride film growth device, and a nitride film with a film thickness of 1,000Angstrom is grown (regionI) with growth speed of 400Angstrom /min at a growth temperature of 700 deg.C. Next, the atmosphere is changed to N2 atmosphere under the present temperature condition, and room temperature is increased up to an annealing temperature of 800 deg.C at a temperature up speed of 100 deg.C/sec. Then, natural cooling is done (region II) by isolating infrared rays after maintaining the nitride film at 800 deg.C for 10min. An impurity conductive layer obtained in this way extremely controls unnecessary heat history as oppose to a conventional method and is superior in reproducibility.

Description

Detailed Description of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and in particular, impurity ions are implanted into a compound semiconductor substrate or a compound semiconductor substrate having an epitaxial growth layer thereon by accelerating the impurity ions in a high electric field. The present invention relates to a method of manufacturing a semiconductor device, which comprises a step of forming an insulating protective film on a substrate and then performing a heat treatment (annealing treatment) to form an N or P-type active conductive layer.

In general, when compound semiconductors such as G&M and InP* are exposed to a certain high temperature, one of the atoms constituting the compound dissociates from the substrate and evaporates, causing a deviation from the stoichiometric composition of the crystal at the surface. .

For example, in the case of a semi-insulating GaAs substrate, 8
When annealing is performed at 00° C. for 30 minutes, a phenomenon in which the substrate surface becomes N conductivity type is often observed.

It has long been known that a Ga Mu crystal becomes an N-conductivity type due to the large amount of N-conductivity type impurities mixed in during crystal growth and the high density of A- vacancies. For this reason, semi-insulating crystals are obtained by intentionally doping Or, which forms deep units. This thermal denaturation problem is especially caused by the thermal diffusion of Or
This is explained as an increase in vacancy density, etc., and is the cause of poor reproducibility in the formation of an impurity layer, which will be described later.

By the way, as methods for forming an N- or P-type impurity conductive layer on a QaA1 crystal substrate, epitaxial growth techniques doped with impurities and ion implantation techniques in which accelerated ions are physically implanted into the substrate surface are currently used. . The latter is a technology that has recently been attracting attention and being widely used as a 10-concentration process because it is thought to be theoretically possible to improve the reproducibility of impurity conductive layers and the uniformity of impurities within the plane of the substrate. .

However, the biggest drawback of ion implantation technology is that it requires high-temperature heat treatment to electrically activate the implanted ions. This results in a redistribution of In order to improve this point, in the past, in order to suppress the dissociation of IAI, 8101.81. After applying a protective film such as N4, heat at 800 to 850℃, N, or H3.
Annealing treatment for 10 to 30 minutes in an atmosphere, or annealing at 800 to 850°C for 10 to 30 minutes in an atmosphere in which arsine (AmH,) gas is introduced to form a positive partial pressure of A-gas.
A method of performing annealing treatment for 0 minutes is used. In the former case, problems include variations in the concentration distribution of the activated impurity layer, a drop in the concentration in the depth direction, and a decrease in the concentration at the surface. This is because stress is generated at the interface due to the difference in thermal expansion coefficient between the GaA1 substrate and the protective film, which causes Or to precipitate at the interface, and because the thermal diffusion coefficient of Or is large, redistribution of Or occurs near the surface. This is thought to be the cause. On the other hand, in the case of the latter, although the problem of the former is small, since it uses a highly poisonous gas called arsine, there are safety issues for workers, making it difficult to apply to mass-produced products. Furthermore, for future IO, the combination of a protective film and ion implantation technology is essential.

From this point of view, when we consider the combination of a GaAs substrate and ion implantation technology as an example, we first consider the A! The amount of I dissociated depends on the film growth conditions.

That is, as the growth temperature increases, the amount of dissociation also increases. However, even if we adopt a method of increasing the growth rate and completing the growth in a short time as the film growth conditions to suppress the dissociation of As,
If the amount of thermal energy received in the subsequent annealing treatment is large, the dissociation of Mu1 cannot be ignored. Further, the stress effect due to the difference in thermal expansion coefficient between the protective film and the G&M interface is also proportional to the amount of thermal energy received. Furthermore, regarding the thermal diffusion of Or, at present, the only way to easily obtain a semi-insulating substrate is an Or-doped substrate, and this problem is unlikely to be avoided. In order to prevent thermal diffusion, the heat treatment temperature can be lowered and the treatment time can be shortened, but the temperature required to electrically activate the ion-implanted impurity atoms can be lowered to 800°C or less. do not have.

Therefore, the purpose of the present invention is to solve problems such as dissociation of Mu$, surface precipitation of Or due to stress at the protective film interface, and redistribution due to thermal diffusion of Or by minimizing the thermal history during heat treatment and using ion implantation technology. An object of the present invention is to provide a method for manufacturing a compound semiconductor device that is improved in combination with a protective film. Next, an embodiment of the present invention will be described in detail.

Figure 1 is a temperature control diagram showing the conventional annealing method using a protective film for GaAs, and (a) shows the temperature transition during the process of growing a nitride film at 700°C on the surface of an ion-implanted substrate. (b) shows a different process, that is, conditions completely separate from the nitride film growth conditions, here 8
It shows the state of temperature transition in a process for obtaining an ion-implanted impurity layer by performing annealing treatment at 00° C. in a N atmosphere. This method requires cooling to room temperature after the nitride film growth is completed, and then heating again from room temperature to annealing temperature. This is an unnecessary process,
In order to reduce thermal history, we must first pay attention to this.

Figure 2 is a temperature control diagram of an embodiment of the present invention, in which 2881+ impurity ions of N conductivity type are deposited on the surface of an SOr-doped semi-insulating GaAs substrate at an acceleration energy of 100 keV.
After implantation with an implantation amount of 3 x 1012 (m-2), 81Ha NH
s Ht-based gas is introduced, and a nitride film with a thickness of 1000X is grown at a growth rate of 400X/mln at a growth temperature of 700°C (region I in FIG. 2).

Next, at that temperature state (within the same processing equipment), switch to Nl atmosphere and 100°C/l until the annealing temperature of 800°C.
Raise the room temperature at a heating rate of @e, hold it at 800℃ for 10 minutes, then turn off the infrared rays and let it cool naturally (area ■ in Figure 2).
).

The impurity conductive layer obtained in this way has unnecessary thermal history suppressed as much as possible compared to conventional methods, and has excellent reproducibility.
It also has the advantage of shortening the process. This is because the processing temperature is not returned to room temperature during the annealing process after the nitride film is formed.

Other embodiments of the present invention may be implemented as follows. That is, without holding the temperature for 10 minutes after rapidly increasing the temperature in the area shown in FIG.
A method of starting cooling immediately (in about a few seconds) may also be used. In this case, the substrate does not undergo metamorphosis even at a higher temperature than the method in which it is held at high temperature for a long time, and the same effect can be obtained. Furthermore, the above method can be applied not only to the formation of an impurity conductive layer by implanting impurity ions into an epitaxially grown layer, but also to the formation of a selective impurity conductive layer, and the same improvement effect can be expected.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are temperature control charts for conventional manufacturing methods, respectively, and FIG. 2 is a temperature control chart for explaining one embodiment of the present invention. Last check → '$2 closing → Call volume → Figure f

Claims (1)

[Claims] The step of forming an impurity implantation layer by ion implantation on a compound semiconductor substrate or a compound semiconductor substrate having an epitaxial growth layer, and forming an insulating protective film on the surface of the impurity implanting layer, and then the temperature at which this insulating protective film was formed. 1. A method for manufacturing a compound semiconductor device, comprising the steps of: forming an electrically active layer of implanted impurities by immediately and continuously performing high-temperature heat treatment.