JPH0547693A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To improve the performance of an element by doping it with impurities from an optional depth without affecting other parts of the elements at the surface of a substrate, an operating layer, etc. CONSTITUTION:The crystals of an AP dope layer 3 by p-type dopant, in a GaAs buffer layer 2, and the crystals of an AP dope layer 8 by n-type dopant, in 8n n-GaAs layer 7, are grown, and by annealing, with these AP dope layers 3 and 8 as diffusion layers, dopant is diffused to form a p-buried layer 9 and an n<+>-ohmic layer 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a substrate is doped with impurity atoms to form a p-type region or an n-type region.

[0002]

2. Description of the Related Art In impurity doping in the process of manufacturing a semiconductor device, an impurity profile is formed in the depth direction from the substrate surface. Conventional impurity doping methods include vapor phase diffusion, solid phase diffusion, and ion implantation. Since the impurities are diffused from the substrate surface in vapor phase diffusion and solid phase diffusion, only the impurity profile in which the impurity concentration on the substrate surface is high and decreases as it goes in the depth direction is obtained.

On the other hand, in the ion implantation method, a profile having a maximum impurity concentration can be formed at an arbitrary depth from the surface by controlling the implantation energy.
A layer embedded type ion implantation FET can be created.

However, in the ion implantation method, the crystal is damaged when high-energy impurities pass through the surface, and the damage is not completely recovered even by the high-temperature annealing treatment performed to activate the impurities. The crystal defects remain and have a great influence on the device characteristics.

The present invention has been made in order to solve such a problem, and the layer grown by the atomic plane doping is used as a diffusion source of impurities, so that other layers such as an operating layer of an element can be obtained. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of diffusing impurities from an arbitrary depth without affecting a portion.

[0006]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device, in which a p-type region or an n-type region is formed by doping an impurity,
An atomic plane dope layer is provided in a region to be formed into a p-type or an n-type, and the atomic plane dope layer is used as a diffusion source of impurities.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, an atomic plane dope layer made of an n-type or p-type dopant is formed in a region to be formed as an n-type or p-type,
The heat treatment is applied to diffuse the impurities using the atomic plane dope layer as a diffusion source. Therefore, the n-type or p-type region can be formed at any depth without damaging the surface of the substrate.

[0008]

The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 1 is a cross-sectional view showing a process of manufacturing an FET by the method of manufacturing a semiconductor device according to the present invention.

First, the 8000 Å buffer layer 2 is formed on the semi-insulating GaAs substrate 1 by crystal growth. The crystal growth is interrupted and a dopant having a large diffusion coefficient is used by a crystal growth method such as MBE or MOCVD. Atomic plane doping is performed, and an AP (atomic plane) doped layer 3 of p-type dopant is inserted.

As the dopant having a large diffusion coefficient, Se, Te or the like is used for forming the n-type region, and Zn or the like is used for forming the p-type region. The diffusion coefficient D (cm ² / sec) of each dopant is shown below. Se: D = 3.0 × 10 ³ e (−4.16 / kT) (however, k: Boltzmann's constant, T: absolute temperature) Te: D = 10 ⁻¹³ (at 1000 ° C.), 3 × 10 ⁻¹⁴ (at 580
℃) Zn: D ≒ 10 ^-8 (at 900 ℃), 10 ^-10 (at 700 ℃)

In this embodiment, after the buffer layer 2 containing the AP (atomic plane) doped layer 3 of p-type dopant is formed, the n-GaAs operating layer 4 is formed on the buffer layer 2 (FIG. 1 (a)). ).

A refractory metal gate 5 of W, Si or the like and a sidewall 6 of SiO ₂ or the like are formed on the n-GaAs operating layer 4 (FIG. 1).
(b)).

The n-GaAs layer 7 is grown by the selective crystal growth method, but the growth is interrupted and the AP-doped layer 8 of the n-type dopant is inserted (FIG. 1 (c)).

Next, an annealing device is used to diffuse the dopants using the AP-doped layer 3 of the p-type dopant and the AP-doped layer 8 of the n-type dopant as diffusion sources, respectively, and the n ⁺ ohmic layer 10 and the p-buried layer 9 are formed. Are formed (FIG. 1 (d)).

The diffusion distance d is d = (D · t) ^1/2 when the diffusion time is t (sec). Therefore, in order to diffuse 300 Å of each of the above dopants, Te:
0 seconds, 580 ℃ for 3 minutes, Se: 1000 ℃ for 36 seconds, Zn: 700 ℃ for 3 seconds
Annealing for 0.1 seconds is required.

FIG. 2 shows a BP-SAINT FET (p-layer-embedded SAINT FET) prepared by the method for manufacturing a semiconductor device according to the present invention.
FIG. In this example, the p-type dopant AP
Annealing is performed using the doped layer 11 as a diffusion source to form the p-buried layer 12
Is formed.

[0017]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the AP-doped layer is inserted into the layer in which the n-type or p-type region is to be formed and the annealing treatment is performed.
Since the impurities are diffused by using the doped layer as a diffusion source, the impurities can be diffused at an arbitrary depth, and a semiconductor element having a good performance without being damaged by the crystal damage on the substrate surface and the change in the impurity concentration can be obtained. It has an excellent effect of being obtained.

[Brief description of drawings]

FIG. 1 is a FET according to a method for manufacturing a semiconductor device according to the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing process of.

FIG. 2 is a cross-sectional view of a BP-SAINT FET manufactured by the method for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols] 1 GaAs substrate 2 GaAs buffer layer 3 AP-doped layer 4 n-GaAs operating layer 7 n-GaAs layer 8 AP-doped layer 9 p buried layer 10 n ⁺ ohmic layer 11 AP-doped layer 12 p buried layer

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a p-type region or an n-type region is formed by doping an impurity,
A method of manufacturing a semiconductor device, comprising: providing an atomic plane dope layer in a region to be formed into a p-type or an n-type, and using the atomic plane dope layer as a diffusion source of impurities.