JPS55111125A - Method for manufacture of semiconductor device - Google Patents

Method for manufacture of semiconductor device

Info

Publication number
JPS55111125A
JPS55111125A JP1836379A JP1836379A JPS55111125A JP S55111125 A JPS55111125 A JP S55111125A JP 1836379 A JP1836379 A JP 1836379A JP 1836379 A JP1836379 A JP 1836379A JP S55111125 A JPS55111125 A JP S55111125A
Authority
JP
Japan
Prior art keywords
temperature
furnace
atmosphere
rate
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1836379A
Other languages
Japanese (ja)
Inventor
Keizo Inaba
Yoshikazu Yanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1836379A priority Critical patent/JPS55111125A/en
Publication of JPS55111125A publication Critical patent/JPS55111125A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To improve characteristics and reliability by implanting impurity ions into the surface of a semiconductor substrate, then, performing high-temperature diffusion in a non-oxidizing atmosphere and oxidation at a slightly lower temperature in an oxidizing atmosphere continuously in the same furnace, thereby eliminating contamination.
CONSTITUTION: The following furnace-heating and furnace-cooling diffusions are performed in accordance with the temperature process shown in the Figure, after the formation of, for example, a B ion impanted layer 3 on an n--type Si substrate 1. A thin SiO2 layer 5 is formed on the base surface before the diffusion treatment by treating the device at for example, 780°C for 30 minutes in the wet O2 atmosphere. Then, p-type base layer 4 is formed by increasing the furnace temperature to 1,200°C or more at the rate of 5°C/min, by holding the device in a dry high-temperature N2 atmosphere of 1,200W1,250°C for specified time, and by performing the diffusion. Then, an oxide film 6 with the thickness of 4,000Å is formed on the base surface by decreasing the temperature to 1,050°C at the rate of, for example, 3W 4°C/min, and by holding the device in the wet O2 atmosphere at 1,000°C or less for specified time. Thereafter, the furnace temperature is decreased to the room temperature at the rate of 3W4°C/min.
COPYRIGHT: (C)1980,JPO&Japio
JP1836379A 1979-02-21 1979-02-21 Method for manufacture of semiconductor device Pending JPS55111125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1836379A JPS55111125A (en) 1979-02-21 1979-02-21 Method for manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1836379A JPS55111125A (en) 1979-02-21 1979-02-21 Method for manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55111125A true JPS55111125A (en) 1980-08-27

Family

ID=11969605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1836379A Pending JPS55111125A (en) 1979-02-21 1979-02-21 Method for manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55111125A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103123A (en) * 1981-12-16 1983-06-20 Nec Corp Manufacture of compound semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52109369A (en) * 1976-03-10 1977-09-13 Hitachi Ltd Manufacture of semiconductor device
JPS53102676A (en) * 1977-02-21 1978-09-07 Sony Corp Preventing method for lamination fault

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52109369A (en) * 1976-03-10 1977-09-13 Hitachi Ltd Manufacture of semiconductor device
JPS53102676A (en) * 1977-02-21 1978-09-07 Sony Corp Preventing method for lamination fault

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103123A (en) * 1981-12-16 1983-06-20 Nec Corp Manufacture of compound semiconductor device

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