JPH01243582A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce an interface level by a method wherein an ion of fluorine is implanted into polycrystalline silicon or a silicon. based heteromaterial and, after that, a heat treatment is executed. CONSTITUTION:An n-type epitaxial layer 2, a high-concentration p-type base contact diffusion layer 3a, a p-type base layer 3b and an oxide film 4 are formed one after another on a high-concentration n-type substrate 1; an n-type polycrystalline Si layer 6 is formed on a single-crystal substratum substrate 5 where a collector and the base layer have been formed. An ion of arsenic as an n-type impurity is implanted into the Si layer 6; a heat treatment is executed at about 850 deg.C for about 10minutes; As is introduced uniformly. An ion of fluorine is implanted into the Si layer 6; the fluorine is stopped. After the ion of fluorine has been implanted, a heat treatment is executed at 600-800 deg.C for about 30minutes; implantation damage is recovered; segregation of fluorine to an interface is promoted; a fluorine segregation layer 7 is formed. Then, the polycrystalline Si layer 6 is worked; only a prescribed region 6a is left.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a single crystal silicon bipolar transistor using polycrystalline silicon in the emitter section and a silicon-based hetero bipolar transistor. The present invention relates to a bonding structure between silicon and polycrystalline silicon or a silicon-based heteromaterial, and a method for forming the same.

[Conventional technology]

In recent years, silicon bipolar transistors (St
The high-speed performance of bipolar transistors has been significantly improved, with a cut-off frequency of 20 to 25 GH! have been developed to reach this level.

Currently, most of the S1 bipolar transistors use polycrystalline S1 in the emitter section. In order to dramatically improve the cutoff frequency in the future, it is necessary to reduce the base width, and at the same time, to avoid an increase in base resistance, it is necessary to increase the base concentration. In order to prevent the current amplification factor hrm from decreasing at this time, the introduction of a nine-hetero bipolar transistor (HBT) using a material with a band gap wider than 8% for the emitter is being considered.

At this time, the main conditions imposed on wide gap materials are:
In addition to having a wider bandgap than Si, it has fewer interface states at the hetero interface and low resistivity.

[Problem to be solved by the invention]

However, unlike the GaAs-based transistor, there is currently no decisive wide-gap material that satisfies these conditions in the Sl-based transistor, and this is due to the 5I
This makes HBT development difficult. Emitter materials proposed to date include amorphous and single crystal SiC, polycrystalline and single crystal SiOx.

There are hydrogenated amorphous St, single-crystal GaP, etc., but these are all still in the development stage, and it is unclear what material satisfies all of the requirements such as wide gap, low resistance, low interface state density, and thermal stability. No, it is still insufficient for practical use.

Therefore, the present invention has been made in view of the above-mentioned conventional problems, and its purpose is to
The characteristics of semiconductor devices and polycrystalline Sl emitters can be improved by reducing the interface states, even in the case of junctions between wide-gap heterogeneous materials and 81 single crystals.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain a large current amplification factor hym even when the base concentration is high.

[Means to solve the problem]

The semiconductor device according to the present invention comprises single crystal silicon, polycrystalline silicon, or at least one of oxygen, carbon, and nitrogen.
A layer containing fluorine is interposed on the bonding surface with a silicon-based hetero material containing fluorine.

Further, the semiconductor device according to the present invention includes single crystal silicon,
A thin silicon oxide film existing at the bonding interface or a layer containing a lower silicon oxide layer and containing fluorine is interposed on the bonding surface with polycrystalline silicon or a silicon-based hetero material containing at least one of oxygen, carbon, and nitrogen. This is what I did.

A method of manufacturing a semiconductor device according to the present invention is to form a layer containing fluorine at a junction interface by implanting fluorine ions into polycrystalline silicon or a silicon-based heteromaterial and subjecting the material to heat treatment.

[Effect]

In the present invention, fluorine ions are implanted into polycrystalline silicon or silicon-based heteromaterials as shown in FIG. A layer containing fluorine is segregated at the interface between the hetero material and single crystal silicon, an interfacial oxide film or a lower oxide layer, and reduces the interface state. Furthermore, this fluorine-containing layer has little effect on resistance and is thermally stable.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

(Example 1) FIG. 1 is a sectional view showing an example in which a semiconductor device according to the present invention is applied to an NPN bipolar transistor with a brainer structure having a polycrystalline S1 emitter. explain.

(1) N-type epitaxial layer 2 on high concentration n-type substrate 1
and a high concentration p-type base contact diffusion layer 3&.

A p-type base layer 3b and an oxide film 4 are sequentially formed on a single-crystal base substrate 5 on which collector and base layers are formed.
A type polycrystalline St layer 6 is formed.

(2) Arsenic (At) is added to the polycrystalline 81 layer 6 as an n-type impurity.
) is ion-implanted and heat treated at about 850° C. for about 10 minutes to make the distribution of Aa uniform.

(2) Inject fluorine ions (F+ ions) into the polycrystalline 81 layer 61 to stop F. Here, the thickness is approximately 0.3 μm.
About 50 KeV was implanted into the polycrystalline St layer 6a, and the implantation amount was 10 to 10 σ-2.

(4), After F+ ion implantation, about 30℃ at 600-800℃
A severe heat treatment is performed to recover the implantation damage and to promote the segregation of F to the interface to form the F segregation layer 7.

(5) Processing the polycrystalline St layer 6 to obtain a predetermined area 6!
Only L remains.

(6,) Hereinafter, a Tr is manufactured by a normal bipolar TrM manufacturing process such as formation of emitter, base, and collector electrodes.

In addition, in the above-mentioned process (2), it is also possible to push A3 into the single crystal S1 by further high-temperature heat treatment depending on C.Also, it is possible to add phosphorus Φ by P ion implantation. It is also possible to use polycrystalline S
Polycrystalline s1 doped with Am or P during deposition of the i-layer 6
But it is possible. Furthermore, arsenic monofluoride (As Fs) +
Using fluoride of n-type impurities such as coffee phosphorus (PF5) as a raw material,
It is also possible to add n-type impurities and F at the same time by implanting ions such as AsF+ and PF+. In this case, processes (3) and (4) described above can be omitted.

Further, as a method for adding F, it is also possible to use a molecular ion in which F is bonded to an element that does not serve as a donor or acceptor in 81, such as SIF. Here, it is also possible to bring processes (3) and (4) after process (5). Furthermore, it is also possible to bring processes (3) and (4) before process (2).

(Embodiment 2) FIG. 2 is a sectional view showing another embodiment in which the semiconductor device according to the present invention is applied to a PNP bipolar transistor with a planar structure having a polycrystalline S1 emitter. Let me explain.

(1) A p-type epitaxial layer 12 on a heavily doped p-type substrate 11 and a heavily doped n-type base contact diffusion layer 13a, n
A mold base layer 13b and an oxide film 14 are sequentially formed, and a polycrystalline Si layer 6 is formed on a single crystal base substrate 15 on which the collector and base layers have been formed.

(2) Boron (B) is added to the polycrystalline Si layer 6 as a p-type impurity.
) is ion-implanted and heat treated at about 800° C. for about 10 minutes to make the distribution of υB uniform. Note that, if necessary, it is also possible to push B into the single crystal S1 by high-temperature heat treatment. In addition, by ion implantation of BFI ions, B
It is also possible to add F and F into the polycrystalline 81 layer 6 at the same time.

(3) F+ ions are implanted into the polycrystalline St layer 6a, and F+ ions are implanted into the polycrystalline St layer 6a.
to stop. Here, a polycrystalline layer of silk with a thickness of about 0.3 6
Inject at about 50 V to a, and the injection amount is 10~
It was set at 10 3 .

(4) After the F+ ion implantation, heat treatment is performed at 600 to sooC for about 30 minutes to recover the implantation damage and to promote the segregation of F to the interface to form the F segregation layer 7.

0), the polycrystalline S1 layer 6 is processed so that only a predetermined region 6a remains.

(6) Hereinafter, a Si'rr is manufactured by a normal bipolar Tr manufacturing process such as formation of emitter, paste, and collector electrodes.

Note that in the embodiment described above, process (3).

It is possible to bring (4) after process 6), so that process (3) and (4) come after process (2).
) is also possible. Furthermore, BF
In the case of I ion implantation, process (3),
(4) can be omitted.

FIG. 3 shows the dependence of the current amplification factor hFl on the amount of F implanted in the transistors fabricated in Examples 1 and 2 described above. It is clear from the figure that the stain current amplification factor hr+e of Example 1.2 is 2 to 3 of that of the normal polycrystalline s1 emitter Tr.
We were able to double the amount.

(Example 3) In the above-mentioned example, the deposition of Kel polycrystalline silicon in process (1) was performed using the commonly used 5IH4+5.
It is deposited at around 400 to 700° C. by a CVD method using a gas such as 12Hs t 5IHzCtx or 5tcz4. At this time, the surface of the sl substrate is thinly oxidized during insertion into a reactor and up to deposition, so polycrystalline St
A thin oxide film is present at the interface between the substrate and the 81 substrate. Thereafter, the Tr is manufactured according to the process (2) described above and the following processes.

Therefore, in this embodiment, a laminated structure is formed of a thin oxide film including a polycrystalline S1 layer/F/single crystal 81 substrate.

(Embodiment 4) Still another embodiment in which the semiconductor device according to the present invention is applied to an NPN bipolar transistor having an emitter made of oxygen-doped silicon (OXSEF) formed by epitaxial growth will be described with reference to FIG.

In this embodiment, the polycrystalline 81 layer 6 in FIG. 1 is replaced with an OXSEF layer. I will explain below if I want to do it in process order.

(1) The base substrate 5 on which the collector and base layers have been formed is inserted into an ultra-high vacuum, and the natural oxide film is removed by heating or treatment with hydrogen plasma.

C2), oxygen gas is introduced, and in an oxygen atmosphere under reduced pressure (~
Molecular beam growth of St is performed at a substrate temperature of 400 to 600° C. at 1O−'Torr). Thereafter, after exhausting the oxygen gas, a polycrystalline Si layer 6 is deposited to a thickness of about 0.3 μm. At this time, n-type impurities such as Ai and P are simultaneously added by molecular beam doping, ionization doping, or a gas source. Well, here we used molecular beam growth, but
5IH4, 81*H・.

CVD using SIH*Ct or 5iC24, etc.
You may also use the law.

(3) Inject F+ ions into the polycrystalline Lunar 6 to stop F. Here, polycrystalline St with a thickness of about 0.3 μm is used.
For layer 6, implant at about 50 @V, the implant dose is 10
~10 σ-2.

(4) After the F+4 on-implantation, a heat treatment of about 30° C. is performed at 600 to 800° C. to recover the implantation damage and to promote the segregation of F to the interface to form the F segregation layer 7.

(5) Process the polycrystalline 5110XSEF layer so that only the predetermined region 6a remains.

(6) Hereinafter, a bipolar transistor is manufactured by a normal bipolar transistor manufacturing process such as formation of emitter, pace, and collector electrodes.

In the above-mentioned embodiment, NPNT was explained, but it is also possible to use the polycrystalline St layer in FIG. 2 as an OXS EF layer and apply it to PNPTr.

It goes without saying that the present invention can also be applied to Si-based hetero materials other than 0XSEP.

(Example 5) FIG. 4 shows another example in which the semiconductor device of the present invention is applied to a planar structure NPNTr in which an extremely thin oxide film layer is controlled and formed at the interface between a polycrystalline Si layer and a single crystal layer. This is a cross-sectional view showing the process.

(1) N-type epitaxial layer 2 on high concentration n-type substrate 1
and 3 m of high concentration p-type base contact diffusion layer.

A p-type base layer 3h and an oxide film 4 are sequentially formed, and the single-crystal base substrate 5 on which the collector and base layers have been formed is inserted into an ultra-high vacuum, and the natural oxide film is removed by heating or treatment with hydrogen plasma, etc. Remove.

(2), [Introducing elementary gas and in an oxygen atmosphere under reduced pressure (
~10 T·rr) to slightly oxidize the surface layer. An extremely thin oxide film layer or lower oxide layer with a film thickness of about 20A or less is formed by controlling the film thickness.

(3) A polycrystalline S1 layer 6 is deposited as is. here,
It is also possible to add impurities such as AI and B at the same time as depositing the polycrystalline 81 layer 6.

(4) Hereinafter, Process Q of Examples 1 and 2) A Tr in which a thin oxide film layer 8 in which F is segregated is formed by the following process.

With this configuration, the layer containing F and the position of the emitter/base pn junction can be selected independently.

That is, a pn junction is formed between the polycrystalline 81 layer 6a and the base layer 3b.
, 13b, and this interface can also be formed slightly closer to the base layers 3b and 13b. However, the effect becomes extremely large when the pn junction coincides with the interface or is close to the interface.

Further, according to such a method, the emitter resistance can be rounded with almost no change, and excellent high frequency characteristics can be obtained. Also,
Unlike hydrogen, it does not desorb during low-temperature heat treatment, so it has good thermal stability.

FIG. 5 shows the relationship between the current amplification factor hrm and the base Gummel number Gm. In the figure, the broken line represents NPNTr with a normal polycrystalline Si minimitter, and the solid line represents NPNTr formed through an F+ ion implantation process and then a heat treatment process. As is clear from the figure, the NPNTs according to the above-mentioned embodiments
r was able to increase the current amplification factor by 2-3 times compared to NPNTr with a normal polycrystalline S1 emitter. Similar effects were also obtained with PNPTr.

In addition, in the above-mentioned embodiment, oxygen gas was introduced,
Although the oxide film was formed under reduced pressure, the film may be formed under normal pressure or chemically formed using sulfuric acid or the like if controllability is good.

Further, in the above embodiment, polycrystalline S1 was used, but it goes without saying that an 81-based hetero material may be deposited instead of polycrystalline St.

Furthermore, although a planar structure Tr has been described, the present invention is not dependent on the structure of the Tr.

〔Effect of the invention〕

As explained above, according to the present invention, single crystal silicon, polycrystalline silicon, oxygen, and carbon.

A layer containing fluorine or a silicon oxide film present on the bonding surface is formed by implanting fluorine ions into polycrystalline silicon or silicon-based heteromaterial and heat-treating the bonding surface with a silicon-based heteromaterial containing at least one of nitrogen. Alternatively, by forming and interposing a layer containing a lower oxide layer and containing fluorine, a semiconductor device that satisfies all the requirements of wide gap, low resistance, low interface state density, and thermal stability and can be used satisfactorily for practical purposes can be created. Extremely excellent effects such as being made possible to be achieved can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part showing an embodiment in which a semiconductor device and its manufacturing method according to the present invention is applied to an NPN transistor, and FIG. 2 is a cross-sectional view of a main part of a PNP transistor showing another embodiment of the present invention. , FIG. 3 is a diagram showing the dependence of the current amplification factor hrm on the amount of fluorine implanted in the transistor according to the example, and FIG.
The figure is a cross-sectional view of a main part of an NPN transistor showing still another embodiment of the present invention, FIG. This figure shows the fluorine distribution after fluorine ion implantation, and FIG. 7 shows the fluorine distribution after heat treatment. DESCRIPTION OF SYMBOLS 1...High concentration n-type substrate, 2...N-type epitaaxial layer, 3a...High concentration p-type base contact diffusion layer, 3bII...p-type base contact layer, 4...Fist ·Oxide film,
5... Base substrate, 6e... Polycrystalline St layer, 6a...
. . . Predetermined area, 1 . . . F segregation layer, 8 . . . thin oxide film layer in which F is segregated. Patent applicant: Nippon Telegraph and Telephone Corporation Agent: Masaki Yamakawa (and one other person) 1/”l
+ ten ~
-Figure 5 Base is t, L Gs (cm -5) Figure 6 Figure 7

Claims (3)

[Claims] (1) In a semiconductor device having a junction between single crystal silicon and polycrystalline silicon or a silicon-based hetero material containing at least one of oxygen, carbon, and nitrogen, a layer containing fluorine is interposed on the junction surface. Characteristic semiconductor devices. (2) The semiconductor device according to claim 1, wherein the fluorine-containing layer includes a silicon oxide film or a lower silicon oxide layer present at the junction surface. (3) In a semiconductor device having a junction between single crystal silicon and polycrystalline silicon or a silicon-based heteromaterial containing at least one of oxygen, carbon, and nitrogen, fluorine ions are added to the polycrystalline silicon or silicon-based heteromaterial. A method for manufacturing a semiconductor device, comprising forming a layer containing fluorine at a bonding interface by ion implantation and heat treatment.