JPS5878457A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5878457A JPS5878457A JP17649481A JP17649481A JPS5878457A JP S5878457 A JPS5878457 A JP S5878457A JP 17649481 A JP17649481 A JP 17649481A JP 17649481 A JP17649481 A JP 17649481A JP S5878457 A JPS5878457 A JP S5878457A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- polycrystal
- base
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 238000000034 method Methods 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 10
- 150000004767 nitrides Chemical class 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
本発明はバイポーラトランジスタの製造方法に係わり、
特に高周波特性の改善、素ヲの微細化に好適な製造工程
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar transistor,
In particular, it relates to a manufacturing process suitable for improving high frequency characteristics and miniaturizing elements.
バイポーラトランジスタの高周波化の必要条件のひとり
は外部ベース抵抗を低減させることである。このため外
部ベースに高濃度ドープ領域を配置するが、従来の写真
蝕刻法を用いたパターン合せによる方法では１μｍ以下
の精度で配置するのは困難であり、また、同一物質を部
分的に化学エッチするサイドエツチングによる自己整合
方式では〔例えば、Ｈｓｕ ｅｔ ａ／、 ｓ ＩＥＥ
Ｅ Ｔｒａｎｓｏ、ＨＤ−２５［６］ （１９７８）
７２３参照〕、工、チ量の制御性に乏しいという難点が
あった。One of the requirements for increasing the frequency of bipolar transistors is to reduce the external base resistance. For this reason, a highly doped region is placed on the external base, but it is difficult to do so with an accuracy of 1 μm or less using conventional pattern matching methods using photolithography, and it is difficult to do so with an accuracy of less than 1 μm. In the self-alignment method by side etching [for example, Hsu et a/, s IEE
E Transo, HD-25 [6] (1978)
723], there was a problem in that the controllability of the amount of work and chi was poor.
本発明は、上記従来技術の問題点を解消するために、サ
イドエッチ量を多結晶シリコンの酸化量に置換して、制
御性の改善を図ったものであり、真正ベース領域に比し
遥かに高濃度に不純物をドープした外部ベースを、エミ
、り・ベース間の接合耐圧（■ＫＢＯ）の低下を来さな
い範囲で、エミ。In order to solve the problems of the prior art described above, the present invention aims to improve controllability by replacing the amount of side etching with the amount of oxidation of polycrystalline silicon, which is far more effective than the true base region. The external base doped with impurities at a high concentration is emittered to the extent that the junction breakdown voltage (■KBO) between the emitter and the base does not decrease.
りに極力近接させて、高精度に自己整合配置する方法を
提供することを目的とするものである。The object of the present invention is to provide a method for highly accurate self-alignment arrangement by placing the elements as close as possible to each other.
本発明の製造方法は・前記サイド・チ法午同様の方式で
はあるが、酸化プロセスが化学エツチングに比し遥かに
良好な制御性を有することから、サイドエッチする部分
を予め酸化物と化しておくことによって、高精度化を図
っている。The manufacturing method of the present invention is similar to the side etching method described above, but since the oxidation process has much better controllability than chemical etching, the portion to be side etched is converted into an oxide in advance. High accuracy is achieved by placing the
以下、本発明を実施例によって詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図（ａ）〜（ｆ）は本発明の一実施例を工程順に示
した素子断面の模式図である。図と対応させ工程順に説
明するが、説明を簡明にするため、半導体の導電形を規
定し、ｎｐｎ ）ランジスタについて述べるけれど、こ
れに限定されるものではなく、本発明の製造方法はｐｎ
ｐ ）ランジスタの場合にも適１５用されることは勿論
である。FIGS. 1(a) to 1(f) are schematic cross-sectional views of elements showing one embodiment of the present invention in the order of steps. Although explanations will be given in the order of steps in correspondence with the drawings, in order to simplify the explanation, the conductivity type of the semiconductor will be defined and an npn) transistor will be described, but the manufacturing method of the present invention is not limited to this.
p) Of course, it is also applicable to transistors.
（ａ）：ｎ形単結晶シリ、コン基板１（以下単に基板と
言う）の表面に薄Ｘ、１（例えば厚さ１０００人）シリ
コン酸化膜（５ＩＯＱ 、以下単に酸化膜と言う）２を
形成し、さらにその上にシリコン窒化膜（Ｓｔ、Ｎ、
、以下単に窒素膜と言う）３を例えばＣＶＤ法で１２０
０Ｊの厚さに形成する。窒化膜３の所定領域を残して他
の部分をエツチングにより除去し、次いで熱酸化を行な
ってフィールド酸化膜４を形成する。(a): A thin X, 1 (e.g. 1,000 layers thick) silicon oxide film (5IOQ, hereinafter simply referred to as oxide film) 2 is formed on the surface of an n-type single crystal silicon substrate 1 (hereinafter simply referred to as the substrate). Furthermore, a silicon nitride film (St, N,
, hereinafter simply referred to as a nitrogen film) 3, by, for example, the CVD method.
Formed to a thickness of 0J. Leaving a predetermined region of the nitride film 3, other parts are removed by etching, and then thermal oxidation is performed to form a field oxide film 4.
（ｂ） ： ＣＶＤ法と写真蝕刻法により、エミ、
りを形成する領域にのみ酸化膜５（厚さ１０００人）及
び多結晶シリコン（Ｓｌ）膜６（厚さ５０００．ｊ）を
形成する。(b): Emi, by CVD method and photo-etching method.
An oxide film 5 (thickness: 1000.j) and a polycrystalline silicon (Sl) film 6 (thickness: 5000.j) are formed only in the region where the film is to be formed.
（Ｃ）： 多結晶８ｉ膜６の表面部分を酸化膜７と化
、すとともに、内部に多結晶Ｓ１膜６′を残す。このと
き、酸化を促進させるため、多結晶Ｓｉ膜６には予め燐
（Ｐ）を原子濃度１％程度ドープしておく。(C): The surface portion of the polycrystalline 8i film 6 is turned into an oxide film 7, and the polycrystalline S1 film 6' is left inside. At this time, in order to promote oxidation, the polycrystalline Si film 6 is doped with phosphorus (P) in advance at an atomic concentration of about 1%.
次いで、酸化膜５．多結晶Ｓ１膜６／、酸化膜７をマス
クとして、硼素（Ｂ）イオンを窒化膜３．酸化膜２を通
して基板１に約７０ ｋｅＶでＩ Ｘ １０１６／ｃ＋
＋＋２打込み、外部ベース８を形成する。Next, oxide film 5. Using the polycrystalline S1 film 6/ and oxide film 7 as masks, boron (B) ions are applied to the nitride film 3. I x 1016/c+ at about 70 keV to the substrate 1 through the oxide film 2
++2 implantation to form external base 8.
（ｄ）：ＩＩ化膜７をエツチングにより除去し、露出し
た多結晶８ｉ膜６／をマスクとして窒化膜３をエツチン
グし、多結晶８ｉ膜６′の下部のみに窒化膜３′を残す
。(d): The II film 7 is removed by etching, and the nitride film 3 is etched using the exposed polycrystalline 8i film 6/ as a mask, leaving the nitride film 3' only under the polycrystalline 8i film 6'.
（ｅ）： 多、結晶Ｓｉ ６’ 、酸化膜５をエツチ
ングにより除去した後、窒化膜３′をマスクとしｗｅｔ
ｏ１１雰囲気中で１０００℃、約４０分間基板表面の選
択酸化を行ない、厚さ約３５０ＯＡの酸化膜９を形成す
る。この工程の加熱処理で生じる不純物拡散によって、
初期の外部ベース８の領域は広がり８′となる。(e): After removing the polycrystalline Si 6' and oxide film 5 by etching, wet etching is performed using the nitride film 3' as a mask.
The substrate surface is selectively oxidized at 1000° C. for about 40 minutes in an o11 atmosphere to form an oxide film 9 with a thickness of about 350 OA. Due to the impurity diffusion that occurs during the heat treatment in this process,
The initial area of the external base 8 becomes an extension 8'.
（ｆ）： 窒化膜３′、酸化膜２′をエツチングによ
り除去し、多結晶Ｓ１膵し０を例えばＣＶＤ法で約１０
００１の厚さに堆積する。この多結晶Ｓ１膜１０に砒素
（Ａｓ）イオンを８０ ｋｅＶで２Ｘ１０１６／Ｃ−打
込み、１０００℃、約１０分間の加熱処理を施こす。こ
の加熱処理により、多結晶Ｓ１膜１０をアニールすると
同時に、多結晶ＳｉよりＡｓを基板内に拡散させ、エミ
、り１１を形成（浅い急峻なエミ、りが形成される。）
する。更に、多結晶８ｉ膜１０を通してＢイオンを６５
ｋｅ■でｌＸｌ０”Ａ−打込んだ後アニールし、真正ベ
ース１２を形成する。(f): The nitride film 3' and the oxide film 2' are removed by etching, and the polycrystalline S1 layer 0 is etched by about 10% by CVD, for example.
Deposited to a thickness of 0.001 mm. Arsenic (As) ions are implanted into this polycrystalline S1 film 10 at 2×10 16 /C− at 80 keV, and heat treatment is performed at 1000° C. for about 10 minutes. Through this heat treatment, the polycrystalline S1 film 10 is annealed and, at the same time, As is diffused from the polycrystalline Si into the substrate, forming emitters and ridges 11 (shallow and steep emitters and ridges are formed).
do. Furthermore, 65 B ions are introduced through the polycrystalline 8i film 10.
After implanting lXl0''A- with ke■, annealing is performed to form the true base 12.
上記（ｅ） 、 （ｆ）の工程で、酸化やアニール等
の加熱処理時に生じる不純物拡散によって、初期の外部
ベース８の領域は広がり、外部ベース８′となるが、そ
の広がりが、選択酸化により形成される酸化膜９の先端
１３とほぼ一致するように、酸化膜９の形成条件等、種
々の処理条件を設定しておくことにより、所望の不純物
濃度で真正ベース１２と外、部ベース８′が連結される
。In the steps (e) and (f) above, the region of the initial external base 8 expands due to impurity diffusion that occurs during heat treatment such as oxidation and annealing, and becomes the external base 8', but this expansion is caused by selective oxidation. By setting various processing conditions such as the formation conditions of the oxide film 9 so as to almost coincide with the tip 13 of the oxide film 9 to be formed, the true base 12 and the external base 8 can be formed at a desired impurity concentration. ' are concatenated.
以上の工程を経て、本発明のバイポーラトランジスタが
完成する。Through the above steps, the bipolar transistor of the present invention is completed.
なお、上記実施例で、エミ、り形成後真正ベース形成を
行なっている理由について補足すると、トランジスタの
高周波化のためには浅いエミッタ。In addition, in the above embodiments, the reason why the true base is formed after the emitter is formed is that the emitter is shallow in order to increase the frequency of the transistor.
真正ベース接合形成が不可欠であり、そのための高濃度
にＡｓをドープした急峻な分布を有するエミッタを形成
するには、濃度依存拡散を有効に利用でき、また、良好
な電気的活性化率の得られる比較的高温処理（１０００
℃以上）が望ましいことと、真正ベース形成にはなるべ
（拡散が生じない比較的低温（９００℃以下）゛もしく
は短時間のアニールが望ましいことを両立させるためで
ある。Formation of a true base junction is essential, and in order to form an emitter doped with As at a high concentration and having a steep distribution, it is possible to effectively utilize concentration-dependent diffusion and to obtain a good electrical activation rate. relatively high temperature treatment (1000
This is in order to achieve both that it is desirable to have annealing at a temperature of at least 900° C. and a relatively low temperature (below 900° C.) at which diffusion does not occur or for a short time to form a true base.
本発明の自己整合方式によれば、こうしたエミッタを追
い越してベース形成を行なうことも容易である。According to the self-alignment method of the present invention, it is easy to form a base by overtaking such an emitter.
第２図は、前述した第１図（ｄ）の工程を一部変更した
場合の実施例で、外部ベース８が酸化膜（９）の先端（
１３）に達しない条件とし、真正ベース（１２）と外部
ベース（８′）の連結のための補助的な外部ベース１４
を設けたものである。このように従来構造と類似の構造
とすることもできる。FIG. 2 shows an embodiment in which the process shown in FIG.
13), and an auxiliary external base 14 for connecting the genuine base (12) and the external base (8').
It has been established. In this way, a structure similar to the conventional structure can be used.
以上説明した本発明の製造方法における各工程は、実施
例に限定されるものではない。すなわち、使用する工、
チング法によっては、酸化膜５を不要とする構造とする
ことも可能であり、更に、エミ１．タ、真正ベース形成
法としては、基板１に直゛接Ａｓを打込む方法や形成順
序を逆にした従来の方法も用い得る。また、アニールの
方法についても特に限定するものではない。なお、電極
形成などの他の工程については、周知の方法に依れば良
く、ここでは説明を省略した。Each step in the manufacturing method of the present invention described above is not limited to the examples. In other words, the technique used,
Depending on the etching method, it is possible to create a structure that does not require the oxide film 5, and furthermore, it is possible to create a structure that does not require the oxide film 5. As a true base forming method, a method of directly implanting As into the substrate 1 or a conventional method in which the formation order is reversed may also be used. Furthermore, there are no particular limitations on the annealing method. Note that other steps such as electrode formation may be carried out by well-known methods, and their explanations are omitted here.
以上述べたように、本発明によれば、不純物（ドーパン
ト）の拡散と同程度の制御性を有する酸化により、真正
ベースと外部ベースを自己整合的に配置しているので、
０．５μｍ程度以下の相対配置が可能となり（マスク合
せによる従来法に比し約４倍以上の高精度化となる）、
バイポーラトランジスタの高周波化、微細化に効果があ
る。As described above, according to the present invention, the intrinsic base and the extrinsic base are arranged in a self-aligned manner by oxidation that has the same controllability as impurity (dopant) diffusion.
Relative placement of approximately 0.5 μm or less is possible (approximately 4 times more accurate than the conventional method using mask alignment),
It is effective in increasing the frequency and miniaturizing bipolar transistors.
第１図（ａ）〜（ｆ）は本発明の一実施例を工程順に示
した素子断面の模式図、第２図は第１図（ｄ）の工程を
一部変更した実施例を示した素子断面の模式図である。
１・・・基板 ２，２′・・・酸化膜 ３，３′・・・
窒化膜４・・・フィールド酸化膜 ５・・・酸化膜 ６
，６′・・・多結晶シリコン膜 ７・・・酸化膜 ８．
８’、１４・・・外部ベース ９・・・酸化膜 １ｏ・
・・外結晶シリコン膜１１・・・エミッタ １２・・・
真正ベース １３・・・酸化膜の先端。
代理人弁理士 中 村 純之助
才１図
ｔ１図
１’２図Figures 1 (a) to (f) are schematic cross-sectional views of an element showing an example of the present invention in the order of steps, and Figure 2 shows an example in which the steps in Figure 1 (d) are partially modified. FIG. 3 is a schematic diagram of a cross section of an element. 1... Substrate 2, 2'... Oxide film 3, 3'...
Nitride film 4... Field oxide film 5... Oxide film 6
, 6'... Polycrystalline silicon film 7... Oxide film 8.
8', 14... External base 9... Oxide film 1o.
...External crystalline silicon film 11...Emitter 12...
Genuine base 13...Tip of oxide film. Representative Patent Attorney Junnosuke Nakamura Figure 1 Figure t1 Figure 1'2 Figure
Claims (1)
工程に於て、シリコン窒化膜を含む耐酸化膜を被覆した
単結晶シリコン基板表面上の所望の領域に多結晶シリコ
ン膜を設け、該多結晶シリコン膜の側部な含む表面を酸
化膜と化した後、この酸化膜で覆われた多結晶シリコン
膜をマスクとして外部ベースを形成するためのイオン打
込みを行なう工程、酸化膜を除去し多結晶シリコン膜を
露出させこれをマスクとして上記耐酸化膜を蝕刻し多結
晶シリコン膜の下部領域にのみ耐酸化膜を残す工程、多
結晶シリコン膜を除去した後、上記耐酸化膜をマスクと
して単結晶基板表面を選択酸化する工程、上記耐酸化膜
を除去しその部分にエミ、り及び真正ベースを形成する
工程を有し、外部ベースと真正ベースを所望の不純物濃
度域で自己整合的に連結することを特徴とする半導体装
置の製造方法。In the step of forming an emitter, a base, and a base of a bipolar transistor, a polycrystalline silicon film is provided in a desired region on the surface of a single-crystal silicon substrate coated with an oxidation-resistant film containing a silicon nitride film, and the polycrystalline silicon film is After converting the surface including the sides into an oxide film, ion implantation is performed to form an external base using the polycrystalline silicon film covered with this oxide film as a mask. A process in which the oxidation-resistant film is etched using this as a mask, leaving the oxidation-resistant film only in the lower region of the polycrystalline silicon film. After removing the polycrystalline silicon film, the oxidation-resistant film is used as a mask to etch the surface of the single crystal substrate. A step of selectively oxidizing the oxidation-resistant film, a step of removing the oxidation-resistant film and forming an emitter, an oxide, and a true base in that part, and connecting the external base and the true base in a desired impurity concentration range in a self-aligned manner. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17649481A JPS5878457A (en) | 1981-11-05 | 1981-11-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17649481A JPS5878457A (en) | 1981-11-05 | 1981-11-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5878457A true JPS5878457A (en) | 1983-05-12 |
Family
ID=16014640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17649481A Pending JPS5878457A (en) | 1981-11-05 | 1981-11-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5878457A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037775A (en) * | 1983-07-05 | 1985-02-27 | フエアチアイルド カメラ アンド インストルメント コーポレーシヨン | Production of wafer by injection through protective layer |
| JPS6076166A (en) * | 1983-10-03 | 1985-04-30 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
| JPS60160164A (en) * | 1983-10-15 | 1985-08-21 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
| JPS6286858A (en) * | 1985-10-14 | 1987-04-21 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JPH05235009A (en) * | 1992-02-20 | 1993-09-10 | Nec Corp | Manufacture of semiconductor integrated circuit device |
-
1981
- 1981-11-05 JP JP17649481A patent/JPS5878457A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037775A (en) * | 1983-07-05 | 1985-02-27 | フエアチアイルド カメラ アンド インストルメント コーポレーシヨン | Production of wafer by injection through protective layer |
| JPS6076166A (en) * | 1983-10-03 | 1985-04-30 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
| JPS60160164A (en) * | 1983-10-15 | 1985-08-21 | Rohm Co Ltd | Semiconductor device and manufacture thereof |
| JPH0362014B2 (en) * | 1983-10-15 | 1991-09-24 | Rohm Kk | |
| JPS6286858A (en) * | 1985-10-14 | 1987-04-21 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JPH05235009A (en) * | 1992-02-20 | 1993-09-10 | Nec Corp | Manufacture of semiconductor integrated circuit device |
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