JPS6154619A - Forming process of gallium arsenide p type conductive layer - Google Patents

Forming process of gallium arsenide p type conductive layer

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Publication number
JPS6154619A
JPS6154619A JP59177100A JP17710084A JPS6154619A JP S6154619 A JPS6154619 A JP S6154619A JP 59177100 A JP59177100 A JP 59177100A JP 17710084 A JP17710084 A JP 17710084A JP S6154619 A JPS6154619 A JP S6154619A
Authority
JP
Japan
Prior art keywords
film
implanted
gallium arsenide
protective film
refractive index
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59177100A
Other languages
Japanese (ja)
Inventor
Jiyunkou Takagi
悛公 高木
Yasuhito Nakagawa
中川 泰仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP59177100A priority Critical patent/JPS6154619A/en
Publication of JPS6154619A publication Critical patent/JPS6154619A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent the stochiometric ratio of GaAs from fluctuating by a method wherein, in order to form a P type GaAs layer on a compound semiconductor substrate, acceptor type impurity ion is firstly implanted by ion implanting process before heat-treatment, an Si3N4 film with refractive index of film in the range of 1.9-2.2 is formed as a protective film by plasma CVD process with film forming temperature not exceeding 300 deg.C. CONSTITUTION:In order to form a P type GaAs layer on a compound semiconductor substrate, acceptor type impurity ion such as Be, Mg, Zn, Cd etc. is firstly implanted by ion implanting process. Later before the heat-treatment to activate the implanted ion, an Si3N4 film with refractive index of film in the range of 1.9-2.2 is formed as a protective film on the overall surface of substrate by plasma CVD process with film forming temperature not exceeding 300 deg.C. Through these procedures, the stoichiometric ratio of formed P type GaAs layer may be stabilized to form specified P type GaAs layer.

Description

【発明の詳細な説明】 〈発明の技術分野〉 本発明は砒化ガリウム半導体におけるp型伝導層の形成
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for forming a p-type conductive layer in a gallium arsenide semiconductor.

〈発明の技術的背景とその問題点〉 砒化ガリウムに対するアクセプタ型不純物としては通常
、ベリリウム、マグネシウム、亜鉛、カドミウム等の■
族元素が知られており、これらの不純物をイオン注入法
によってドープしてp型伝導領域を形成した例が報告さ
れている。
<Technical background of the invention and its problems> Generally, acceptor-type impurities for gallium arsenide include beryllium, magnesium, zinc, cadmium, etc.
Group elements are known, and examples have been reported in which p-type conduction regions are formed by doping these impurities by ion implantation.

一般に砒化ガリウム半導体にイオン注入法を適用した場
合、注入時に誘起された格子欠陥が、その後の熱処理に
よっても完全には回復せず、又、更に不都合なことには
、熱処理時に砒素やガリウムが抜は出していくために基
板結晶内に多量の空孔が発生し、これら、或いはこれら
と注入不純物。
Generally, when ion implantation is applied to gallium arsenide semiconductors, lattice defects induced during implantation are not completely recovered even by subsequent heat treatment, and even more inconveniently, arsenic and gallium are extracted during heat treatment. A large number of vacancies are generated within the substrate crystal due to the removal of these vacancies, or these and the implanted impurities.

これらと基板原子との結合によって生じた複合欠陥が、
アクセプタやドナーとして作用するため、得られたイオ
ン注入層の特性は注入不純物の特性で決定されるものと
異なって複雑な挙動を示すことが多い。そこで、このよ
うな基板原子の抜は出しによる空孔の発生を抑え、同時
に注入不純物の抜は出しをも抑えて注入層の高品質化を
図る目的で、注入層の表面に絶縁性保護膜を被覆して結
晶性の熱回復を行う、キャップアニール法が考案されて
きた。
Complex defects caused by the bonding of these and substrate atoms are
Because they act as acceptors and donors, the properties of the resulting ion-implanted layer often exhibit complex behavior that differs from those determined by the properties of the implanted impurities. Therefore, in order to suppress the generation of vacancies due to the extraction of substrate atoms, and at the same time to suppress the extraction of implanted impurities and improve the quality of the implanted layer, an insulating protective film is applied to the surface of the implanted layer. A cap annealing method has been devised in which thermal recovery of crystallinity is achieved by coating the crystalline material.

又、一方では基板原子、特に砒素の抜は出しに着目して
、これを積極的に抑制する方法として、保護膜を用いる
ことなく、直接砒素圧雰囲気下で結晶性熱回復を行うキ
ャップレスアニール法が考案されている。
On the other hand, focusing on the extraction of substrate atoms, especially arsenic, as a method to actively suppress this, capless annealing is used to perform crystallization thermal recovery directly under an arsenic pressure atmosphere without using a protective film. A law has been devised.

本発明は、前者のキャップアニール法に関するものであ
るが、まず従来の方法について説明する。
The present invention relates to the former cap annealing method, and first, a conventional method will be explained.

、1砒化ガリウムに対して従来用いられてきた保護膜と
して、CVD  5402.CVD  AA20B 、
CVD−5i3N4.スパッタSiNx、スパッタAI
N等がある。これらの絶縁膜の生膜温度はCVD S 
i 02とCvD−A1203が400〜450℃、 
CVD 513N4は750℃、スパッタSiNxとス
パッタAINは約300℃である。砒化ガリウムの熱的
安定性は乏しく、500℃以上では明らかに基板の熱分
解が起こり、又、それ以下の三百数十度でもわずかな砒
素原子の解離が起こると考えられる。この意味で、75
0℃もの高温で形成するCVD  S+3N4では生膜
時にイオン注入基板より砒素原子やガリウム原子の解離
が起こり、砒化ガリウム結晶中には多量の砒素原子空孔
とGa原子空孔が発生するため、化学量論的組成比が大
幅に変動し、熱処理後に得られたp型伝導層は予測され
る厚さよりはるかに深く、キャリヤ変換効率が低い上に
深いトラップ準位が多いという好ましくない特性であっ
た。
, CVD 5402. as a protective film conventionally used for gallium monoarsenide. CVD AA20B,
CVD-5i3N4. Sputter SiNx, sputter AI
There are N etc. The raw film temperature of these insulating films is CVD S
i 02 and CvD-A1203 at 400-450°C,
CVD 513N4 is at 750°C, sputtered SiNx and sputtered AIN at about 300°C. Gallium arsenide has poor thermal stability; thermal decomposition of the substrate clearly occurs at temperatures above 500°C, and slight dissociation of arsenic atoms is thought to occur at temperatures below 300°C. In this sense, 75
In CVD S+3N4, which is formed at temperatures as high as 0°C, arsenic atoms and gallium atoms are dissociated from the ion-implanted substrate during the production of a living film, and a large number of arsenic and Ga atomic vacancies are generated in the gallium arsenide crystal. The stoichiometric composition ratio varied significantly, and the p-type conductive layer obtained after heat treatment was much deeper than expected, which had unfavorable characteristics such as low carrier conversion efficiency and many deep trap levels. .

一方、スパッタSiNxやスパッタAINは低温生膜が
可能であるが、注入層にスパッタ原子が導入されたり、
表面損傷を被る等の欠点がある。
On the other hand, sputtered SiNx and sputtered AIN can form low-temperature raw films, but sputtered atoms may be introduced into the injection layer,
There are disadvantages such as surface damage.

CVD S + 02とCvD−A1208は400〜
5oO℃の比較的低温で形成されるが、CvD−A12
03はこの生膜温度で砒素原子、次いでガリウム原子に
対する強い吸い出し効果をもっている。
CVD S+02 and CvD-A1208 are 400~
Although formed at a relatively low temperature of 5oO℃, CvD-A12
03 has a strong suction effect on arsenic atoms and then on gallium atoms at this biofilm temperature.

以上の理由により、アニール用保護膜としては従来より
CVD  5102が用いられる例が多かった。
For the above reasons, CVD 5102 has conventionally been used in many cases as a protective film for annealing.

以下、アニール用保護膜としてCVD 5I02を用い
た場合について説明する。
The case where CVD 5I02 is used as the annealing protective film will be described below.

まず、LECECファンドープ半絶縁性砒化ガリウム基
板備し、硫酸−過酸化水素水−水系エッチング液を用い
て基板表面を鏡面エツチングする。
First, a LECEC fan-doped semi-insulating gallium arsenide substrate is provided, and the surface of the substrate is mirror-etched using a sulfuric acid-hydrogen peroxide-water etchant.

次に、64Zn士イオンを加速エネルギー18QKeV
で1×10 α 注入する。この後SiH4と02ガス
をソースガスとして基板温度430℃で3500λの膜
厚を有するCVD 5i02膜を注入層表面に形成し、
これを保護膜としてN2気流中で750℃、800℃、
830℃、各15分のアニールを行った。
Next, the 64Zn ions were accelerated with an energy of 18QKeV.
Inject 1 × 10 α at After that, a CVD 5i02 film having a thickness of 3500λ was formed on the surface of the injection layer at a substrate temperature of 430°C using SiH4 and 02 gas as source gases.
This was used as a protective film at 750°C and 800°C in a N2 stream.
Annealing was performed at 830° C. for 15 minutes each.

かくして得られたZnn注入梨型砒化ガリウム層深さ方
向キャリア濃度分布を第2図に示す。
The carrier concentration distribution in the depth direction of the Znn-implanted pear-shaped gallium arsenide layer thus obtained is shown in FIG.

この第2図より明らかなように750℃の比較的低温の
アニールでは注入したZn原子の理論分布に近い浅いア
クセプタ分布が形成されているが、アニール温度の上昇
につれて基板のガリウム原子が急激にSiO2保護膜中
に外拡散するために基板結晶中にガリウム空孔が発生し
、この空孔に増速されてZn原子が急激に内部拡散する
。特に、通常G a A s集積回路の製造に用いられ
る830℃のアニール温度では、第2図で認められるよ
うに、表面近傍にキャリヤ濃度の落込みが発生し、同時
に多量のトラップ準位が導入される等の異常が起こって
、設計通りのp型層が得られないという不都合が生じた
As is clear from Fig. 2, when annealing at a relatively low temperature of 750°C, a shallow acceptor distribution close to the theoretical distribution of implanted Zn atoms is formed, but as the annealing temperature increases, gallium atoms in the substrate rapidly change to SiO2. In order to diffuse out into the protective film, gallium vacancies are generated in the substrate crystal, and Zn atoms are rapidly internally diffused by the vacancies. In particular, at the annealing temperature of 830°C, which is normally used in the production of GaAs integrated circuits, as seen in Figure 2, a drop in carrier concentration occurs near the surface, and at the same time a large number of trap levels are introduced. This resulted in the inconvenience that a p-type layer as designed could not be obtained due to abnormalities such as oxidation.

〈発明の目的〉 本発明は上記従来の問題点を除去した新規な砒化ガリウ
ムp型伝導層の形成方法を提供することを目的とし、こ
の目的を達成するため、本発明の砒化ガリウムp型伝導
層の形成方法は、砒化ガリウムにイオン注入法によりベ
リウム、マグネシウム、亜鉛、カドミウム等のアクセプ
タ型不純物を注入し、然る後、生膜温度が300℃以下
のプラズマCVD法によって膜屈折率が1.9〜2.2
の範囲に入る窒化シリコン膜を形成して保護膜として被
着し、熱処理を施すことによって優れた特性を有する砒
化ガリウムp型伝導層を形成するように成されている。
<Object of the Invention> An object of the present invention is to provide a novel method for forming a gallium arsenide p-type conductive layer that eliminates the above-mentioned conventional problems. The layer is formed by implanting acceptor-type impurities such as beryllium, magnesium, zinc, and cadmium into gallium arsenide using an ion implantation method, and then using a plasma CVD method at a raw film temperature of 300°C or less to reduce the refractive index of the film to 1. .9~2.2
A silicon nitride film falling within the range of 100 to 100% is formed, deposited as a protective film, and subjected to heat treatment to form a gallium arsenide p-type conductive layer having excellent characteristics.

即ち、本発明はキャップアニール法に於けるアニール用
保護膜に関して改善を加えたものであり、その特徴は、
300℃以下の低温プラズマCVD法によって形成した
屈折率1.9〜2.2の窒化シリコン膜をアニール用保
護膜として用いることにより、電気的特性に優れた砒化
ガリウムp型伝導層を実現し得るようにしたものである
That is, the present invention improves the annealing protective film in the cap annealing method, and its features are as follows:
By using a silicon nitride film with a refractive index of 1.9 to 2.2 formed by low-temperature plasma CVD at 300°C or lower as a protective film for annealing, a gallium arsenide p-type conductive layer with excellent electrical properties can be realized. This is how it was done.

〈発明の実施例〉 以下、本発明につき、実施例に基づいて詳細に説明する
<Examples of the Invention> The present invention will be described in detail below based on Examples.

まず、アニール用保護膜としてのプラズスCVD法によ
る窒化シリコン膜(以下、 PCVD −S i Nx
と表現する)の生膜方法について説明する。
First, as a protective film for annealing, a silicon nitride film (hereinafter referred to as PCVD-S i Nx
We will explain the biomembrane method (expressed as ).

装置は静電容量結合方式の平行平板型リアクタであり、
N2希釈のモノシランとアンモニアを反応ガスソースと
して用いた。N H3/S i H4ガス流量比は4と
し、基板温度とデボガス圧、RF電力を生膜パラメータ
として種々の屈折率を有するPCVD SiNx膜を形
成することができる。この時、生膜パラメータと屈折率
との相関は通常報告されているように、基板温度とデポ
ガス圧の上昇につれて屈折率は増加し、RF電力の増大
につれて、逆に屈折率は減少する。
The device is a capacitively coupled parallel plate reactor.
Monosilane diluted with N2 and ammonia were used as reactant gas sources. The N H3/S i H4 gas flow rate ratio is set to 4, and PCVD SiNx films having various refractive indexes can be formed using the substrate temperature, debo gas pressure, and RF power as biofilm parameters. At this time, as the correlation between biofilm parameters and refractive index is usually reported, the refractive index increases as the substrate temperature and the deposition gas pressure increase, and conversely decreases as the RF power increases.

以下、種々の屈折率をもつPCVD−5iNxをZnイ
オン注入層に対するアニール用保護膜として用いた場合
のアニール特性について説明する。
Hereinafter, annealing characteristics when PCVD-5iNx having various refractive indexes are used as an annealing protective film for a Zn ion-implanted layer will be described.

用いた砒化ガリウム基板はアンドープLEC法によるも
のであり、64Zn+イオン注入は130KeV、lX
l0  cIM (7)条件テ行ツタ。
The gallium arsenide substrate used was made by the undoped LEC method, and the 64Zn+ ion implantation was performed at 130 KeV and lX.
l0 cIM (7) Condition Te row ivy.

まず、基板温度を280℃として屈折率が1.8から2
.3の範囲のPCVD  SiNxを、それぞれ700
Aの膜厚で形成した後、830℃、15分間のアニール
を行った。屈折率1.8の膜質は化学当量比に近い組成
と思われるが、アニールの結果、微小ピンホールやクラ
ックが発生したため保護膜としては適用できなかった。
First, the substrate temperature is 280°C and the refractive index is 1.8 to 2.
.. PCVD SiNx in the range of 3, 700 each
After forming the film to a thickness of A, annealing was performed at 830° C. for 15 minutes. Although the film quality with a refractive index of 1.8 seems to have a composition close to the chemical equivalent ratio, it could not be used as a protective film because minute pinholes and cracks were generated as a result of annealing.

屈折率が1.9以上の膜ではこのような耐熱性不良はみ
られず、アニール後のイオン注入砒化ガリウム層表面は
良好な鏡面性を示したので、注入層のキャリヤ濃度分布
を調べた。その結果、屈折率が1.9〜2.2の範囲の
SiNx膜では0.25μm以下の浅いp型伝導層が得
られており、前述のCVD S r 02保護膜を用い
た従来例で認められたような異常なキャリヤ分布は観測
されなかった。更に、81組成比が増したと思われる屈
折率2.3以上のSiNx膜を適用した場合の注入層の
キャリヤ濃度分布は屈折率の増加につれて徐々に深くな
る傾向が現われた。
Such poor heat resistance was not observed in films with a refractive index of 1.9 or more, and the surface of the ion-implanted gallium arsenide layer after annealing showed good specularity, so the carrier concentration distribution of the implanted layer was investigated. As a result, a shallow p-type conductive layer of 0.25 μm or less was obtained with a SiNx film with a refractive index in the range of 1.9 to 2.2, which was found in the conventional example using the CVD S r 02 protective film mentioned above. No abnormal carrier distribution was observed. Furthermore, when a SiNx film with a refractive index of 2.3 or more, which is thought to have an increased 81 composition ratio, was applied, the carrier concentration distribution in the injection layer tended to gradually become deeper as the refractive index increased.

即ち、以上の結果より、1.9≦屈折率≦2.2の領域
で、830℃の高温アニール後も比較的注入Zn原子の
LSS分布に近い浅いキャリヤ濃度分布が得られること
が判明した。
That is, from the above results, it has been found that in the region of 1.9≦refractive index≦2.2, a shallow carrier concentration distribution relatively close to the LSS distribution of implanted Zn atoms can be obtained even after high-temperature annealing at 830° C.

次に膜層折率を1.9〜2.2に維持して、生膜温度を
変えた結果につき説明する。生膜温度としては200℃
から400℃を検討した。200℃〜300℃で形成し
たSiNx膜を用いた場合のキャリヤ濃度分布は前述の
280℃と同様、高濃度かつ、浅い良好な形状を示した
。第1図は生膜温度が300℃のSiNx膜を保護膜と
して、N2気流中で750℃、800℃、および、83
0℃の各温度で15分間アニールして得られたZn注入
層のキャリヤ濃度分布を示したものである。750℃で
も比較的キャリヤの活性化が促進されている他、830
℃迄アニール温度を上昇してもキーリヤ濃度分布の変動
(Zn原子の内部拡散)が非常に少い点が留意される。
Next, the results of changing the living membrane temperature while maintaining the membrane layer refractive index between 1.9 and 2.2 will be explained. The biofilm temperature is 200℃
to 400°C. The carrier concentration distribution when using the SiNx film formed at 200° C. to 300° C. showed a high concentration and a good shallow shape, similar to the case at 280° C. described above. Figure 1 shows the SiNx film with a biofilm temperature of 300°C used as a protective film, and the film heated to 750°C, 800°C, and 83°C in a N2 stream.
This figure shows the carrier concentration distribution of the Zn injection layer obtained by annealing at each temperature of 0° C. for 15 minutes. Activation of carriers is relatively promoted even at 750°C, and at 830°C
It should be noted that even if the annealing temperature is increased to .degree. C., the variation in the key layer concentration distribution (internal diffusion of Zn atoms) is very small.

一方、基板温度を300℃〜400℃まで上昇して形成
したSiNx膜を用いた場合には、CVD−8iO2膜
で認められたような深いキャリヤ濃度分布となり、明ら
かに、高温性膜に起因するイオン注入層表面からの基板
原子の解離と、それに助長された注入Zn原子の内部拡
散とが起こっていた。
On the other hand, when a SiNx film formed by raising the substrate temperature to 300°C to 400°C is used, a deep carrier concentration distribution like that observed in the CVD-8iO2 film is obtained, which is clearly caused by the high temperature film. Dissociation of substrate atoms from the surface of the ion-implanted layer and internal diffusion of implanted Zn atoms promoted by this dissociation occurred.

〈発明の効果〉 以上のように本発明は、砒化ガリウム基板の表面分解を
伴わない、300℃以下の低温プラズマCVDプロセス
を採用し、その生膜条件を1.9≦屈折率≦2.2に適
正化した窒化シリコン膜をZnイオン注入層アニール用
保護膜として用いることにより、G a A s化学当
量比の変動を防止してキャリヤ濃度分布に優れたp型伝
導層を形成することが出来るものである。
<Effects of the Invention> As described above, the present invention employs a low-temperature plasma CVD process of 300°C or less that does not involve surface decomposition of a gallium arsenide substrate, and the raw film condition is 1.9≦refractive index≦2.2. By using a silicon nitride film optimized for Zn ion implantation layer as a protective film for annealing, it is possible to prevent fluctuations in the GaAs chemical equivalence ratio and form a p-type conductive layer with excellent carrier concentration distribution. It is something.

なお、上記実施例ではアクセプタ型不純物として亜鉛を
用いた場合を説明したが、本発明はこれに限定されるこ
とな(、ベリリウム、マグネシウム、カドミウム等の他
のアクセプタ型不純物を用いても同様な効果を得ること
ができる。
Although the above embodiment describes the case where zinc is used as the acceptor type impurity, the present invention is not limited to this. effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるPCVD−5iNxを保護膜とし
て用いて得られたZnイオン注入層のキャリ中濃度分布
を示す図、第2図は従来法によるCVD−8iO2をZ
nイオン注入層のアニール用保護膜として用いて得られ
たp型伝導層のキャリヤ濃度分布を示す図である。 代理人 弁理士 福 士 愛 彦(他2名)0   0
.1   0.2   0.3   0.4L0.5吸
さ (、am) 第1図
Figure 1 shows the carrier concentration distribution of a Zn ion-implanted layer obtained using PCVD-5iNx according to the present invention as a protective film, and Figure 2 shows the carrier concentration distribution of a Zn ion-implanted layer obtained using PCVD-5iNx according to the present invention as a protective film.
FIG. 3 is a diagram showing the carrier concentration distribution of a p-type conductive layer obtained by using it as a protective film for annealing an n-ion implanted layer. Agent Patent attorney Aihiko Fuku (and 2 others) 0 0
.. 1 0.2 0.3 0.4L0.5 sucked (, am) Figure 1

Claims (1)

【特許請求の範囲】[Claims] 1、砒化ガリウムにイオン注入法によりアクセプタ型不
純物を注入し、然る後、生膜温度が300℃以下のプラ
ズマCVD法によって膜屈折率が1.9〜2.2の範囲
に入る窒化シリコン膜を形成して保護膜として被着し、
熱処理を施すように成したことを特徴とする砒化ガリウ
ムp型伝導層の形成方法。
1. Acceptor type impurities are implanted into gallium arsenide by ion implantation, and then a silicon nitride film with a film refractive index in the range of 1.9 to 2.2 is formed by plasma CVD at a raw film temperature of 300°C or less. is formed and deposited as a protective film,
1. A method for forming a gallium arsenide p-type conductive layer, the method comprising performing heat treatment.
JP59177100A 1984-08-24 1984-08-24 Forming process of gallium arsenide p type conductive layer Pending JPS6154619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59177100A JPS6154619A (en) 1984-08-24 1984-08-24 Forming process of gallium arsenide p type conductive layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59177100A JPS6154619A (en) 1984-08-24 1984-08-24 Forming process of gallium arsenide p type conductive layer

Publications (1)

Publication Number Publication Date
JPS6154619A true JPS6154619A (en) 1986-03-18

Family

ID=16025139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59177100A Pending JPS6154619A (en) 1984-08-24 1984-08-24 Forming process of gallium arsenide p type conductive layer

Country Status (1)

Country Link
JP (1) JPS6154619A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308913A (en) * 1987-06-10 1988-12-16 Sharp Corp Manufacture of semiconductor device
JPS63308912A (en) * 1987-06-10 1988-12-16 Sharp Corp Manufacture of semiconductor device
DE3844246A1 (en) * 1987-12-29 1989-07-13 Nippon Abs Ltd BRAKE FLUID PRESSURE CONTROL DEVICE FOR ANTI-LOCK BRAKING SYSTEMS OF VEHICLES

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308913A (en) * 1987-06-10 1988-12-16 Sharp Corp Manufacture of semiconductor device
JPS63308912A (en) * 1987-06-10 1988-12-16 Sharp Corp Manufacture of semiconductor device
DE3844246A1 (en) * 1987-12-29 1989-07-13 Nippon Abs Ltd BRAKE FLUID PRESSURE CONTROL DEVICE FOR ANTI-LOCK BRAKING SYSTEMS OF VEHICLES

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