JPS61172379A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enlarge the change of capacitance, to thin a P<+> type GaAs layer and to reduce parasitic resistance by forming a P-N junction with a steep narrow transition region to varactor diode and a lead type IMPATT diode. CONSTITUTION:An N<-> type GaAs layer 12 is formed onto an N<+> type GaAs substrate 11 through an epitaxial growth method so that carrier concentration is brought to 10<15>cm<-3> and thickness to approximately 4.5mum. Silicon is injected to the N<-> type GaAs layer 12, and an N-type GaAs layer 13 having 10<17>cm<-3> carrier concentration and approximately 0.5mum thickness is shaped through annealing. A P<+> type GaAs layer 14 is formed onto the N-type GaAs layer 13. An electrode such as an ohmic electrode 15 consisting of gold is applied, and the layers are removed through etching up to the N<+> type GaAs substrate 11 while using the electrode 15 as one part of a mask, thus shaping a mesa.

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a varactor diode and a lead type inbat diode.

BACKGROUND OF THE INVENTION Currently, varactor diodes are widely used as single frequency multiplication devices for tuning in microwave exaggeration devices and information electronic equipment such as TVs, VTRs, and CATVs. Invat diodes are also used as single oscillation and power amplification devices in microwave exaggeration devices.

These diodes generally have the structure and configuration shown in FIGS. 1 and 2. FIG. 1 is a cross-sectional structural diagram of these diodes, and FIG. 2 shows the distinction between n-type and p-type semiconductor regions shown in FIG. 1, and the thicknesses and typical carrier concentrations of these layers. In FIG. 1, electrode 1 is in ohmic contact with P-type layer 2, and electrode 4 is in ohmic contact with N-type layer 3. The n-type layer 3 is divided into an n-type substrate and an n-type active layer, and the carrier concentration of the n-type substrate is generally IX
IOCm or more, and the carrier concentration profile of the n-type active layer has a shape as shown in FIG. 2 as an example. The n-type active N forms a P-n junction with the P-type layer, and this P-n
By the reverse voltage applied to the junction, the varactor diode and the invat diode are operated mainly by utilizing the depletion layer that spreads in the n-type active layer.

Conventionally, in order to form a carrier concentration profile as shown in the 1M2 diagram, first, an n-type layer having a carrier concentration of IX10Cm is epitaxially grown on an n-type substrate, and then an ion implantation method is used to grow the n-type layer to a thickness of about 1x10 cm. An n-type layer is formed to form an n-type active layer, and a P+ type layer having a carrier concentration of l x 10''cm or more is epitaxially grown on the n-type active layer.

However, in this manufacturing method, the carrier concentration of the P type layer near the interface between the P+ type layer and the n type active layer does not rise sharply, and therefore I
In order to obtain a high carrier concentration layer, it was necessary to grow an r-type layer with an approximately 1 micron step step. For this reason, the capacitance change of the diode becomes small and the resistance of the P-type layer becomes large, making it impossible to sufficiently improve the performance of varactor diodes and invat diodes.

OBJECTS OF THE INVENTION The present invention has been made to overcome the above-mentioned drawbacks inherent in the prior art, and therefore, it is an object of the present invention to provide a new manufacturing method for forming a thin P-type layer, The purpose of this invention is to improve the performance of semiconductor devices such as varactor diodes and invat diodes.

Structure of the Invention In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention includes forming a semiconductor layer of one conductivity type in a semiconductor having the same conductivity type as the semiconductor and having a higher carrier concentration. a step of forming an xD shadow in the ion implantation method; and an atomic or molecular beam beam consisting of at least one constituent element of the semiconductor layer, at least a part of which is ionized, on the semiconductor layer; , a semiconductor layer exhibiting a conductivity type different from that of the semiconductor by using atoms or a molecular beam of an impurity element that can be ionized by interaction with the atoms or molecular beam and exhibit a conductivity type different from that of the semiconductor. and a step of providing an ohmic electrode on the epitaxially grown semiconductor layer.

EMBODIMENT OF THE INVENTION Hereinafter, one preferred embodiment of the present invention will be specifically explained with reference to the drawings. FIGS. 3(a) to 3(d) show an embodiment of the present invention, and are diagrams illustrating a method of forming a varactor diode using gallium arsenide (GaAs) as a semiconductor. In FIG. 3 (1), n-domain GaAs
On the substrate 11, n-type GaAsNl2 is formed by epitaxial growth, for example, to have a carrier concentration of 1011 cm''3 and a thickness of 45 μm.Next, as shown in FIG. 3(b), the n-type GaAsNl2 For example, silicon (hereinafter referred to as Si and T), which becomes an n-type impurity, is implanted into GaAs using an ion implantation method, and then annealing is performed to recover the implantation damage and activate the implanted impurity. For example, n-type GaAs 1@13 with a carrier concentration of JIEIO" cm and a thickness of about 0.5P is formed.

Next, as shown in FIG. 3(C), the n-type GaAs
A P+ decagonal aAs layer is formed on the layer 13, and an im-blunt epitaxial method is used as the formation method. The concept of this im-blunt epitaxial method will be explained using FIG. 4. In a high vacuum, a substance A22 such as As and a G
When the substance B23 a is evaporated using the high-temperature heating crucible 24, the evaporated gas of the substance B23, that is, the molecular beam beam, is emitted in the electron gas generated by applying a voltage between the cathode 25 and the seventh node 26. It is ionized by passing through it.

Next, a substance C27, such as zinc, is evaporated using a high-temperature heating lupus to produce an evaporated gas of this substance C2'7.

That is, by intersecting the molecular beam with the at least partially ionized substance B23, this substance C2
A part of the evaporated gas of No. 7 is ionized.

At this time, if the semiconductor substrate 21 or the holding jig for the semiconductor substrate is set to a negative potential, the gases of the ionized substance C27, the at least partially ionized substance B23, and the non-ionized substance A22 are placed on the semiconductor substrate 21. However, the semiconductor substrate 21 is heated to a high temperature of about 600°C, for example.
In other words, if material 22 and material B23 are chemically bonded and kept at a temperature that can form a single crystal, material A22 and material B2 will be formed.
3 grows as a single crystal on the semiconductor substrate, while the ionized substance B23 and substance C27 are accelerated toward the semiconductor substrate 21.

At the beginning of the deposition of the substance A22 and the substance B23 onto the semiconductor substrate 21, a so-called ion implantation phenomenon occurs. Damage to the semiconductor substrate 21 that normally occurs due to ion implantation phenomena does not occur due to the high temperature of the semiconductor substrate. Further, the semiconductor substrate 21 is made of the material W and the material B23. In the case of so-called compound semiconductors, if the impurity substance C27 occupies the lattice position of substance A22 and becomes activated and becomes a donor or acceptor, substance B23 is simultaneously implanted into the semiconductor substrate 21, so that substance C27 becomes active. The probability of occupying the lattice position of substance A22 increases,
An n-type or p-type semiconductor layer having an increased probability of becoming a donor or an acceptor and having a high carrier concentration can be formed on the semiconductor substrate.

When applying the implant epitaxial method shown in FIG. 4 to a single-element semiconductor, it is not necessary to use a high-temperature heating crucible containing the substance A22. Therefore, according to this instant epitaxial method, the surface of the semiconductor substrate is
It is possible to change the semiconductor layer to a type or n-type semiconductor, and then grow a p-type or n-type semiconductor thereon by epitaxial growth. In FIG. 4, Ga as substance A22,
If zn is used as substance B23 and substance C27, P-type Mt with zinc k as 7 receptors - first, Fig. 3 (
In step C), a p-type GaAs layer 14 can be formed on the surface region of the n-type oaAs layer 13, and then a p-type GaAs layer 14 can be epitaxially grown.

Next, as shown in FIG. 3(d), an ohmic electrode 15 made of, for example, gold is deposited on the P-type GaAs 14, and then this electrode 15 is removed by etching with an n-type GaAs substrate lit as part of a mask. When a mesa is formed, a varactor diode is completed.

The above explanation deals with the formation of a P-type layer, but
The same applies to the n+ type layer. When the semiconductor is silicon, it is most effective to use phosphorus, arsenic, gallium, and indium, which have large atomic numbers and are easily ionized, as the impurity substance C27.

Moreover, when GaAs is used as a semiconductor, germanium, selenium, tellurium-f f -force Y miraA.

Anine is effective as an impurity.

It is clear that the method for manufacturing a P-n junction, which is a part of the present invention, can be applied to devices other than varactor diodes and invat diodes having P-n junctions, and is effective in improving the performance of such devices. That's true.

Effects of the Invention From the above explanation, 1. By using the manufacturing method according to the present invention, it is possible to form a P-n junction with a steeply narrowed transition region, so that the capacitance change can be increased. Furthermore, since the thickness of the %P+ type QaAs layer can be reduced, parasitic resistance can be reduced. These advantages are also helped by the higher frequency and higher efficiency of invat diodes.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the structure of the diode, Figure 2 is M1
Figures showing the configuration of the semiconductor region of the diode shown in the figure, t43 (a) to (d) Fi process diagram showing an actual winding example of the present invention, No. 4
The figure shows the concept of the im-blunt epitaxial method, which is an important step of the present invention. 1.4... Electrode, 2... P+ type layer, 3... N type layer, 11... N+ type GaAs substrate, 12... N- type ()a
As layer, 13...n-type GaAs layer, 14...pj
n-type aAs layer, 15...ohmic electrode. 21... Semiconductor substrate, 22... Substance A, 23...
Substance B, 24... High temperature heating crucible, 25... Cathode, 26... Anode. n...Substance C

Claims (3)

[Claims] (1) A step of forming a semiconductor layer having the same conductivity type as the semiconductor and having a higher carrier concentration on a semiconductor of one conductivity type by ion implantation, and at least one constituent element of the semiconductor layer is formed on the semiconductor layer. an atomic or molecular beam consisting of a constituent element of the semiconductor layer, at least a part of which is ionized, and an impurity element that is ionized by interaction with the atomic or molecular beam and can exhibit another conductivity type in the semiconductor; A semiconductor device comprising the steps of: epitaxially growing a semiconductor layer exhibiting a conductivity type different from that of the semiconductor using an atomic or molecular beam beam; and providing an ohmic electrode on the epitaxially grown semiconductor layer. manufacturing method. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the semiconductor is silicon, and the impurity element is phosphorus, arsenic, gallium, or indium. (3) The method for manufacturing a semiconductor device according to claim (1), wherein the semiconductor is gallium arsenide, and the impurity is germanium, selenium, tellurium, tin, or cadmium.