JPS60254672A - Manufacture of fet - Google Patents
Manufacture of fetInfo
- Publication number
- JPS60254672A JPS60254672A JP11111884A JP11111884A JPS60254672A JP S60254672 A JPS60254672 A JP S60254672A JP 11111884 A JP11111884 A JP 11111884A JP 11111884 A JP11111884 A JP 11111884A JP S60254672 A JPS60254672 A JP S60254672A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- substrate
- active layer
- type layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 8
- 239000010410 layer Substances 0.000 abstract description 35
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000000370 acceptor Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電界効果型トランジスタの製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a field effect transistor.
従来例の構成とその問題点
第１図は、従来のＧ ａ Ａ ｓショットキーゲート型
電界効果トランジスタ（以下ＧａＡｇ ＭＥＳＦＥＴと
呼ぶ）の断面図を示したものである０１は半絶縁性Ｇ
ａ Ａ ｓ基板、２はバッフ１一層、３はｎ型活性層、
４，６．６はそれぞれソース電極、ドレイン電極、ゲー
ト電極を示す。従来２のバッファ一層としてはｎ−型（
電子濃度−１０１６〜１０”ｃｍ−３）が用いられてい
るが、ｐ−型（正孔濃度＜： １０ ”ｃｙｎ−’）層
の方が、バッファ一層を流れるリーク電流も少すく、活
性層３のキャリアプロフィールもバッファ一層付近で急
峻になるのでピンチオフ付近でのｐｍ も増加し都合が
よい。しかし、従来の気相。Structure of conventional example and its problems Figure 1 shows a cross-sectional view of a conventional GaAs Schottky gate field effect transistor (hereinafter referred to as GaAg MESFET).
aA s substrate, 2 is a buffer 1 layer, 3 is an n-type active layer,
4, 6.6 indicate a source electrode, a drain electrode, and a gate electrode, respectively. Conventional 2 buffer layer is n-type (
Although an electron concentration of -1016 to 10"cm-3) is used, a p-type (hole concentration <: 10"cm-3) layer has less leakage current flowing through the buffer layer, and the active layer Since the carrier profile of No. 3 also becomes steeper near the buffer layer, the pm near the pinch-off also increases, which is convenient. However, the conventional gas phase.
液相などの結晶成長方法では精度よくｐ−型層が成長で
きなかった。A p-type layer cannot be grown with high precision using a crystal growth method such as a liquid phase method.
発明の目的
本発明は、このような問題に鑑み、ｐ−型バッファ一層
を有したＧ ａ Ａ ｓ電界効果型トランジスタを再現
性良く製造する方法を提供するものである。OBJECTS OF THE INVENTION In view of these problems, the present invention provides a method for manufacturing a GaAs field effect transistor having a single p-type buffer layer with good reproducibility.
発明の構成
本発明は、半絶縁性ＧａＡｓ ＬＥＣ（ＬｉｑｕｉｄＥ
ｎｃａｐｓｕｌａｔｅｄ Ｃｚｏｃｈｒａｌａｓｋｉ）
基板を用い、これにＢイオンを注入して熱処理すること
により、表面層にｐ−型層を形成し、この上にｎ型活性
層をエピタキシャル成長させることにより、ｐ−型バッ
フ７一層を有するＧ ａ Ａ ｓ電界効果型トランジス
タを再現性良く製造する方法を可能とするものである。Structure of the Invention The present invention is a semi-insulating GaAs LEC (LiquidE
ncapsulated Czochralaski)
Using a substrate, a p-type layer is formed on the surface layer by implanting B ions into the substrate and heat-treating it, and by epitaxially growing an n-type active layer on this, a G layer having a p-type buffer 7 is formed. This enables a method of manufacturing an aAs field effect transistor with good reproducibility.
実施例の説明
以下、ショットキーゲート型ＦＥＴ （ＭＥＳＦＥＴ）
を例にとって説明する。第２図ａ−，ｄは本発明の実施
例を示したものである。１ず同図ａに示すように、半絶
縁性ＧａＡｓ Ｌ Ｅ Ｃ基板７を用いてＢを加速電圧
１８０ＫｅＶ、ドーズ量８Ｘ１ｏｃｒｎでイオン注入を
行ないＢ注入領域８を形成する。Description of Examples Below, Schottky gate type FET (MESFET)
will be explained using an example. FIGS. 2a-2d show embodiments of the present invention. First, as shown in FIG. 1A, a B-implanted region 8 is formed by ion-implanting B into a semi-insulating GaAs LEC substrate 7 at an acceleration voltage of 180 KeV and a dose of 8×1 ocrn.
次に同図すに示すように、ＣｖＤＳ１３Ｎ４膜９を保護
膜として８５０’Ｃ，’３０分間、Ａｒ雰囲気中でアニ
ールを行なうと、半絶縁性ＧａＡｇ ＬＥＣ基板７の表
面上Ｂ注入領域８の一部に、厚さ約６０００人、正孔濃
度１ｏ１４ｃｒｎ−５のｐ−型層１ｏが形成される。第
３図はこのｐ−型層の正孔濃度分布を示したものである
。次にＣＶ Ｄ Ｓ １３Ｎ ４膜９を除去後、第２図
Ｃに示すようにｎ型活性層３をエピタキシャル成長させ
、次に同図ｄに示すように、ソース電極４．ドレイン電
極５．ゲート電極６を順次形成してＭＥＳＦＥＴ を製
造するものである。Next, as shown in the figure, when annealing is performed in an Ar atmosphere at 850'C for 30 minutes using the CvDS13N4 film 9 as a protective film, part of the B implanted region 8 on the surface of the semi-insulating GaAg LEC substrate 7 is removed. A p-type layer 1o having a thickness of about 6000 nm and a hole concentration of 1014 crn-5 is formed in the area. FIG. 3 shows the hole concentration distribution in this p-type layer. Next, after removing the CV D S 13N 4 film 9, the n-type active layer 3 is epitaxially grown as shown in FIG. 2C, and then the source electrode 4. Drain electrode5. MESFET is manufactured by sequentially forming gate electrodes 6.
このように、半絶縁性Ｇ ａ Ａ ｓ基板としてＬＥＣ
法で成長したものを用い、Ｂ住人後アニールを行なうと
ｐ−型層が形成されるのは、本発明者が実験的にめたも
のであり、この原因としては、Ｂ注入領域の一部で、Ｌ
ＥＣ結晶で浅いアクセプターを補償している深いドナー
濃度が減少し、浅いアクセプターが補償されずｐ−型層
が形成されたものと考えている。In this way, LEC as a semi-insulating GaAs substrate
The present inventor experimentally found that a p-type layer is formed when annealing is performed after B inhabitation using a material grown by the B method. So, L
We believe that the deep donor concentration that compensates for the shallow acceptors in the EC crystal decreases, and that the shallow acceptors are not compensated for and a p-type layer is formed.
このように本発明の電界効果型トランジスタの製造方法
を用いると、ｐ−型層が容易に再現性よく形成され、こ
の上にｎ型活性層をエピタキシャル成長させることによ
り、ｐ−型バッファ一層を有するＧａＡｓ ＭＥＳＦＥ
Ｔを製造することが可能である。なお、Ｂイオン注入条
件を変化させると、ｐ−型層の厚さ、正孔濃度を変える
ことが可能である。As described above, by using the method for manufacturing a field effect transistor of the present invention, a p-type layer can be easily formed with good reproducibility, and by epitaxially growing an n-type active layer thereon, a p-type buffer layer can be formed. GaAs MESFE
It is possible to manufacture T. Note that by changing the B ion implantation conditions, it is possible to change the thickness of the p-type layer and the hole concentration.
なお、以上の説明ではＭＥＳＦＥＴ に限ったが、ｐｎ
接合ゲート型電界効果型トランジスタにも応用できるこ
とはいうまでもない。In addition, although the above explanation was limited to MESFET, pn
Needless to say, the present invention can also be applied to junction gate field effect transistors.
発明の効果
以上のように本発明は、半絶縁性ＧａＡｓ ＬＥＣ基板
を用い、これにＢを注入してアニールすることにより表
面にｐ−型層を精度良く形成し、この上にｎ型活性層を
エピタキシャル成長させることにより、ｐ−型バッファ
一層を有するＧ ａ Ａ ｓ電界効果型トランジスタを
再現性良く製造する方法を実現するものである。Effects of the Invention As described above, the present invention uses a semi-insulating GaAs LEC substrate, implants B into it and anneals it to form a p-type layer on the surface with high accuracy, and then forms an n-type active layer on this. By epitaxially growing a p-type buffer layer, a method of manufacturing a GaAs field effect transistor having a single p-type buffer layer with good reproducibility is realized.
第１図は従来のＧａＡｇ ＭＥＳＦＥＴの断面図、第２
図（−） 〜（ｄ）は本発明の一実施例のＧａＡｓ Ｍ
ＥＳＦＥＴの製造工程断面図、第３図はｐ−型層の正孔
濃度分布を示す図である。
３・・・・・・ｎ型活性層、４・・・・・・ソース電極
、６・・・・・・ドレイン電極、６・・・・・・ゲート
電極、７・・・・・・半絶縁性ＬＥＣ法Ｇ ａ Ａ ｓ
基板、８・・・・・・Ｂ注入領域、９・・・、・・ＣＶ
ＤＳｉ３Ｎ４膜、１０・・・・・・ｐ−型層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
（ｄＪ
第３図
表面ａ’ジの導さくメ町Figure 1 is a cross-sectional view of a conventional GaAg MESFET, Figure 2 is a cross-sectional view of a conventional GaAg MESFET.
Figures (-) to (d) show GaAs M according to an embodiment of the present invention.
FIG. 3, which is a sectional view of the ESFET manufacturing process, is a diagram showing the hole concentration distribution in the p-type layer. 3...N-type active layer, 4...Source electrode, 6...Drain electrode, 6...Gate electrode, 7...Half Insulating LEC method G a As
Substrate, 8...B injection region, 9...,...CV
DSi3N4 film, 10...p-type layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (dJ Figure 3 surface a')
Claims (1)
、前記基板にＢイオンを注入後アニールを行ない、前記
基板表面にｐ−型層を形成する工程と、前記ｐ−型層上
にｎ型層 ａ Ａ ｓ活性層をエピタキシャル、成長さ
せる工程を備えたことを特徴とする電界効果型トランジ
スタの製造方法。Using a semi-insulating GaAs substrate grown by the LEC method, annealing is performed after implanting B ions into the substrate to form a p-type layer on the substrate surface, and a step of forming a p-type layer on the p-type layer. A method for manufacturing a field effect transistor, comprising the step of epitaxially growing a type layer aAs active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11111884A JPS60254672A (en) | 1984-05-31 | 1984-05-31 | Manufacture of fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11111884A JPS60254672A (en) | 1984-05-31 | 1984-05-31 | Manufacture of fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60254672A true JPS60254672A (en) | 1985-12-16 |
Family
ID=14552875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11111884A Pending JPS60254672A (en) | 1984-05-31 | 1984-05-31 | Manufacture of fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254672A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114195A (en) * | 1994-07-11 | 2000-09-05 | Kabushiki Kaisha Toshiba | Manufacturing method of compound semiconductor field effect transistor |
-
1984
- 1984-05-31 JP JP11111884A patent/JPS60254672A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114195A (en) * | 1994-07-11 | 2000-09-05 | Kabushiki Kaisha Toshiba | Manufacturing method of compound semiconductor field effect transistor |
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