JPH0464455B2 - - Google Patents
Info
- Publication number
- JPH0464455B2 JPH0464455B2 JP59254364A JP25436484A JPH0464455B2 JP H0464455 B2 JPH0464455 B2 JP H0464455B2 JP 59254364 A JP59254364 A JP 59254364A JP 25436484 A JP25436484 A JP 25436484A JP H0464455 B2 JPH0464455 B2 JP H0464455B2
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- JP
- Japan
- Prior art keywords
- layer
- amorphous
- gaas
- crystal
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013078 crystal Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 17
- 238000010884 ion-beam technique Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000010894 electron beam technology Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 13
- 238000002955 isolation Methods 0.000 description 11
- 150000002500 ions Chemical group 0.000 description 9
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002164 ion-beam lithography Methods 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の素子間分離の方法に係
り、特にMBE（分子線エピタキシヤル結晶成長）
法により素子間分離領域を形成する半導体装置の
製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for separating elements in a semiconductor device, and particularly relates to a method for isolating elements in a semiconductor device, and in particular, MBE (Molecular Beam Epitaxial Growth).
The present invention relates to a method of manufacturing a semiconductor device in which an isolation region is formed by a method.
分子線エピタキシヤル結晶成長法を用いて作製
された結晶材料を用いて半導体装置を作る場合、
特に複数個の半導体素子をモノリシツクに集積化
する場合に、素子間分離が重要である。 When making a semiconductor device using a crystal material made using molecular beam epitaxial crystal growth method,
Particularly when a plurality of semiconductor elements are monolithically integrated, isolation between elements is important.
従来、一般的には第２図に示すようにメサエツ
チングで素子間分離を行なつている。図Ａにおい
て、半絶縁性GaAs基板１に順にｉ−GaAsバツ
フア層２，ｎ−GaAs活性層３をMBE法で形成
し、点線７のようにメサエツチングする。次に図
Ｂのごとく分離されたメサに素子を形成する。こ
れはFETの例であり、ソース・ドレイン電極４，
５及びゲート電極６が形成されている。
Conventionally, elements have generally been isolated by mesa etching as shown in FIG. In FIG. A, an i-GaAs buffer layer 2 and an n-GaAs active layer 3 are sequentially formed on a semi-insulating GaAs substrate 1 by the MBE method, and then mesa-etched as indicated by the dotted line 7. Next, elements are formed on the separated mesas as shown in Figure B. This is an example of a FET, and the source/drain electrodes 4,
5 and a gate electrode 6 are formed.
ところて、メサエツチングによる分離では、図
Ｂのようにメサエツチング部分で段差が生ずる欠
点がある。 However, separation by mesa etching has the disadvantage that a step is created at the mesa etching portion as shown in Figure B.
また、他の分離方法として、素子間分離をすべ
き結晶部分にイオン法入法等で所望のイオン原子
を注入することにより、該注入部分をアモルフア
ス化して高抵抗化する方法があり、或いは不純物
イオンを注入してｐ−ｎ接合化して素子間分離を
行なう方法がある。 Other isolation methods include implanting desired ion atoms into a crystal part where elements are to be isolated using an ion implantation method, thereby making the implanted part amorphous and increasing its resistance; There is a method of implanting ions to form a p-n junction to isolate elements.
ところが、これらの方法では各素子間分離部分
で段差がないプレーナ化が達成できるが、素子作
製工程における熱処理時に素子間分離部分の熱変
成や素子間分離部分の浮遊容量の増大等の欠点を
伴う。 However, although these methods can achieve planarization with no step difference in each element isolation part, they have drawbacks such as thermal transformation of the element isolation part and an increase in stray capacitance in the element isolation part during heat treatment in the element fabrication process. .
本発明は従来の分離方法の欠点、すなわち上述
のメサエツチングでは段差構造が配線等の断線の
原因となり、イオン注入法では熱処理時の熱変成
や浮遊容量の増大の欠点がある。本発明はこれら
の欠点が無い半導体装置の製造方法を提供しよう
とするものである。
The present invention has the disadvantages of conventional isolation methods, namely, the above-mentioned mesa etching has the disadvantage that the stepped structure causes disconnection of wiring, etc., and the ion implantation method has the disadvantages of thermal transformation during heat treatment and an increase in stray capacitance. The present invention aims to provide a method for manufacturing a semiconductor device that does not have these drawbacks.
本発明においてはMBE法を用いた半導体装置
の製造方法において、以下の工程を備える。
In the present invention, a method for manufacturing a semiconductor device using the MBE method includes the following steps.
半導体基板上にこれと同じ元素のアモルフアス
層を十数Å〜数十Åの厚みに形成する第１の工
程。 The first step is to form an amorphous layer of the same element on the semiconductor substrate to a thickness of several tens of angstroms to several tens of angstroms.
該半導体基板を第１の温度に加熱した状態で電
子線、イオン線、またはレーザ光線のビームを表
面の所望部分に照射して前記アモルフアス層の照
射部分のみを単結晶化する第２の工程。 A second step of irradiating a desired portion of the surface of the semiconductor substrate with an electron beam, ion beam, or laser beam while heating the semiconductor substrate to a first temperature to single-crystallize only the irradiated portion of the amorphous layer.
該半導体基板を第２の温度に加熱し、分子線エ
ピタキシヤル結晶成長により結晶成長を行ない、
前記第２の工程において単結晶化した部分には単
結晶層を成長し、他の部分にはアモルフアス又は
多結晶の高抵抗層が堆積沈着するように形成する
第３の工程。 heating the semiconductor substrate to a second temperature and performing crystal growth by molecular beam epitaxial crystal growth;
A third step in which a single crystal layer is grown in the portion that has been made into a single crystal in the second step, and an amorphous or polycrystalline high resistance layer is deposited in other portions.
前記第３の工程において、前記成長した単結晶
層内に半導体素子を形成する第４の工程。 A fourth step of forming a semiconductor element in the grown single crystal layer in the third step.
本発明によれば、第３の工程において、第２の
加熱温度を適当に選べば、分子線エピタキシヤル
結晶成長により、下地が単結晶化部分には単結晶
層が成長し、アモルフアス部分にはアモルフアス
又は多結晶層の沈着ができる。しかも、両層間で
の成長或いは沈着速度が一定であるため、完全に
平面の結晶基板を作ることができる。
According to the present invention, in the third step, if the second heating temperature is appropriately selected, a single crystal layer will grow in the portion where the base is single crystallized, and a single crystal layer will grow in the amorphous portion by molecular beam epitaxial crystal growth. Amorphous or polycrystalline layers can be deposited. Moreover, since the growth or deposition rate between both layers is constant, a completely flat crystal substrate can be produced.
第１図に本発明をGaAs結晶を用いた半導体装
置に適用する一実施例を示す。
FIG. 1 shows an embodiment in which the present invention is applied to a semiconductor device using GaAs crystal.
第１図Ａ参照
図Ａにおいて、まず最初に半絶縁性GaAs結晶
基板１１上にGaAsアモルフアス層１２を約30Å
沈着させる。沈着にはMBE装置を用いた。MBE
装置では基板結晶温度を約400℃以上にすると、
沈着したGaAsはアモルフアスとならずエピタキ
シヤル結晶化する。本発明ではアモルフアス化す
るのに結晶基板を室温度にしても可能であるが、
最終的に得られる結晶品質を向上させるために
は、アモルフアス層沈着時の結晶基板温度は室温
よりも150〜250℃の範囲にするのが最適である。Refer to FIG. 1A In FIG.
Deposit. An MBE device was used for the deposition. M.B.E.
In the device, when the substrate crystal temperature is increased to approximately 400℃ or higher,
The deposited GaAs does not become amorphous but epitaxially crystallizes. In the present invention, it is possible to make the crystal substrate amorphous even if it is kept at room temperature.
In order to improve the quality of the ultimately obtained crystal, it is optimal that the temperature of the crystal substrate during deposition of the amorphous layer is in the range of 150 to 250°C above room temperature.
第１図Ｂ参照
このアモルフアス層１２が形成されたGaAs結
晶基板１１を、電子線、イオン線又はレーザ光線
１４を用いて所望の部分を照射する。この照射時
にはGaAs結晶基板温度を300〜500℃の範囲に維
持して行うと良好な結晶のものを得る事ができ
る。１３が結晶化部分である。Refer to FIG. 1B. A desired portion of the GaAs crystal substrate 11 on which the amorphous layer 12 is formed is irradiated with an electron beam, an ion beam, or a laser beam 14. Referring to FIG. If this irradiation is carried out while maintaining the temperature of the GaAs crystal substrate in the range of 300 to 500°C, a good crystal can be obtained. 13 is a crystallized portion.
本実施例に於てMBE装置とイオン線描画装置
とを結合させておけば、アモルフアス層を沈着し
た後、真空を破ることなく、直接にイオン線描画
装置のステージに結晶基板を移して処理すること
ができる。このイオン線描画装置を用いて所望の
領域にイオン線を照射する場合、照射イオン種は
アモルフアス層の元素と同じガリウム（Ga+）又
は砒素（As+）イオンを用いるのが良い。イオン
種にGa+を用いた例において、照射加速電圧は
5KeV、ドーズ量５×1013cm-2となし、この時の
GaAs結晶基板温度は320℃とした。照射領域は
GaAs集積回路の場合、単体素子（FET）のソー
ス、ドレイン及び動作層形成予定領域の部分のみ
とする。 In this example, if the MBE device and the ion beam lithography device are combined, after depositing the amorphous amorphous layer, the crystal substrate can be directly transferred to the stage of the ion beam lithography device for processing without breaking the vacuum. be able to. When irradiating a desired region with an ion beam using this ion beam lithography apparatus, it is preferable to use gallium (Ga + ) or arsenic (As + ) ions, which are the same elements as the amorphous layer, as the irradiation ion species. In the example using Ga + as the ion species, the irradiation acceleration voltage is
5KeV, dose amount 5×10 13 cm -2 , at this time
The GaAs crystal substrate temperature was 320°C. The irradiation area is
In the case of GaAs integrated circuits, only the source, drain and active layer formation regions of the single element (FET) are covered.
第１図Ｃ参照
照射の終つたGaAs結晶基板の温度を400〜600
℃まで上げてGaAs層の結晶成長を行う。すると
イオン照射による単結晶化部分１３上には単結晶
１６，１７が成長するが、アモルフアス層１２上
にはアモルフアス層又はポリ層の沈着ができる。
なお、１６はｉ−GaAsバツフア層、１７はｎ−
GaAs動作層である。この単結晶１６，１７とア
モルフアス層１２の成長において、両層間での成
長あるいは沈着速度が一定であるため、完全に平
面の結晶基板を作ることが可能になる。図Ｃにお
いて単結晶のｎ−GaAs動作層１７にソース及び
ドレイン電極１８，１９をAuGe／Auのアロイ
により形成し、次にゲート領域にAl等のゲート
金属２０を蒸着により形成する。次に各素子を所
望の回路を構成するようにTi，Pt，Au等を用い
て配線を行なう。配線は全てアモルフアス層１５
の高抵抗領域上に形成する。本実施例により、良
好な素子間分離ができ、段差の無い完全プレーナ
化の集積回路を製造することができる。See Figure 1 C. After irradiation, the temperature of the GaAs crystal substrate is set to 400 to 600.
℃ to perform crystal growth of the GaAs layer. Then, single crystals 16 and 17 grow on the single crystallized portion 13 due to ion irradiation, but an amorphous layer or a poly layer is deposited on the amorphous layer 12.
Note that 16 is an i-GaAs buffer layer, and 17 is an n-GaAs buffer layer.
This is a GaAs active layer. In the growth of the single crystals 16, 17 and the amorphous layer 12, the growth or deposition rate between the two layers is constant, making it possible to produce a completely flat crystal substrate. In FIG. C, source and drain electrodes 18 and 19 are formed on the single crystal n-GaAs active layer 17 using an alloy of AuGe/Au, and then a gate metal 20 such as Al is formed on the gate region by vapor deposition. Next, each element is wired using Ti, Pt, Au, etc. so as to form a desired circuit. All wiring is amorphous layer 15
formed on the high resistance region of According to this embodiment, it is possible to achieve good isolation between elements and to manufacture a completely planar integrated circuit with no steps.
本発明の実施において、イオン線、電子線及び
レーザ光線を用いることができるが、それぞれの
特色及び条件を以下に示す。 In carrying out the present invention, ion beams, electron beams, and laser beams can be used, and the characteristics and conditions of each are shown below.
イオン線の場合
照射イオンにアモルフアス層の構成元素と同じ
元素のイオンを用いる。その際、注入イオンの量
を調製することによりアモルフアス層の組成、例
えばGaAsの場合、GaとAsの割合を変えること
ができる。GaとAsの割合を１：１からずらした
場合、アモルフアス層が単結晶化し難くすること
ができる。これを利用して、例えば第１図Ａにお
いてアモルフアス層１２のGa，Asの割合をずれ
た状態に沈着しておき、Ga+又はAs+イオンを図
Ｂで照射し、結晶化すべき部分のみがGa，Asの
割合が１：１となるようにすれば、該部が選択的
に単結晶化し、他部はアモルフアスのままにする
ことが容易となる。なお、イオン線による局所加
熱効果と物理的作用のみで単結晶化を行うことも
可能である。 In the case of ion beams, ions of the same element as the constituent element of the amorphous layer are used for irradiation. At this time, the composition of the amorphous layer, for example, in the case of GaAs, the ratio of Ga and As can be changed by adjusting the amount of implanted ions. When the ratio of Ga and As is shifted from 1:1, it is possible to make it difficult for the amorphous layer to become a single crystal. Utilizing this, for example, the amorphous layer 12 is deposited with different ratios of Ga and As in Figure 1A, and Ga + or As + ions are irradiated in Figure B, so that only the portion to be crystallized is deposited. If the ratio of Ga and As is set to 1:1, it becomes easy to selectively form a single crystal in that part and leave the other part amorphous. Note that it is also possible to perform single crystallization using only the local heating effect and physical action of the ion beam.
電子線の場合
ビーム径を細くしぼれる特徴があり、単結晶化
はアモルフアス層の電子線による局所加熱により
行なわれる。アモルフアス層の単結晶化を例えば
加速電圧10KV、ビーム径0.1μmで行なうことが
できる。 In the case of electron beams, the beam diameter can be narrowed, and single crystallization is achieved by local heating of the amorphous layer by the electron beam. Single crystallization of the amorphous layer can be carried out, for example, at an accelerating voltage of 10 KV and a beam diameter of 0.1 μm.
レーザ光線の場合 照射による局所加熱で選択的に単結晶化する。 For laser beams Selectively crystallizes into single crystals by local heating by irradiation.
実施例として、アモルフアス層の単結晶化例を
示す。 As an example, an example of single crystallization of an amorphous layer will be shown.
光 源 色素（Dye）レーザ
出 力 10〜100mW
ビーム径 0.1mm（基板上で）
次に本発明の実施の条件として、最初基板上に
形成するアモルフアス層（第１図Ａの１２）の厚
さは十分薄くする必要がある。これは、後でイオ
ン線等の照射をする際厚いと再結晶化しにくいた
めで、十数Å〜数十Åの厚みが良い。 Light source: Dye laser Output: 10 to 100 mW Beam diameter: 0.1 mm (on the substrate) Next, as a condition for implementing the present invention, the thickness of the amorphous layer (12 in Fig. 1 A) initially formed on the substrate is determined. needs to be sufficiently thin. This is because it is difficult to recrystallize the film if it is thick when irradiating it with an ion beam or the like later, so a thickness of about ten to several tens of angstroms is preferable.
以上において、主としてGaAsを用いた半導体
装置について説明したが、本発明は、多元混晶の
AlGaAs，InGaAs，InGaAsP，InAlAsP等にも
適用でき、シリコン（Si），ゲルマニウム（Ge）
等の半導体装置にも適用できる。以下に特にシリ
コンのMBEの場合の条件をあげると、
単結晶成長温度≧500℃
アモルフアス層又は多結晶層成長温度≦100℃
であり、これらを考慮して本発明を適用すると良
い。 In the above, the semiconductor device mainly using GaAs has been explained, but the present invention
Applicable to AlGaAs, InGaAs, InGaAsP, InAlAsP, etc. Silicon (Si), Germanium (Ge)
It can also be applied to semiconductor devices such as. The conditions for MBE of silicon are listed below: Single crystal growth temperature ≧500℃ Amorphous layer or polycrystalline layer growth temperature ≦100℃
Therefore, the present invention should be applied taking these into consideration.
更に、本発明について実施例は通常のGaAs
FETを示したが、他にヘテロ接合を用いた半導
体装置や超格子構造を用いた半導体装置、例えば
HEMT，ヘテロ接合バイポーラトランジスタ
（HBT）、多重量子井戸レーザダイオードや光電
子素子と半導体素子を組み合せたOEIC（Opto
and Electronic IC）にも応用可能である。特に
第３図にヘテロ接合バイポーラトランジスタを示
しており、この場合n+GaAs基板３１を用いてお
り、その表面に先に第１図において説明したと同
様な処理によりアモルフアス（GaAs）層１２と
単結晶化（GaAs）部分１３を形成し、MBEに
より順にn+−GaAsバツフア層３２，n-−GaAs
コレクタ層３３，P+−GaAsベース層３４，n+−
AlGaAsエミツタ層３５，n+−GaAsコンタクト
層３６を単結晶化部１３上に成長せしめ、その際
アモルフアスGaAs１２上には高抵抗なアモルフ
アス又は多結晶（GaAs）１５が沈着する。該ア
モルフアス又は多結晶（GaAs）１５により隣接
素子間が分離できる。 Furthermore, the embodiment of the present invention is based on ordinary GaAs.
Although FET is shown, there are other semiconductor devices using heterojunctions and superlattice structures, such as
HEMT, heterojunction bipolar transistor (HBT), multi-quantum well laser diode, and OEIC (optoelectronic) that combines optoelectronic and semiconductor devices.
It can also be applied to electronic and electronic ICs. In particular, FIG. 3 shows a heterojunction bipolar transistor, in which an n + GaAs substrate 31 is used, and a simple amorphous (GaAs) layer 12 is formed on the surface of the substrate by the same treatment as previously explained in FIG. A crystallized (GaAs) portion 13 is formed, and an n + -GaAs buffer layer 32 and an n - -GaAs buffer layer 32 are formed in order by MBE.
Collector layer 33, P + −GaAs base layer 34, n + −
An AlGaAs emitter layer 35 and an n + -GaAs contact layer 36 are grown on the monocrystalline portion 13 , with a high resistance amorphous or polycrystalline (GaAs) 15 deposited on the amorphous GaAs 12 . Adjacent elements can be separated by the amorphous or polycrystalline (GaAs) 15.
第４図に多重量子井戸レーザダイオードに本発
明を適用した断面構造を示す。図において、n+
−GaAs基板４１上に第１図におけると同様にア
モルフアス（GaAs）層１２を形成し、電子線、
イオン線又はレーザ光線で単結晶化パターニング
を行ない、単結晶化部分１３上にMBEによりn+
−GaAsバツフア層４２、N+AlGaAs層４３，Ｎ
−AlGaAs下部クラツド層４４，GaAs／
AlGaAs超格子層４５，ｐ−AlGaAs上部クラツ
ド層４６，p+−GaAs層４７を成長せしめ、その
際他の領域にはアモルフアス又は多結晶の高抵抗
層１５が沈着する。本例において、アモルフアス
又は多結晶の高抵抗層１５により隣接する他の素
子との分離が行なわれる。なおレーザ光は紙面に
垂直方向に放射される。 FIG. 4 shows a cross-sectional structure in which the present invention is applied to a multiple quantum well laser diode. In the figure, n +
- An amorphous (GaAs) layer 12 is formed on a GaAs substrate 41 in the same manner as in FIG.
Single crystallization patterning is performed using an ion beam or laser beam, and n + is formed on the single crystallized portion 13 by MBE.
−GaAs buffer layer 42, N + AlGaAs layer 43, N
-AlGaAs lower cladding layer 44, GaAs/
An AlGaAs superlattice layer 45, a p-AlGaAs upper cladding layer 46, and a p + -GaAs layer 47 are grown, with amorphous or polycrystalline high-resistance layers 15 being deposited in other regions. In this example, separation from other adjacent elements is achieved by an amorphous or polycrystalline high resistance layer 15. Note that the laser beam is emitted in a direction perpendicular to the plane of the paper.
本発明によれば以上のように、基板と同じ元素
のアモルフアス層を薄く形成し、所望部に電子
線，イオン線、レーザ線を照射して部分的に結晶
化し、その後MBEにより結晶成長を行なうこと
より結晶化部分には結晶が成長し、他の領域に高
抵抗なアモルフアス或は多結晶層が沈積し、該高
抵抗層を絶縁分離に使用できる（106〜107Ω・cm
以上の比抵抗で素子間分離ができる）。その場合
従来法のようにメサエツチによる段差形成を避け
ることができ、また素子間分離部の後工程での熱
変成や素子間分離部分の浮遊容量の増大の欠点を
なくすことができる。
According to the present invention, as described above, a thin amorphous layer of the same element as the substrate is formed, a desired portion is irradiated with an electron beam, an ion beam, or a laser beam to partially crystallize it, and then crystal growth is performed by MBE. In particular, crystals grow in the crystallized area, and a high-resistance amorphous or polycrystalline layer is deposited in other areas, and this high-resistance layer can be used for insulation isolation (10 6 - 10 7 Ωcm).
(Separation between elements can be achieved with the above specific resistance.) In this case, it is possible to avoid the formation of a step due to mesa etching as in the conventional method, and it is also possible to eliminate the disadvantages of thermal transformation in the subsequent process of the element isolation part and increase in stray capacitance in the element isolation part.
第１図Ａ〜Ｃは本発明の実施例の工程説明図、
第２図Ａ，Ｂは従来例の工程説明図，第３図及び
第４図はそれぞれ本発明の適用されるHBT及び
多重量子井戸レーザダイオードの断面図。
主な符号、 １１……半絶縁性GaAs結晶基板、
１２……（GaAs）アモルフアス層、１３……単
結晶化部分、１４……電子線、イオン線又はレー
ザ光線、１５……アモルフアス又は多結晶層（高
抵抗層）、１６……単結晶（ｉ−GaAsバツフア
層）、１７……単結晶（ｎ−GaAs動作層）、１
８，１９……ソース、ドレイン電極、２０……ゲ
ート金属。
FIGS. 1A to 1C are process explanatory diagrams of embodiments of the present invention,
2A and 2B are process explanatory diagrams of a conventional example, and FIGS. 3 and 4 are sectional views of an HBT and a multi-quantum well laser diode to which the present invention is applied, respectively. Main symbols: 11... Semi-insulating GaAs crystal substrate,
12... (GaAs) amorphous layer, 13... single crystallized portion, 14... electron beam, ion beam or laser beam, 15... amorphous or polycrystalline layer (high resistance layer), 16... single crystal (i -GaAs buffer layer), 17...Single crystal (n-GaAs active layer), 1
8, 19...source, drain electrode, 20...gate metal.
Claims (1)
方法であつて、 半導体基板上に該半導体基板と同じ元素のアモ
ルフアス層を十数Å〜数十Åの厚みに形成する第
１の工程と、 該半導体基板を第１の温度に加熱した状態で、
電子線、イオン線、またはレーザ光線のビームを
表面の所望部分に照射して該アモルフアス層の照
射部分のみを単結晶化する第２の工程と、 該半導体基板を第２の温度に加熱し、分子線エ
ピタキシヤル結晶成長により結晶成長を行ない、
その際、前記第２の工程において単結晶化した部
分には単結晶層が成長し、他の部分にはアモルフ
アス或いは多結晶の高抵抗層が沈着するように形
成する、第３の工程と、 前記第３の工程において、前記成長した単結晶
層内に半導体素子を形成する第４の工程との工程
の結合により形成されることを特徴とする半導体
装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device, comprising the following steps in order: forming an amorphous layer on a semiconductor substrate with the same element as that of the semiconductor substrate to a thickness of several tens of angstroms to several tens of angstroms; a first step, with the semiconductor substrate heated to a first temperature;
a second step of irradiating a desired portion of the surface with an electron beam, ion beam, or laser beam to monocrystallize only the irradiated portion of the amorphous layer; heating the semiconductor substrate to a second temperature; Crystal growth is performed by molecular beam epitaxial crystal growth,
At that time, a third step in which a single crystal layer is grown in the portion that has been single crystallized in the second step, and an amorphous or polycrystalline high resistance layer is deposited in other portions; A method for manufacturing a semiconductor device, characterized in that the third step is formed by combining the steps with a fourth step of forming a semiconductor element in the grown single crystal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25436484A JPS61131526A (en) | 1984-11-30 | 1984-11-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25436484A JPS61131526A (en) | 1984-11-30 | 1984-11-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61131526A JPS61131526A (en) | 1986-06-19 |
| JPH0464455B2 true JPH0464455B2 (en) | 1992-10-15 |
Family
ID=17263958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25436484A Granted JPS61131526A (en) | 1984-11-30 | 1984-11-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61131526A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0746684B2 (en) * | 1985-03-07 | 1995-05-17 | 日本電気株式会社 | Semiconductor wafer and manufacturing method thereof |
| JPH0810674B2 (en) * | 1987-11-09 | 1996-01-31 | 株式会社日立製作所 | Compound semiconductor substrate and manufacturing method thereof |
| JP2894801B2 (en) * | 1990-06-29 | 1999-05-24 | 日本電気株式会社 | Semiconductor transistor and method of manufacturing the same |
| JPH0661269A (en) * | 1992-08-11 | 1994-03-04 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JP2738379B2 (en) * | 1996-02-20 | 1998-04-08 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP2008306130A (en) * | 2007-06-11 | 2008-12-18 | Sanken Electric Co Ltd | Field-effect semiconductor device and its manufacturing method |
| JP2011171595A (en) * | 2010-02-19 | 2011-09-01 | Fujitsu Ltd | Method of manufacturing compound semiconductor device, and compound semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS528672A (en) * | 1975-07-09 | 1977-01-22 | Jidosha Seiki Kogyo Kk | Car washing device |
| JPS55901A (en) * | 1977-10-07 | 1980-01-07 | Hitachi Ltd | Data buffer control system |
| JPS5769784A (en) * | 1980-10-20 | 1982-04-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor light emitting device |
| JPS59116192A (en) * | 1982-12-21 | 1984-07-04 | Fujitsu Ltd | Crystal growth method by molecular beam |
-
1984
- 1984-11-30 JP JP25436484A patent/JPS61131526A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS528672A (en) * | 1975-07-09 | 1977-01-22 | Jidosha Seiki Kogyo Kk | Car washing device |
| JPS55901A (en) * | 1977-10-07 | 1980-01-07 | Hitachi Ltd | Data buffer control system |
| JPS5769784A (en) * | 1980-10-20 | 1982-04-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor light emitting device |
| JPS59116192A (en) * | 1982-12-21 | 1984-07-04 | Fujitsu Ltd | Crystal growth method by molecular beam |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61131526A (en) | 1986-06-19 |
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