JPS58143572A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To give the titled transistor the characteristics thereof will be applicable to the manufacture of super high speed transistor and an extra high speed integrated circuit by a method wherein AlAs is used instead of AlxGa1-xAs in order to prevent the lowering of electronic mobility due to the clustering in AlxGa1-xAs. CONSTITUTION:The point which is different from the structure heretofore in use is that AlAs is used instead of AlxGa1-xAs. In the same manner as in the case of structure heretofore in use, a two-dimensional electron gas layer 8 is formed in the vicinity of the AlAs/GaAs hetero interface. Moreover, as the AlAs layer is a two-element III-V group compound semiconductor, it has no clustering generating from mixed crystal as in the case of AlxGa1-xAs. Accordingly, the scattering of electron on the hetero interface is reduced, and a high-speed electrostatic transistor, which is higher in speed than AlxGa1-xAs/GaAs HEMT, can be manufactured. The thickness of a non-doped high purity GaAs layer 2 is 0.5-1mum, a non-doped AlAs layer 3a is 50-100Angstrom , an Si doped N type AlAs is 1-0.5mum, and the carrier density is 0.5-2X10<18>cm<-3> or thereabout.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor used as an element for, for example, an ultrahigh-speed computer.

Conventionally, high electron mobility transistors using a heterostructure include HEMT (High F#ctron), which uses a GaAs/AAGaAs single heterostructure.
MobilityTransistor). As shown in FIG.
) Non-doped high purity GaAs I@2 grown with
(thickness 0.8μm), non-doped 7UxGa, -XA8
Layer 3 (thickness 60A), St-doped 9n type -Ga, -
xAs l114 (x~0.3, thickness 0.1pm) (
The carrier concentration is 0.5 to 2×10” cat-3), and 5 and 6.7 are the source of the ohmic metal electrode, the metal gate of the Schottky junction, and the drain of the ohmic metal electrode.

A part of the electrons emitted from the n-ALxGal-XAs layer 4 transfers to the GaAs layer 2, which has a large electron affinity, and these electrons accumulate in the energy potential well on the GaAs layer 2 side of the heterointerface generated by this electron transfer, forming two-dimensional electrons. gas layer (
2DEG) 8. This region is partially undoped with impurities and has a high concentration of electrons, so scattering due to ionized impurities is significantly reduced and high mobility is achieved.

However, M and GaO clustering occurs in the AtxGal-XA three layer, although there are differences in degree depending on the growth method. In other words, microscopically, as shown in FIG. 2, in the mixed crystal with , single crystal regions of GaAs clusters marked with white circles and circular AAAs clusters marked with haunches form a mosaic shape. This clustering has a negative effect on the formation of 2DEG8 and electrons 9 are
A7XGal-xA through AaABO3aAs cluster
It also seeps into the s-layer 3 and becomes a scattering factor, reducing electron mobility.

The present invention solves the problem of decreased electron mobility due to clustering in AtxGal and As.
By using MA8 in place of s, a field effect transistor having characteristics applicable to the production of ultrahigh-speed transistors and ultrahigh-speed integrated circuits is provided.

The present invention will be explained in detail below.

FIG. 3 shows an embodiment of the present invention, which differs from the conventional structure in that IuAs is used instead of 1Ga1-XA8. In this structure as well, M
Two-dimensional electron gas 1 near the Mua/Ga'Aa hetero interface
#8 is formed. Moreover, the juAs layer is binary ■−v
Since it is a group compound semiconductor, MxGa
There is no clustering that occurs in mixed crystals such as 1xAs. Therefore, the scattering of electrons at the hetero interface is reduced, and A7
XGa, , As/GaAa HEMT also makes it possible to fabricate even higher-speed field transistors.

The non-doped high purity GaAs layer 2 has a thickness of 0.5 to lpm, the non-doped MMS layer 3a has a thickness of 50 to 100 A, the Si-doped n-type AtAs layer has a thickness of 0.1 to 0.5 μm, and the carrier concentration is 05 to zXIO. It is about 3-3.

As described above, at the AtAs/GaAs1 hetero interface of the field effect transistor according to the present invention, "
Since there is no reduction in the mobility of two-dimensional electrons due to the clustering of the x''t-x 8 layers, it becomes possible to easily realize a transistor with even higher mobility.

[Brief explanation of drawings]

Figure 1 is a vertical cross-sectional view showing an example of the structure of a high electron mobility transistor using a conventional heterostructure, Figure 2 is a schematic diagram illustrating the operating characteristics of the conventional example in Figure 1, and Figure 3. 4 is a longitudinal sectional view showing an embodiment of the present invention, and FIG. 4 is a schematic diagram for explaining the operating characteristics of the embodiment of FIG. 3. 1... Semi-insulating GaAs substrate, 2... Non-doped GaAs layer, 3... Non-doped Ga1-xAs layer, 4... Stdog n-1Ga1-XA8 layer, 5
...Source, 6...Gate, 7...Drain, 8
... Two-dimensional electron gas layer (2DEG), 9... Electron,
3a...Non-doped AtA s layer, 4a...n-type A
tA3 layer. Patent applicant: Nippon Telegraph and Telephone Public Corporation Agent: Tsune Hakumizu 1 male W 1 Figure 2 Flash 3 Figure η 4 Flash 303-

Claims (1)

[Claims] A 0.5-1 μm thick undoped high-purity GaAs layer, a 50-100 A thick undoped AAAs layer, and a 0.1-0.5 pm thick St layer on a semi-insulating GaAs substrate.
Doped n-type A7As layer (carrier concentration 0.5-2
A field effect transistor having a three-layer structure of 10" on-3) and having ohmic metal electrodes for a source and a drain placed on the three-layer structure with a metal gate of a Schottky junction sandwiched therebetween.