JPS58143573A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To give the titled transistor the characteristics which will be applicable to the manufacture of an extra high speed transistor and an extra high speed integrated circuit by a method wherein, in order to prevent the lowering of electron mobility caused by the clustering in AlxGa1-xAs, AlAs0.95P0.05 which was lattice-matched with GaAs is used instead of AlxGa1-xAs. CONSTITUTION:On a semiinsulating GaAs substrate 1, a non-doped high purity GaAs layer 2 of 0.5-1mum in thickness, a non-doped AlAs0.95P0.05 layer 3 of 50-100Angstrom in thickness which was lattice-matched to GaAs, an Si-doped N type AlAs0.05P0.05 layer 4a (carrier density of 0.5-2X10<18>cm<-3>) of triple-layer construction, and an ohmic metal electrode of a source and drain, arraged on said tripe-layer structure pinching the metal gate of a Schottky junction, are provided. On the AlAs0.95P0.5/GaAs hetero interface of this field-effect transistor, there is no lowering of two-dimensional electron mobility caused by the clustering of the AlxGa1-xAs layer which is experienced in the case of AlxGa1-xAs/ GaAs heretofore in use, and the generation of a dislocation and a defect on the hetero-interface is small because a lattice-matching was performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor used, for example, as an element for an ultra-high speed combinator.

Conventionally, high electron mobility transistors using heterostructures include HEMTs (high electron mobility transistors) using GaAa/AAGaAs nanostructures.
MobilityTransistor). As shown in FIG.
Non-doped high purity IJI' GaAs grown in y)
Layer 2 (thickness 0.8 μm) non-doped AtxGa1-xA
s-layer 3 (thickness 60A) l and St-doped i-type At
xGa1-XAsAs layer x~0.3. thickness 0.1pm)
(Carrier concentration 0.5-2 x 10"cm-"
), and 5, 6.7 are the source of the ohmic metal electrode, the metal gate of the Shilnotki junction, and the drain of the ohmic metal electrode.

A part of the electrons emitted from the Si non-doped layer-AtxGa1-xAs layer 4 is formed in a non-doped GaAj layer with a large electron affinity.
Moving on to layer 2, the G of the hetero interface created by this electron transfer
These electrons accumulate in the energy potential well on the aAs layer 2 side, forming a two-dimensional electron gas layer (2DEC) 8. This region is partially undoped with impurities and has a high concentration of electrons, so scattering due to ionized impurities is significantly reduced and high mobility is achieved.

However, in the mXca, -XAs layer, clustering of M and Ga occurs to varying degrees depending on the growth method. In other words, in this mixed crystal, microscopically, the second
As shown in the figure, a single crystal region of GaAs (white circles) and AtAs (hatched circles) forms a mosaic. This clustering has a negative effect on the formation of 2DEG8, and the electron 9 cancer ~ Ga1-XA8 layer 3 GaAs
It also seeps into the AtxGal-XAs layer 3 through the clusters, becoming a scattering factor and reducing electron mobility. There is also an example of using AtAa instead of ktXGal-XAs to solve the mobility decrease caused by clustering, but in this case, the lattice mismatch between GaAs and A7Aa causes dislocations and defects to occur at the hetero interface, which causes electron movement to increase. The degree decreases.

The present invention relates to clustering in A7XGa, As.

Aj, Ga I-x A
(lattice matched to GaAa instead of tXGa1-XAs)
By using dlAm o, s s Po, and o s, a field effect transistor having characteristics applicable to the production of ultra-high speed transistors and ultra-high speed integrated circuits is provided.

The present invention will be explained in detail below.

Fig. 3 shows an embodiment of the present invention, and the difference from the conventional structure is that GaAs is used instead of the Ga1-xAs layer 3.4.
Layer 3a of uA8g, g5 pa05 lattice matched to
4a is used. In this structure as well, /L4A as in the conventional ktxGa1□x As /GaAs
8(1g5P(1o5/GaAl1 Ga at the hetero interface
A two-dimensional electron gas layer 8 is formed near As.

Since A7Aa, ), 95po, and os are lattice matched with GaAs, there are few dislocations and defects that reduce electron mobility near the GaAs at the hetero interface.

Also) A-ZAaQ, Q5p0.05 but AjxGal-
It is thought that rastering occurs as seen in XAs as shown in Figure 4, but the A7As clustering shown by the hatched circles and the AI shown by the dotted circles.
1. Both P clusters have higher bandgap energies than GaAa, and AtXGa1□A through GaAs clusters as seen in Ga1-XAs.
There is no seepage of electrons into the 8th layer. Therefore, there is no decrease in two-dimensional electron mobility due to clustering, and AtxGal
, it becomes possible to fabricate a field transistor even faster than an As/GaAs HEMT.

As mentioned above, at the AtAso,g5PG,05/GJLA8 heterointerface of the field effect transistor according to the present invention, the conventional AtxGal,,As/
AI-zGa (-z A') as seen in GaAa
There is no reduction in two-dimensional electron mobility caused by layer clustering, and lattice matching reduces the occurrence of dislocations and defects at heterointerfaces, making it easier to realize higher mobility transistors. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing an example of a conventional field effect transistor, FIG. 2 is a schematic diagram for explaining the operation of the field effect transistor shown in FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a schematic diagram for explaining the operation of the embodiment shown in FIG. 3. l... Semi-insulating GaAs substrate, 2... Non-doped G
aAs layer, 3... non-doped AZxGal-xAs layer, 4- Si 'to'-1n type M engineering Ga1-8Aa layer,
5... Source, 6... Base, 7... Drain,
8...Non-doped-Ga1-XAs layer, 3a...)
/doped, vAS(1,s Po, o 5 layers, 4a −
・-Si-doped n-type J'J-As O, 95P005 layer O Patent applicant: Nippon Telegraph and Telephone Public Corporation Agent: Tsune Hakusui, 1 person outside II, 2nd, 3rd, 3rd, 4th,

Claims (1)

[Claims] On a semi-insulating GaAs substrate, there is a 0.5-1 μm thick undoped high-purity GaAs layer and a 50-100 μm thick undoped ALA that is lattice matched to GaAs! IO, 65Po
, 05 layer, and 0.1-05 μm thick GaAs lattice-matched Si-doped h-type kLAB6.65P@66 layer (carrier concentration 0.5-2 x 10” Fd).
A field effect transistor that has a layered structure and includes ohmic metal electrodes for the source and drain, which are placed on top of the three-layer structure with a metal gate in the form of a metal junction.