JP2009049121A - Heterojunction type field effect transistor and production method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction type field effect transistor in which an AlN layer or an Al<SB>x</SB>Ga<SB>1-x</SB>N layer (wherein, x is 0.6 or more) is used as an electron donating layer. <P>SOLUTION: This heterojunction type field effect transistor comprises a laminate 30 produced by laminating a first GaN layer which is a channel layer 40, an AlN layer which is an electron donating layer 50 and a second GaN layer which is a cap layer 60 in this order. In addition, according to another preferred embodiment of the heterojunction type field effect transistor of the present invention, the heterojunction type field effect transistor comprises a laminate produced by laminating a first GaN layer which is a channel layer, an Al<SB>x</SB>Ga<SB>1-x</SB>N layer (wherein, 0.6≤x<1) which is an electron donating layer and a second GaN layer which is a cap layer in this order. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a heterojunction field effect transistor and a method for manufacturing the heterojunction field effect transistor, and in particular, a heterojunction type in which an electron supply layer is an AlN layer or an Al _x Ga _1-x N layer (0.6 ≦ x <1). The present invention relates to a field effect transistor and a manufacturing method thereof.

  A conventional heterojunction field effect transistor will be described with reference to FIG. FIG. 11 is a schematic view for explaining a conventional heterojunction field effect transistor, and shows a cut end face of a main part.

  The heterojunction field effect transistor 110 is configured by sequentially stacking a GaN layer as a channel layer 140 and an AlGaN layer as an electron supply layer 150 on a base 120. The heterojunction field effect transistor 110 has a heterostructure of an AlGaN layer that is the electron supply layer 150 and a GaN layer that is the channel layer 140. According to this structure, the two-dimensional electron gas (2DEG) formed at the heterointerface 142, which is the interface between the channel layer 140 and the electron supply layer 150, has a high concentration and high electron mobility. Good characteristics as a mobility transistor. Hereinafter, a high electron mobility transistor, which is a heterojunction field effect transistor having an AlGaN / GaN heterostructure, may also be referred to as an AlGaN / GaN-HEMT (High Electron Mobility Transistor).

  On the electron supply layer 150, a source electrode 182 and a drain electrode 184 formed by ohmic junction, and a gate electrode 180 formed by Schottky junction are provided. The AlGaN / GaN-HEMT 110 is separated from other elements by, for example, an element isolation region 135 formed by implanting impurities into the channel layer 140 and the electron supply layer 150. A silicon nitride film is formed as a surface protective film 190 on the upper surface 152 of the electron supply layer 150.

For example, when the composition of the electron supply layer 150 is Al _x Ga _1-x N (x = 0.25), when the thickness (active layer thickness) a of the electron supply layer is 25 nm, the 2DEG concentration is about 1 0.0 × 10 ¹³ cm ⁻² and the electron mobility is 1500 cm ² / V · s.

  It is known that increasing the cutoff frequency is effective for increasing the frequency of the FET, and shortening the gate length Lg is most effective for increasing the cutoff frequency.

  Here, when the gate length Lg is shortened, a short channel effect such as poor pinch-off characteristics and a negative shift of the threshold voltage occurs. A defective pinch-off characteristic causes a reduction in the operating voltage of the FET. Further, the shift of the threshold voltage has an influence on the yield and the like because the allowable range for the design value is narrowed.

  In order to prevent this short channel effect, it is desirable that the ratio (aspect ratio) Lg / a between the active layer thickness a and the gate length Lg is 5 or more (for example, see Non-Patent Document 1).

  In the AlGaN / GaN-HEMT 110 described above, since the active layer thickness a is 25 nm, in the short gate region where the gate length Lg is 0.1 μm, the aspect ratio becomes about 4 and a short channel effect occurs.

Here, if the active layer thickness a is decreased, that is, the thickness of the electron supply layer 150 is decreased, the 2DEG concentration is decreased. On the other hand, when _x of Al _x Ga _1-x N is increased, that is, when the Al concentration is increased and finally AlN is used, it is compared with the case of Al _x Ga _1-x N (x = 0.25). It is theoretically possible to make the thickness of the electron supply layer 150 ¼ or less. However, when AlGaN is grown by the metal organic chemical vapor deposition (MOCVD) method, if the Al concentration of Al _x Ga _1-x N is increased, the surface of the AlGaN layer cracks when x = 0.52. This crack affects the FET characteristics (see Non-Patent Document 2, for example).

  In addition, it is known that the gate leakage characteristic is deteriorated by surface oxidation (see, for example, Non-Patent Document 3).

  Similarly, when an AlN layer is grown by metal organic vapor phase epitaxy, even an AlN layer having a thickness of about 2 nm is cracked on the surface.

Therefore, as an electron supply layer 0.99, AlN and, x is from can not be used _Al x _{Ga 1-x} N is 0.6 or more.

  This crack of the AlN layer is caused by a difference in thermal expansion coefficient between GaN and AlN during the temperature drop after growth because the AlN layer is grown at a high temperature (1200 ° C.) in the MOCVD method. It may be caused by oxidation due to exposure, but the cause is not clear.

  There is also a method in which the steps up to the formation of the AlN layer are performed by plasma molecular beam epitaxy (PAMBE: Plasma Assisted Molecular Beam Epitaxy) (see Non-Patent Document 4).

In Non-Patent Document 4, since the growth temperature of AlN in the PAMBE method is as low as 200 to 300 ° C., it is possible to grow AlN without causing cracks.
Masumi Fukuda, Yasuhiro Hirachi, “Basics of GaAs Field Effect Transistors” Corona, 1992, pp 56-59 M.M. Miyoshi et al. , “Characterization of Difficult-Al-Content AlGaN / GaN Heterostructures and High-Electron-Mobility Transistor Pistol Sapphire Sap. J. et al. Appl. Phys. , Vol. 43, no. 12, 2004, pp. 7939-7943 T.A. Hashizumi et al. , “Surface Control Process of AlGaN for Suppression of Gate Leakage Currents in AlGaN / GaN Heterostructure Field Effect Transistors”, Jpn. J. et al. Appl. Phys. , Vol. 45, no. 4, 2006, pp. L111-L113 M.M. Higashiwaki et al. "AlN / GaN Insulated-Gate HFETs Using Cat-CVD SiN", IEEE ELECTRON DEVICE LETTERS, Vol. 27, no. 9, 2006, pp. 719-721 Akihiko Iwasaki et al., “Study on crystal growth of AlGaN / GaN HEMT on SiC substrate”, IEICE Technical Report, IEICE TECHNICICAL REPORT, ED2006-155, CPM2006-92, LQE2006-59 (2006-10)

  Here, when the AlN layer is used as the electron supply layer, in order to increase the 2DEG concentration, the AlN layer is preferably formed to be thicker than 2 nm and at least about 4 to 5 nm.

  However, Non-Patent Document 3 reports the formation of an AlN layer having a thickness of about 2.5 mm, but does not report the formation of an AlN layer having a thickness exceeding that.

  Further, studies have been made to use an AlN layer as a spacer layer (see, for example, Non-Patent Document 5). This Non-Patent Document 5 discloses a technique for forming a GaN layer that is a channel layer, an AlN layer that is a spacer layer, and an AlGaN layer that is an electron supply layer on a base by a metal organic chemical vapor deposition method. .

  However, in Non-Patent Document 5, the AlN layer is used as a spacer layer, and a thickness of about 1 nm is optimal, and formation of a thickness larger than 2 nm has not been studied.

  Therefore, the inventors of the present application have conducted intensive research. As a result of forming the GaN layer as the cap layer following the formation of the AlN layer as the electron supply layer by MOCVD, the thickness of the AlN layer becomes 2. It has been found that even when the thickness is 5 nm or more, cracks are eliminated and the surface becomes flat.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is a heterojunction electric field using an AlN layer or an Al _x GaN layer having x of 0.6 or more as an electron supply layer. An effect transistor and a method for manufacturing the same are provided.

  In order to achieve the above-described object, the heterojunction field effect transistor according to the present invention includes a first GaN layer that is a channel layer, an AlN layer that is an electron supply layer, and a second GaN layer that is a cap layer. It is comprised with the laminated body made.

According to another preferred embodiment of the heterojunction field effect transistor of the present invention, a first GaN layer as a channel layer and an Al _x Ga _1-x N layer (0.6 ≦ x <) as an electron supply layer. 1) and a second GaN layer that is a cap layer are sequentially provided.

  In implementing the above-described heterojunction field effect transistor, it is preferable that a control electrode, a first main electrode, and a second main electrode be provided on the stacked body. In addition, a structure including a gate insulating film between the stacked body and the control electrode is preferable.

  In order to achieve the above-described object, a method for manufacturing a heterojunction field effect transistor according to the present invention includes the following steps. First, a first GaN layer that is a channel layer is formed on a base. Next, an AlN layer that is an electron supply layer is formed on the channel layer. Next, a second GaN layer that is a cap layer is formed on the electron supply layer. Here, the channel layer, the electron supply layer, and the cap layer are stacked in the same apparatus by metal organic vapor phase epitaxy.

Another preferred embodiment of the method for producing a heterojunction field effect transistor of the present invention comprises the following steps. First, a first GaN layer that is a channel layer is formed on a base. Next, an Al _x Ga _1-x N layer (0.6 ≦ x <1) that is an electron supply layer is formed on the channel layer. Next, a second GaN layer that is a cap layer is formed on the electron supply layer. Here, the channel layer, the electron supply layer, and the cap layer are stacked in the same apparatus by metal organic vapor phase epitaxy.

  In carrying out the above-described method of manufacturing a heterojunction field effect transistor, preferably, following the step of forming a cap layer, a silicon nitride film used as a gate insulating film in the same apparatus is formed by metal organic vapor phase epitaxy. It is good to form.

  Another preferred embodiment of the method for producing a heterojunction field effect transistor according to the present invention comprises the following steps. First, a GaN layer that is a channel layer is formed on a base. Next, an AlN layer that is an electron supply layer is formed on the channel layer. Next, a silicon nitride film used as a gate insulating film is formed on the electron supply layer. Here, the channel layer, the electron supply layer, and the silicon nitride film are stacked in the same apparatus by metal organic vapor phase epitaxy.

Another preferred embodiment of the method for producing a heterojunction field effect transistor according to the present invention comprises the following steps. First, a GaN layer that is a channel layer is formed on a base. Next, an Al _x Ga _1-x N layer (0.6 ≦ x <1) that is an electron supply layer is formed on the channel layer. Next, a silicon nitride film used as a gate insulating film is formed on the electron supply layer. Here, the channel layer, the electron supply layer, and the silicon nitride film are stacked in the same apparatus by metal organic vapor phase epitaxy.

According to the heterojunction field effect transistor of the present invention, since the AlN layer or the Al _x Ga _1-x N layer (0.6 ≦ x <1) is provided as the electron supply layer, the 2DEG concentration is the conventional one. It becomes higher than the case of an Al _x Ga _1-x N layer (for example, x = 0.25), and as a result, the thickness of the electron supply layer can be reduced. Therefore, even in the short gate region, the aspect ratio can be increased and the short channel effect can be suppressed.

In addition, according to the method for manufacturing a heterojunction field effect transistor of the present invention, an AlN layer or an Al _x Ga _1-x N layer (0.6 ≦ x <1) formed as an electron supply layer can be formed. Subsequently, a GaN layer as a cap layer or an SiN layer as a gate insulating film is formed in the same apparatus using metal organic vapor phase epitaxy. For this reason, since exposure of the AlN layer to the atmosphere does not occur, cracks in the AlN layer due to oxidation of the AlN layer can be suppressed. Similarly, cracks can also be suppressed in the Al _x Ga _1-x N layer (0.6 ≦ x <1) layer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(First embodiment)
The heterojunction field effect transistor of the first embodiment will be described with reference to FIG. Since this heterojunction field effect transistor is a high electron mobility transistor (HEMT), it may be referred to as HEMT in the following description.

  FIG. 1 is a schematic diagram for explaining the heterojunction field effect transistor according to the first embodiment, and shows a cut end face of a main part.

  In the heterojunction field effect transistor 10 of the first embodiment, a first GaN layer that is a channel layer 40, an AlN layer that is an electron supply layer 50, and a second GaN layer that is a cap layer 60 are sequentially formed on a base 20. It is comprised including the laminated body 30 laminated | stacked on. A two-dimensional electron gas (2DEG) is formed at the AlN / GaN-heterointerface 45, which is the interface between the first GaN layer that is the channel layer 40 and the AlN layer that is the electron supply layer 50.

  On the cap layer 60, a source electrode 82 and a drain electrode 84 formed by ohmic junction and a gate electrode 80 formed by Schottky junction are provided. The AlN / GaN-HEMT is separated from other elements by, for example, an element isolation region 35 formed by implanting impurities into the channel layer 40 and the electron supply layer 50. A silicon nitride film 90 is formed on the upper surface 62 of the cap layer 60 as a surface protective film.

  The heterojunction field effect transistor of the first embodiment can be formed by the following steps.

  First, the base 20 is prepared. The underlayer 20 can have the same configuration as that normally used in a heterojunction field effect transistor. For example, a substrate provided with a buffer layer on a substrate formed of one material selected from silicon, silicon carbide, and sapphire may be used. The buffer layer is provided in order to produce a lattice relaxation effect between the substrate such as silicon and the channel layer. The buffer layer is formed, for example, by growing AlN by metal organic chemical vapor deposition (MOCVD).

  Next, a first GaN layer that is the channel layer 40 is formed on the base 20. Next, an AlN layer that is the electron supply layer 50 is formed on the channel layer 40. Next, a second GaN layer that is the cap layer 60 is formed on the electron supply layer 50.

  Here, the channel layer 40, the electron supply layer 50, and the cap layer 60 are stacked in the same apparatus by MOCVD. The AlN layer is formed at a growth temperature of 1200 ° C. by introducing ammonia (NH 3) gas and trimethylaluminum (TMA) gas at a flow rate of 6 slm and 10 sccm, respectively, into the CVD apparatus. The first GaN layer and the second GaN layer are formed at a growth temperature of 1070 ° C. by introducing NH 3 gas and trimethyl gallium (TMG) gas at 5 slm and 6 sccm, respectively, into the CVD apparatus. Note that sccm (standard cubic cm per minute) and slm (standard liter per minute) are units representing gas flow rates when converted to 0 ° C. and 1 atm (= 1013 hPa).

  Here, since the AlN layer contains a large amount of Al, it is easily affected by surface oxidation and induces cracks. For this reason, it is difficult to suppress the gate leakage current when the AlN layer is exposed to the atmosphere. In the method of manufacturing the heterojunction field effect transistor according to the first embodiment, since the AlN layer that is the electron supply layer 50 is covered with the second GaN layer that is the cap layer 60, oxidation can be suppressed.

  FIG. 2 shows an AlN layer surface observed with an atomic force microscope (AFM) after an AlN layer having a thickness of 2 nm is formed by MOCVD. FIG. 3 shows the surface of the second GaN layer observed by AFM after forming the second GaN layer as the cap layer following the formation of the AlN layer as the electron supply layer. 2 and 3 both show a 1 μm square region.

  In FIG. 2, a crack structure is seen on the surface, whereas in FIG. 3, no cracks are seen on the surface, indicating that the surface structure is good. When a crack is generated in the AlN layer, the effect also appears on the surface of the second GaN layer formed on the AlN layer, but here, no crack is observed on the surface of the second GaN layer. That is, it can be seen that the formation of cracks in the AlN layer can be suppressed by forming the second GaN layer in the same apparatus following the formation of the AlN layer by MOCVD.

  When the growth is stopped at the stage when the AlN layer is formed, cracks are observed on the surface in the AFM image (see FIG. 2). Therefore, the formation of the GaN layer subsequent to the formation of the AlN layer indicates that the crack of the AlN layer is It is thought that it brought about the suppression. The reason for this is not clear, but the AlN layer is structured to be sandwiched between the first GaN layer and the second GaN layer, so that the AlN layer is prevented from being broken, or the surface of the AlN layer is covered, so that the AlN layer And the crack structure caused by the oxidation is suppressed.

  In any case, after the AlN layer is grown at 1200 ° C., the AlN layer cracks at the stage where the temperature is lowered to 1070 ° C. or the stage where the GaN layer is growing because of the growth of the GaN layer. In addition, after the growth of the GaN layer, even if the temperature is lowered to room temperature, the flatness of the surface is ensured.

  For example, if the thickness of the electron supply layer is 2.5 nm and the thickness of the cap layer is 5 nm, the active layer thickness a is 7.5 nm, and an aspect ratio of 5 or more can be ensured even when the gate length is shortened to 40 nm. .

  In order to increase the 2DEG concentration, it is preferable to increase the thickness of the AlN layer. Since AlN and GaN have lattice constants of 3.112 mm and 3.187 mm, respectively, and the difference is about 2.4%, the critical film thickness that can form an AlN layer without cracking is theoretically Is about 10 nm.

  4 (A), (B), (C), (D), (E), and (F), the thickness of the AlN layer is 0.5 nm, 2.5 nm, 2.55 nm, 6.08 nm, 8 AFM images for 12 nm and 20 nm are shown. Here, an AFM image of a 1 μm square region is shown on the surface of the GaN layer (second GaN layer) formed on the AlN layer, as in FIGS.

  FIG. 5 shows the relationship between the thickness of the AlN layer and the flatness of the surface. FIG. 5 shows the thickness of the AlN layer (unit: μm) on the horizontal axis, and the surface RMS (Root Mean Square) (unit: nm) on the vertical axis. The RMS of the surface is used for evaluating the flatness of the surface, and the distribution of the position in the height direction of the surface is calculated as the mean square of the distance from the average position.

  When the thickness of the AlN layer is up to 2.55 nm, there is no crack on the surface, and the RMS is 0.2 nm or less. When the thickness of the AlN layer is 6.08 nm, cracks are generated on the surface, and become prominent as the thickness of the AlN layer increases.

  In the region where the thickness of the AlN layer is 6.08 nm or more, the RMS increases linearly with respect to the thickness of the AlN layer. That is, an increase in RMS corresponds to an increase in cracks. On the other hand, the AlN layer has a substantially constant value up to 2.55 nm.

  When the thickness of the AlN layer is 6.08 nm or more, when the relationship between the thickness of the AlN layer and RMS is approximated by a linear line, y = 0.18x−0.89, and when x = 5, y is 0. become. That is, if the thickness of the AlN layer is 5 nm or less, it is considered that the influence of cracks on the operation of the FET can be ignored.

FIG. 6 shows the measurement results of the carrier concentration by CV measurement using a mercury probe. In FIG. 6, the horizontal axis indicates the depth (unit: nm) from the lower surface of the gate electrode, that is, the upper surface of the stacked body 30, and the vertical axis indicates the carrier concentration (unit: cm ⁻³ ). ing. FIG. 6 shows the measurement results when the thickness of the AlN layer is 2.5 nm and the thickness of the second GaN layer is 5 nm. At this time, the presence of a carrier having a depth of 9 nm and a concentration of 8.6 × 10 ¹⁹ cm ⁻³ was observed.

  When the carrier concentration was measured by the same method, no carrier was observed when the thickness of the AlN layer was 0.5 nm. Further, when the thickness of the AlN layer is 2.5 nm or more, the presence of carriers is recognized until the thickness of the AlN layer is 20 nm.

  From the above results, the thickness of the AlN layer is preferably 2.5 nm to 5 nm in consideration of the presence of carriers and the RMS of the surface.

Here, if the Al concentration of Al _x Ga _1-x N is increased and x = 1, it becomes AlN, and when x is 0.52 or more, Al _x Ga _1-x N has a cracked structure. Is known (see Non-Patent Document 2).

On the other hand, the GaN cap layer that is effective in suppressing cracks in the AlN layer is effective in suppressing cracks even for Al _x Ga _1-x N layers (0.6 ≦ x <1). Can be guessed easily. Therefore, an Al _x Ga _1-x N layer (0.6 ≦ x <1) can be used as the electron supply layer instead of the AlN layer.

The film thickness of the Al _x Ga _1-x N layer (0.6 ≦ x <1) is determined depending on the size of x. In order to increase the 2DEG concentration, the film thickness of the Al _x Ga _1-x N layer (0.6 ≦ x <1) is preferably made thicker than when an AlN layer is used as the electron supply layer. At this time, the difference in lattice constant between the Al _x Ga _1-x N layer and the GaN layer is smaller than the difference between the AlN layer and the GaN layer, so that the critical film thickness is increased and the thickness is equal to or greater than that of the AlN layer. Can be formed.

According to the heterojunction field effect transistor of the present invention, since the AlN layer or the Al _x Ga _1-x N layer (0.6 ≦ x <1) is provided as the electron supply layer, the 2DEG concentration is the conventional one. It becomes higher than the case of an Al _x Ga _1-x N layer (for example, x = 0.25), and as a result, the thickness of the electron supply layer can be reduced. Therefore, even in the short gate region, the aspect ratio can be increased and the short channel effect can be suppressed.

In addition, according to the method for manufacturing a heterojunction field effect transistor of the present invention, an AlN layer or an Al _x Ga _1-x N layer (0.6 ≦ x <1) formed as an electron supply layer can be formed. Subsequently, by forming a GaN layer as a cap layer using metal organic vapor phase epitaxy in the same apparatus, an AlN layer or an Al _x Ga _1-x N layer (0.6 ≦ x <1) is formed. Cracks can be suppressed.

(Second Embodiment)
With reference to FIG. 7, the heterojunction field effect transistor of 2nd Embodiment is demonstrated. FIG. 7 is a schematic view for explaining the heterojunction field effect transistor according to the second embodiment, and shows a cut end surface of a main part.

  The heterojunction field effect transistor 11 of the second embodiment includes a silicon nitride film as a gate insulating film 92 on a stacked body having a cap layer, and a gate electrode 80 on the gate insulating film 92. This is a field effect transistor (MISFET) having a so-called MIS (Metal Insulator Semiconductor) structure.

  With the MIS structure, gate leakage current can be suppressed. Even when a silicon nitride film having a thickness of 14 nm is laminated as the gate insulating film, if the thickness of the electron supply layer is 2.4 nm and the thickness of the cap layer is 3.3 nm, the active layer thickness a is 20 nm or less. Even when the length is 100 nm, an aspect ratio of 5 or more can be maintained.

In the conventional GaN-based MISFET, the AlGaN layer is used as the electron supply layer, and thus the aspect ratio is low. For example, in the case of an Al _x Ga _1-x N layer (x = 0.25) and the thickness of the electron supply layer is 25 nm, the thickness of the silicon nitride film is 14 nm. The distance to the interface is 39 nm, and the aspect ratio decreases to 2.5 when the gate length is 0.1 μm.

  On the other hand, if 2DEG formed at the AlN / GaN heterointerface is used, for example, the thickness of the AlN layer that is the electron supply layer 50 is 2.4 nm, and the thickness of the second GaN layer that is the cap layer 60 is 3.3 nm. Thus, even if the thickness of the silicon nitride film is 14 nm, an aspect ratio of 5 or more can be maintained.

FIG. 8 shows the measurement result of the carrier concentration by CV measurement using a mercury probe. In FIG. 8, the horizontal axis indicates the depth from the lower surface of the gate electrode, that is, the upper surface of the stacked body 30 (unit: nm), and the vertical axis indicates the carrier concentration (unit: cm ⁻³ ). ing. FIG. 8 shows measurement results when the thickness of the AlN layer is 2.4 nm, the thickness of the cap layer is 3.3 nm, and the thickness of the silicon nitride film is 14 nm. At this time, the presence of a carrier having a depth of 30 nm and a concentration of 1.75 × 10 ²⁰ cm ⁻³ was observed.

  The gate leakage current will be described with reference to FIG. FIG. 9A is a characteristic diagram showing the gate leakage current of the heterojunction field effect transistor according to the first embodiment described with reference to FIG. 1, and FIG. It is a characteristic view which shows the gate leak current of the heterojunction field effect transistor of 2nd Embodiment demonstrated. 9A and 9B, the horizontal axis indicates the source-gate voltage Vgs (unit: V), and the vertical axis indicates the leakage current Ids (unit: A) flowing between the source and gate. It shows.

In the first embodiment, the current Ids is about 1 × 10 ⁻⁸ to 1 × 10 ⁻⁷ A, whereas in the second embodiment, the leakage current is reduced by about 3 digits, and the current Ids is about 1 × 10 ⁻¹² to It is about 1 × 10 ⁻¹¹ A.

  The silicon nitride film can be formed by any suitable method such as a plasma CVD method or a thermal CVD method. However, following the formation of the stacked layer of the channel layer, the electron supply layer, and the cap layer, the MOCVD method is performed in the same apparatus. It is good to deposit by. In this case, the silicon nitride film is formed at a growth temperature of 850 ° C. by introducing NH 3 gas and silane (SiH 4) gas at 4 slm and 100 sccm, respectively, into the CVD apparatus.

  Here, following the formation of the stacked body of the channel layer, the electron supply layer, and the cap layer, the gate insulating film is formed in the same apparatus. For this reason, the SiN / GaN interface state is improved. As a result, the interface state is small in the operation of the MISFET, the current collapse due to the interface state is improved, and the gate breakdown voltage can be expected to be improved.

In the heterostructure field effect transistor according to the second embodiment, an Al _x Ga _1-x N layer (0.6 ≦ x <1) is used instead of the AlN layer as the electron supply layer, as in the first embodiment. Can be used.

(Third embodiment)
A heterojunction field effect transistor according to the third embodiment will be described with reference to FIG. FIG. 10 is a schematic view for explaining the heterojunction field effect transistor according to the third embodiment, and shows a cut end surface of a main part.

  The heterojunction field effect transistor 12 of the third embodiment includes a stacked body 32 in which a GaN layer that is a channel layer 40 and an AlN layer that is an electron supply layer 50 are sequentially stacked. A two-dimensional electron gas (2DEG) is formed at the AlN / GaN-hetero interface between the channel layer GaN layer and the electron supply layer AlN layer.

  A silicon nitride film that is a gate insulating film 92 is formed on the electron supply layer. The GaN layer and the AlN layer are formed by MOCVD as in the second embodiment, and a silicon nitride film is formed in the MOCVD apparatus following the formation of the AlN layer as the electron supply layer.

  As a result, since the SiN layer is formed without exposing the surface of the AlN layer to the atmosphere, surface oxidation of the AlN layer and cracks due to this surface oxidation can be prevented.

In the heterostructure field effect transistor of the third embodiment, as in the first and second embodiments, an Al _x Ga _1-x N layer (0.6 ≦ x) is used instead of the AlN layer as the electron supply layer. <1) can be used.

It is the schematic for demonstrating the heterojunction field effect transistor of 1st Embodiment. It is a figure which shows the AlN layer surface observed with the atomic force microscope. It is a figure which shows the 2nd GaN layer surface observed with the atomic force microscope. It is a figure which shows the 2nd GaN layer surface observed with the atomic force microscope at the time of changing the thickness of an AlN layer. It is a characteristic view which shows the relationship between the thickness of an AlN layer, and surface RMS. It is a figure which shows the measurement result of the carrier concentration by CV measurement in 1st Embodiment. It is the schematic for demonstrating the heterojunction field effect transistor of 2nd Embodiment. It is a figure which shows the measurement result of the carrier concentration by CV measurement in 2nd Embodiment. It is a characteristic view which shows the gate leakage current of a heterojunction field effect transistor. It is the schematic for demonstrating the heterojunction field effect transistor of 3rd Embodiment. It is the schematic for demonstrating the conventional heterojunction field effect transistor.

Explanation of symbols

10, 11, 12 Heterojunction field effect transistor
20 Underlayer 30, 32 Laminate
35 Device isolation region
40 channel layer 45 AlN / GaN-hetero interface 50 electron supply layer 60 cap layer 80 gate electrode 82 source electrode 84 drain electrode 90, 94 surface protection film 92 gate insulating film

Claims (9)

A first GaN layer that is a channel layer;
An AlN layer which is an electron supply layer;
A heterojunction field effect transistor comprising a laminate in which a second GaN layer as a cap layer is sequentially laminated. A first GaN layer that is a channel layer;
Al _x Ga _1-x N layer (0.6 ≦ x <1) which is an electron supply layer;
A heterojunction field effect transistor comprising a laminate in which a second GaN layer as a cap layer is sequentially laminated. The heterojunction field effect transistor according to claim 1, further comprising a control electrode, a first main electrode, and a second main electrode on the stacked body. The heterojunction field effect transistor according to claim 3, further comprising a gate insulating film between the stacked body and the control electrode. Forming a first GaN layer as a channel layer on the ground;
Forming an AlN layer as an electron supply layer on the channel layer;
Forming a second GaN layer as a cap layer on the electron supply layer,
The method for manufacturing a heterojunction field effect transistor, wherein the channel layer, the electron supply layer, and the cap layer are stacked in the same apparatus by metal organic chemical vapor deposition. Forming a first GaN layer as a channel layer on the ground;
Forming an Al _x Ga _1-x N layer (0.6 ≦ x <1) as an electron supply layer on the channel layer;
Forming a second GaN layer as a cap layer on the electron supply layer,
The method for manufacturing a heterojunction field effect transistor, wherein the channel layer, the electron supply layer, and the cap layer are stacked in the same apparatus by metal organic chemical vapor deposition. 7. The heterojunction according to claim 5, wherein a silicon nitride film used as a gate insulating film in the same apparatus is formed by metal organic vapor phase epitaxy after the step of forming the cap layer. Type field effect transistor manufacturing method. Forming a GaN layer as a channel layer on the ground;
Forming an AlN layer as an electron supply layer on the channel layer;
Forming a silicon nitride film used as a gate insulating film on the electron supply layer,
The method of manufacturing a heterojunction field effect transistor, wherein the channel layer, the electron supply layer, and the silicon nitride film are stacked in the same apparatus by metal organic vapor phase epitaxy. Forming a GaN layer as a channel layer on the ground;
Forming an Al _x Ga _1-x N layer (0.6 ≦ x <1) as an electron supply layer on the channel layer;
Forming a silicon nitride film used as a gate insulating film on the electron supply layer,
The method of manufacturing a heterojunction field effect transistor, wherein the channel layer, the electron supply layer, and the silicon nitride film are stacked in the same apparatus by metal organic vapor phase epitaxy.