JPS61274369A - Field effect type semiconductor device - Google Patents
Field effect type semiconductor deviceInfo
- Publication number
- JPS61274369A JPS61274369A JP10989585A JP10989585A JPS61274369A JP S61274369 A JPS61274369 A JP S61274369A JP 10989585 A JP10989585 A JP 10989585A JP 10989585 A JP10989585 A JP 10989585A JP S61274369 A JPS61274369 A JP S61274369A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- hemt
- conductivity type
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 title claims 2
- 230000000295 complement effect Effects 0.000 abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000004047 hole gas Substances 0.000 abstract description 2
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 2
- 239000000956 alloy Substances 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 abstract 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000012010 growth Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ヘテロ接合を用いてｐ及びルテヤネルを有するＨＥＭＴ
構造の相補型デバイスを作製する際、該ｐ。[Detailed description of the invention] [Summary] HEMT having p and luteyanel using a heterojunction
When producing a complementary device of the structure, the p.
ｎ ＨＥＭＴ構造用のエピタキシャル層を重ねて形成し
た構造？用い、下方のＨＥＭＴ構造は上方のＨＥＭＴ構
造を部分的に除去して用いるようにし、再成長工程を不
要とする。n Structure formed by stacking epitaxial layers for HEMT structure? The lower HEMT structure is used by partially removing the upper HEMT structure, thereby eliminating the need for a regrowth process.
本発明は相補型のＨＥＭＴ （高電子、正孔移動度トラ
ンジスタ）に係り、特にそのエピタキシャル層構造の改
良に関する。The present invention relates to complementary HEMTs (high electron, hole mobility transistors), and in particular to improvements in their epitaxial layer structure.
コンプリメンタ９・デバイス（相補型）は、低消費電力
、高集積度化が実現可能なことから、シリコンでは技術
的進歩が著しい分野である。Complementary 9 devices (complementary type) are a field in which significant technological progress is being made in silicon because low power consumption and high integration can be achieved.
ＧａＡｓ系でも相、捕型が試みられているが、Ｐｆヤネ
ルの正孔移動度が小さいためシー、特性的Ｃ；あまり興
味のある系ではなかったが、最近へテロ接合への選択ド
ーピングＣ二より、ＧＩＺＡＪＰよりはるかに高い正孔
移動度をもつ構造が研究されている。Although phase and trapping have been attempted in the GaAs system, due to the low hole mobility of Pf layer, the characteristic C; Therefore, structures with much higher hole mobility than GIZAJP are being studied.
第３図（二従来例の相補型ＨＥＭＴを示してあり、５１
は１板であり、その上（ニル型ＨＥＭＴ構造■をエビタ
キＶヤル成長し、次にｐ型ＨＥＭＴ （Ｈｉ ！Ａ ｈ
ａ ｌ ＃Ｆ７Ｌｏｂｉｌｉｔｙ ｔｒａｎｓｉｓｔｏ
ｒと称されＨＨＭＴとなるが通常Ｐ型ＨＥＭＴと呼ばれ
る）構造［株］を［相］の層を選択的（：除去した部分
Ｃ；成長している。■の６２はバッファ層、５３はアン
ドープＧαＡｓ、５４はルーＡＩＧａＡｚ 。Figure 3 (shows two conventional complementary HEMTs, 51
is one plate, on top of which (nil-type HEMT structure) is grown, then p-type HEMT (Hi!A h
a l #F7Labilitytransisto
The layer of [phase] is selectively grown (removed part C; 62 of ■ is a buffer layer, 53 is an undoped layer). GaAs, 54 is Lu AIGaAz.
３５は３− （ｒＸＡｔＸＡｔキャラあり、電極Ｓ、Ｄ
及びゲート電極Ｇが設けられている。■の４２はバッフ
ァ層、４３はノンドープＧａＡｚ 、 ４４はｐ −Ａ
ＩＧａＡｚ 。35 is 3- (rXAtXAt character included, electrodes S, D
and a gate electrode G are provided. 42 is a buffer layer, 43 is non-doped GaAz, and 44 is p-A.
IGaAz.
４５はｐ −ＧａＡｚキャップ層であり、電極Ｓ、Ｄ及
びゲート電極Ｇが形成されている。45 is a p-GaAz cap layer, on which electrodes S, D and gate electrode G are formed.
ところが、上記のように選択エツチング等で除去した凹
部Ｃｐ ｍＨＥＭＴ ＠造を成長する方法では、欠点と
して成長層界面の問題から成る程度以上の膜厚が必要（
〜６０００Ａ ）であり、再成長ｌ二時間がかかる。更
（こ、凹部の深さ方向界面近辺の成長面の高抵抗化のた
めに、素子部分には不用な領域（第３図のＸ印）が生じ
、素子面積縮小の妨げとなる。However, the method of growing the concave Cp mHEMT structure removed by selective etching, etc., as described above, has the disadvantage of requiring a film thickness greater than that due to the problem of the interface between the grown layers (
~6000A), and regrowth takes 12 hours. Furthermore, due to the high resistance of the growth surface near the interface in the depth direction of the recess, an unnecessary region (marked by X in FIG. 3) is generated in the element portion, which becomes an obstacle to reducing the area of the element.
なお、この成長面の高抵抗化は、凹部側面の成長により
複雑な界面が形成される為と考えられており、これｔ避
けることはできない。Note that this increase in the resistance of the growth surface is thought to be due to the formation of a complex interface due to the growth of the side surface of the recess, and this cannot be avoided.
また、このよう）二、再成長工程な用いること自体、製
造上の効率を悪化させる。In addition, the use of such a regrowth process itself deteriorates manufacturing efficiency.
本発明（二おいては、相補型のＨＥＭＴ構造を作製する
のに、Ｐｆ−ヤネルを生じるエピタキシャル月及びルチ
ャネルを生じるエピタキシャル層を重ねた構造を形成し
、下方のエピタキシャル層を部分的（二露出して、ｐも
しくはｒｂ ＨＥＭＴ ｌ；用い、上方のエピタキシャ
ル層′ｆｊＩニルもしくはｐ ＨＥＭＴ ｌ：用いる。In the present invention (2), to fabricate a complementary HEMT structure, a structure is formed in which an epitaxial layer producing a Pf channel and an epitaxial layer producing a channel are stacked, and the lower epitaxial layer is partially Exposed, p or rb HEMT l: used, upper epitaxial layer 'fjI' or p HEMT l: used.
上記相補型ＨＥＭＴ構造は一度（一連）のエビタ午ンヤ
ル成長（二より形成できる。The above complementary HEMT structure can be formed by one (series) of two consecutive growths.
第２図に本発明の実施例のＨＥＭＴ用エピタキシャル構
造が表わしてあり、Ｇ ａ Ａ ｓ基板１上に以下の層
がＭＯＣＶＤ （有機金属気相成長１法等により、典型
的な例として形成される。FIG. 2 shows an epitaxial structure for HEMT according to an embodiment of the present invention, in which the following layers are typically formed on a GaAs substrate 1 by MOCVD (metal-organic chemical vapor deposition 1 method, etc.). Ru.
キャリア濃度 膜厚
２：アンドープＧｃＬＡＪ層 ６Ｑ
ＱＯＡ４ニル型傾斜組成の
ＡＩＧａＡｚ層Ｃ８番ドープ） ｊ、５ＸｊＯ”ｃｍ
−３５０ＯＡ：キャリア濃度 膜厚
５ ： ｎ −ＧａＡｊＣ８ｉドープ）
２ｘ１０ ｃｍ ５００Ａ６：ア、
ドープＡｔ 、 Ｇａ１−２ＡＩ層
５０，４７：アンドープ員ＡＪＦ層
１０００Ａ９：ｐ”−ＧａＡｓＪｔｌｌ
４Ｘ１０”ｃｍ−’ ５００Ａ上記１：おいて
、３のルーＡｔ、Ｇａ１−ｙ Ａ ｓ層の７＝０．５．
４のル型傾斜組成のＡｌＧａＡｓはＡｌｏ、！ｔ Ｇａ
ｏ、７ＡＩからＱ ａＡ Ｊに傾斜型に変化させた層、
６のアンドープＡｔｚＧα１ ＋Ｚ Ａ ＪＰ層はｚ
” Ｏａ ５．８のｐ ＡｌｚＧａ１ｚＡｚ層のＸ ＝
Ｏ，Ｓとなした。Carrier concentration Film thickness 2: Undoped GcLAJ layer 6Q
AIGaAz layer C8 doped with QOA4nyl type gradient composition) j, 5XjO”cm
-350OA: Carrier concentration Film thickness 5: n-GaAjC8i doped)
2x10 cm 500A6:A,
Doped At, Ga1-2AI layer
50, 47: Undoped AJF layer
1000A9:p”-GaAsJtll
4X10"cm-' 500A above 1:, 3 Lu At, Ga1-y As layer 7=0.5.
4, AlGaAs with a le-graded composition is Alo,! tGa
o, a layer with a gradient type change from 7AI to Q aA J,
The undoped AtzGα1 +Z A JP layer of 6 is z
” X of p AlzGa1zAz layer with Oa 5.8 =
O, S.
なお、適用可能なｘ、ｙ、ｚの値の範囲は、０．１ ＜
２ ＜ ０．７
０．１ ＜ ｙ＜ ０．５
０．１ ＜ ｚ≦１
である。Note that the applicable range of x, y, and z values is 0.1 <
2 < 0.7 0.1 < y < 0.5 0.1 < z≦1.
前記の１〜５の層は通常のｒＬ−ＨＥＭＴ構造と同じで
あり、その上１；アンドープＡｔｚＧａ１−ＺＡＪＦ層
６を介してｐ −ＨＥＭＴ構造が形成されており、これ
らは一連の成長で作製される。Ｐ ｙ ’同構造の間の
ＡｔｚＧα１−ヱＡ＃層は同構造間の電気的分離と、ｐ
−ＨＥＭＴ構造を均一（；エツチングするだめのエツ
チング停止層を兼ねた役割をする。The above-mentioned layers 1 to 5 are the same as the normal rL-HEMT structure, and a p-HEMT structure is formed via an undoped AtzGa1-ZAJF layer 6, which is fabricated by a series of growths. Ru. P y 'The AtzGα1-ヱA# layer between the same structures provides electrical isolation between the same structures and p
- Uniform HEMT structure (also serves as an etching stop layer before etching).
このようなエピタキシャル層構造をとれば、エピタキシ
ャル成長時間は従来の約ン「：短縮され、再成長界面の
問題もないので良好なデバイス作鰻につながる。If such an epitaxial layer structure is adopted, the epitaxial growth time will be shortened compared to the conventional method, and there will be no problem with regrowth interfaces, leading to good device production.
第１図に、第２図のＨＥＭＴ用エピタキシャル構造を用
いて形成した実施例の素子構造（４）及びその等価回路
（ロ）を表わしている。FIG. 1 shows an element structure (4) of an example formed using the HEMT epitaxial structure shown in FIG. 2 and its equivalent circuit (b).
第１図（イ）を参照して、製造工程を説明する。The manufacturing process will be explained with reference to FIG. 1(a).
ｐ −ＨＥＭＴはＨＥＭＴ用エピタキシャル構造をその
まま使用する。For p-HEMT, the epitaxial structure for HEMT is used as is.
３−ＨＥＭＴは、Ａ ｌ ｚ Ｇ Ｇ １−２ Ａ １
層６をエツチング停止層として用い、ドライエツチング
で凹部を形成し、その後ＡｌｚＧ”１−２”層６をウェ
ットエツチングで除去して％−ＨＥＭＴ構造を露出して
用いる。3-HEMT is Al z G G 1-2 A 1
Using layer 6 as an etch stop layer, a recess is formed by dry etching, and then AlzG "1-2" layer 6 is removed by wet etching to expose the %-HEMT structure for use.
該ドライエツチングは、ＣＣｌ ２ Ｊ’２ ＋ Ｈ＃
（ガス圧１：１）の混合ガスを用いて行なう。その選
択比はＡｌＧａＡｓ／ＧａＡｚ ＝ １／ ２５０であ
り、ＡｌｚＧａｌ−ｚＡ’層６をストッパとして均一（
二ｐ −ＨＥＭＴ構造を除去することができる。The dry etching is CCl 2 J'2 + H#
(gas pressure 1:1) using a mixed gas. The selection ratio is AlGaAs/GaAz = 1/250, and the AlzGal-zA' layer 6 is used as a stopper to uniformly (
The 2p-HEMT structure can be removed.
２次元電子ガス（３チヤネル）層Ｃ１及び２次元正孔ガ
ス＜ｐｆヤネル）層Ｃ２は、２，３及び８゜７の半導体
界面の電子親和力がより大なｉ（非ドープ）ＧａＡｓ層
２，７に形成される。オーミック電極２１ 、２２及び
１１，１２はそれぞれリフト・オフで形成後合金処理で
作製し、ゲート電極１３．２５は例えばＡｔを用いて、
Ｐ、ル側を同時に１回の蒸着で形成できる。The two-dimensional electron gas (three-channel) layer C1 and the two-dimensional hole gas <pf channel) layer C2 are an i (undoped) GaAs layer 2, which has a larger electron affinity at the semiconductor interface of 2, 3, and 8°7. 7 is formed. The ohmic electrodes 21, 22 and 11, 12 are formed by lift-off and then alloyed, and the gate electrodes 13, 25 are made of, for example, At.
The P and L sides can be formed simultaneously in one vapor deposition.
なお、その際ゲート形成部のｐ −ＧａＡｓ９及びｎ”
−ＧａＡｚ ５ ｆリセスして取除き、ｐ−ＡｌｚＧ
ａ１４Ａｚ層８及びルーＡｔ、Ｇａ１ ＋＋ｙ Ａ Ｊ
Ｆ層６にゲート電極を形成している。In addition, in this case, the p-GaAs9 and n"
-GaAz 5f recessed and removed, p-AlzG
a14Az layer 8 and Lu At, Ga1 ++y A J
A gate electrode is formed in the F layer 6.
なお、第１図（Ａ）ｌ二おいて＠〜■と指示するのは素
子間の電気的分離領域であり、Ｔ ｉ ／Ａμの５００
０ Ａ程度の膜（図示せず）７にマスクにして酸素イオ
ンを注入して形成した高抵抗領域である（本実施例は図
（５）のようにインバータを構成しているので＠〜■の
分離は不用であるが、一般的な例として示しである）。Note that in FIG. 1(A) 12, the areas indicated by @~■ are electrical isolation regions between elements, and are 500% of T i /Aμ.
This is a high resistance region formed by implanting oxygen ions into a film (not shown) 7 of about 0 A as a mask. separation is not necessary, but is shown as a general example).
以上のよう１；構成された相補型ＨＥＭＴのｐ −ＨＥ
ＭＴは低温下（二おいて４０００ ａｍ”／Ｖ−８程度
の移動度を示し、十分高速動作が可能である。As above 1; p-HE of the constructed complementary HEMT
MT exhibits a mobility of approximately 4000 am''/V-8 at low temperatures (2000 am''/V-8) and is capable of sufficiently high-speed operation.
なお、これまでルーＨＥＭＴ用エピタキシャル構造を下
方に、ｐ−ＨＥＭＴ用エピタキシャル構造全上方に形成
した例で説明し之が、これを逆にしても良いことはもち
ろんである。また、本発明は他の半導体系１例えばＩｎ
Ｐ系にも適用できる。Although an example has been described so far in which the R-HEMT epitaxial structure is formed below and the p-HEMT epitaxial structure is formed entirely above, it goes without saying that this may be reversed. The present invention also applies to other semiconductor systems such as In
It can also be applied to P series.
以上のことから明らかなように、本発明によれば従来の
よう（二再成長が必要でないので、Ｐ、ルＨＥＭＴ形成
用のエピタキシャル構造の作製が容易であり、再成長界
面の問題もないので良好な相補ｆｉ ＨＥＭＴを高密度
に形成することが可能になる０As is clear from the above, according to the present invention, it is easy to fabricate an epitaxial structure for forming a P, Le HEMT because two regrowths are not required, and there is no problem with the regrowth interface. 0, which makes it possible to form high-density complementary fi HEMTs.
第１因（イ）向はそれぞれ本発明の実施例の断面図及び
等価回路図、
第２図は実施例のエピタキシャル構造な示す図、第３図
は従来例の断面図である。
１・・・ＧａＡｚ基板
２・・・アンドープＧ ａ Ａ ７層
５・・・ルーＡｔ、Ｇａ１ ＋ｙＡ ｚ層４ ・−ｎ
−ｇｒａｄｅｄ ＡＩＧａＡｚ層５…ルーＧａＡｓ層
６・・・アンドープＡｔｚＧα１−２ＡＪＰ層７・・・
アンドープＡｔｚＧα１−１Ａｊ層８、−ｐ−Ａｌ□Ｇ
α１−２ Ａ １層９ …ｐ −ＧａＡｓ層The first factor (A) direction is a cross-sectional view and an equivalent circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the epitaxial structure of the embodiment, and FIG. 3 is a cross-sectional diagram of a conventional example. 1... GaAz substrate 2... Undoped GaA 7 layer 5... Lu At, Ga1 +yA z layer 4 ・-n
-graded AIGaAz layer 5...Ru GaAs layer 6...Undoped AtzGα1-2AJP layer 7...
Undoped AtzGα1-1Aj layer 8, -p-Al□G
α1-2 A 1 layer 9...p -GaAs layer
Claims (1)
合し、第１半導体層より電子親和力が小なる一導電型の
第２半導体層を有し、第１半導体層の第２半導体層との
界面に一導電型のチャネルが形成される一導電型素子用
エピタキシャル構造を備え、 該一導電型素子用エピタキシャル構造上に反対導電型チ
ャネル用の第３半導体層及びこれに格子整合し、第３半
導体層より電子親和力が小なる第４半導体層を有し、第
３半導体層の第４半導体層との界面に反対導電型のチャ
ネルが形成される反対導電型素子用エピタキシャル構造
を備え、該反対導電型素子用エピタキシャル構造に一導
電型素子用エピタキシャル構造の表面に到る凹部が備え
られ、該凹部内の一導電型素子用エピタキシヤル構造の
表面に一導電型素子用のソース、ドレイン及びゲート電
極が備えられ、 該反対導電型素子用エピタキシャル構造の表面に、反対
導電型素子用のソース、ドレイン及びゲート電極が備え
られてなることを特徴とする電界効果型半導体装置。[Scope of Claims] A first semiconductor layer for a channel of one conductivity type, and a second semiconductor layer of one conductivity type that is lattice matched thereto and has a smaller electron affinity than the first semiconductor layer; an epitaxial structure for an element of one conductivity type in which a channel of one conductivity type is formed at an interface with a second semiconductor layer, and a third semiconductor layer for a channel of an opposite conductivity type on the epitaxial structure for an element of one conductivity type; For an element of opposite conductivity type, which has a fourth semiconductor layer that is lattice-matched and has a lower electron affinity than the third semiconductor layer, and a channel of the opposite conductivity type is formed at the interface between the third semiconductor layer and the fourth semiconductor layer. an epitaxial structure, the epitaxial structure for an element of opposite conductivity type is provided with a recess that reaches the surface of the epitaxial structure for an element of one conductivity type, and the surface of the epitaxial structure for an element of one conductivity type within the recess is provided with an element of one conductivity type. A field effect semiconductor, comprising: a source, a drain, and a gate electrode for an opposite conductivity type element, and a surface of the opposite conductivity type element epitaxial structure is provided with a source, drain, and gate electrode for an opposite conductivity type element. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10989585A JPS61274369A (en) | 1985-05-22 | 1985-05-22 | Field effect type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10989585A JPS61274369A (en) | 1985-05-22 | 1985-05-22 | Field effect type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61274369A true JPS61274369A (en) | 1986-12-04 |
Family
ID=14521879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10989585A Pending JPS61274369A (en) | 1985-05-22 | 1985-05-22 | Field effect type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61274369A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4963948A (en) * | 1986-12-20 | 1990-10-16 | Fujitsu Limited | Semiconductor device having level shift diode |
| US4974038A (en) * | 1987-08-05 | 1990-11-27 | Thomson Hybrides Et Microondes | Microwave transistor with double heterojunction |
| JPH033336A (en) * | 1989-05-31 | 1991-01-09 | Hitachi Ltd | Semiconductor device |
| US5302840A (en) * | 1991-06-20 | 1994-04-12 | Fujitsu Limited | HEMT type semiconductor device having two semiconductor well layers |
| GB2504614A (en) * | 2012-07-17 | 2014-02-05 | Element Six Technologies Us Corp | Complimentary Heterojunction Field Effect Transistor |
-
1985
- 1985-05-22 JP JP10989585A patent/JPS61274369A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4963948A (en) * | 1986-12-20 | 1990-10-16 | Fujitsu Limited | Semiconductor device having level shift diode |
| US4974038A (en) * | 1987-08-05 | 1990-11-27 | Thomson Hybrides Et Microondes | Microwave transistor with double heterojunction |
| JPH033336A (en) * | 1989-05-31 | 1991-01-09 | Hitachi Ltd | Semiconductor device |
| US5302840A (en) * | 1991-06-20 | 1994-04-12 | Fujitsu Limited | HEMT type semiconductor device having two semiconductor well layers |
| GB2504614A (en) * | 2012-07-17 | 2014-02-05 | Element Six Technologies Us Corp | Complimentary Heterojunction Field Effect Transistor |
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