JPS63211770A - Filed-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a high performance 2 DEGFET, in which resistance values between a source electrode and a gate electrode and between a drain electrode and the gate electrode are sufficiently decreased, by specifying the thickness of a resistance decreasing semiconductor layer, and making only a region, where the source electrode and the drain electrode are formed, thin. CONSTITUTION:The thickness of a resistance decreasing third semiconductor layer 5a is made to be 1,000-1,500Angstrom . Only a region, where a source electrode and a drain electrode are formed, is thinly formed. When the thickness (d) of the n-type GaAs layer 5a is thin, the resistance value R1 of the n-type GaAs layer 5a becomes large. When the thickness (d) of the n-type GaAs layer 5a becomes too thick, the lateral width of a recess groove 9 increases with said increased thickness, and a resistance value R3 becomes large. In consideration of these conditions, the resistance value RS(d)/RS(d=500Angstrom ), i.e., the resistance value RS, becomes the minimum value when the thickness (d) of the GaAs layer 5a is d=1,000-1,500Angstrom .

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field effect transistor (hereinafter referred to as 2DEGFET) that utilizes a two-dimensional electron gas (2DEG) formed at the interface of, for example, GaAs and AuGaAs.

[Conventional technology]

Figures 4(a) to (d) show the conventional 2DE
FIG. 2 is a diagram showing an example of a structure of a GFET.

In these figures, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs layer as the first semiconductor layer, and 3 is a Z
The DEG layer 4 is an n-type Aj! as a second semiconductor layer. Ga
an As layer, 5 an n-type GaAs layer as a third semiconductor layer,
6 is a gate electrode, 7 is a source electrode, 8 is a drain electrode,
9 is a recess groove.

There are two types of 2DEGFETs: a planar structure and a recessed structure. FIGS. 4(a) and 4(b) show the planar structure, and FIGS. 4(c) and 4(d) show the recessed structure.

In the case shown in FIG. 4(a), an undoped GaAs layer 2 is formed on a semi-insulating GaAs substrate 1. An n-type AIGaAS layer 4 is epitaxially grown to form a source electrode 7 and a drain electrode 8 that are in ohmic contact with these, and a gate electrode 6 that is in Schottky contact with the n-type AJ2GaAs layer 4.

The one shown in FIG. 4(b) is an improved structure of the n-type Aj! G
An n-type GaAs layer 5 is provided between the aAs layer 4 and the gate electrode 6.

4(C) and (d), the gate electrode 6 is formed in the recess groove 9, but in the case of FIG. 4(C), the bottom of the recess groove 9 is made of n-type AλGaAs. Located in layer 4,
In the case of FIG. 4(d), the bottom of the recess groove 9 is in the n-type GaAs layer 5.

The structure of 2DEGFET can be roughly divided into 2 types as shown below.
Although there are different types, the planar structure 2DEGFET shown in Figures 4(a) and 4(b) can be expected to improve the uniformity of the transistor characteristics within the plane. control is necessary. Also, in general, in such a planar structure, the resistance values between the source electrode 7 and the gate electrode 6, and between the gate electrode 6 and the drain electrode 8 are lower than in the recessed structure 2DEGFET shown in FIGS. 4(e) and 4(d). Therefore, in order to reduce this resistance value, the distance between the source electrode 7 and the drain electrode 8 is changed to a 2DEGFE with a recessed structure as shown in FIGS. 4(C) and 4(d).
There is a manufacturing difficulty in that it must be narrower than T.

For this reason, relatively many 2DEGFETs having the recess structure shown in FIGS. 4(c) and 4(d) are currently manufactured.

The second most common recess structure shown in Figure 4 (C)
The operation of DEGFET will be explained.

When a voltage is applied between the source electrode 7 and the drain electrode 8,
A current flows through the 2DEG layer 3, and when a voltage is applied to the gate electrode 6 at this time, the concentration of the 2DEG layer 3 under the gate changes, causing a transistor operation.

Therefore, by adjusting the depth of the recess groove 9 forming the gate electrode 6, the initial current value of the transistor can be adjusted, and a 2DEGFET with desired characteristics can be manufactured.

In addition, the n-type GaAS layer 5 in the 2DEGFET having such a recessed structure promotes the reaction with the electrode metal when forming the source electrode 7 and drain electrode 8, so that the source electrode 7 and drain electrode 8 and the 2DEG layer It is used for the purpose of lowering the contact resistance value with 3, and a film thickness of 400 to 600 is usually adopted. This is because if the film thickness is made too thick,
There is a concern that the electrode metals of the source electrode 7 and the drain electrode 8 will not sink sufficiently, and the contact resistance value with the ZDEG layer 3 will increase.

(Problems to be Solved by the Invention) In the conventional 2DEGFET as described above, a recess structure is adopted to reduce the resistance value between the source electrode 7 and the gate electrode 6, and between the drain electrode 8 and the gate electrode 6. However, when the n-type GaAs layer 5 has a thickness of about 400 to 600 layers, there is a problem that the resistance values between the source electrode 7 and the gate electrode 6 and between the drain electrode 8 and the gate electrode 6 are not sufficiently reduced. .

The present invention was made to solve these problems, and is a high-performance 2DE with sufficiently reduced resistance values between the source electrode and the gate electrode, and between the drain electrode and the gate electrode.
The purpose is to obtain a GFET.

[Means for solving problems]

In the 2DEGFET according to the present invention, the third semiconductor layer for reducing resistance has a thickness of 1,000 to 1,500 layers, and only the regions where the source electrode and drain electrode are formed are formed thinly.

(Function) In this invention, the contact resistance value between the source electrode and the drain electrode and the 2DEG layer is reduced by the third semiconductor layer.

〔Example〕

FIG. 1 is a diagram showing the structure of an embodiment of a 2DEGFET of the present invention.

In this figure, 5a is the n-type GaAs in this invention.
It is made up of 1,000 to 1,500 thick layers. Further, the depth and lateral extent of the recess groove 9 are both Il (μm), the distance between the source electrode 7 and the gate electrode 6 is 1 μm, and the width of the gate electrode 6 is W (μm).

In addition, FIGS. 2(a) and 2(b) show the source voltage 8i! 2 is a diagram isometrically showing the dependence of the resistance value between the gate electrode 7 and the gate electrode 6 on the thickness of the n-type GaAs layer 5a and the 2DEGFET shown in FIG. 1. FIG.

In FIG. 2(a), the thickness of the n-type GaAs layer 5a is d, and the resistance value between the source electrode i7 and the gate electrode 6 is Rs (d).
, the horizontal axis is d, and the vertical axis is R3 (ct)/Rs (
d = 500 people).

In addition, in FIG. 2(b), Rc is the contact resistance value between the electrode metal and the epitaxial layer including the contact resistance value to the 2DEG layer 3, R1 is the resistance value of the n-type GaAs layer 5a, R2,
Rs is the resistance value of the 2DEG layer 3, and each resistance value is RCccl/
W, R, oe (1-j2)/11-W, R2” (
1-℃)/W, R3cei/w.

Next, using Figure 2(b), calculate the film thickness d and the resistance value R5(d).
/Rs (d = 500 people).

When the film thickness d of the n-type GaAs layer 5a is small, the n-type GaAs
Even if the resistance value R1 of the s-layer 5a is large and the film thickness d of the n-type GaAs layer 5a becomes too thick, the lateral extent 2 of the recess groove 9 increases with the film thickness, and the resistance value R3 becomes large. Considering these conditions, a curve as shown in Fig. 2(a) is obtained, and the resistance value R at d = 1000 to 1500 people.
8(d)/Rs (d=500 people) That is, the resistance value Rs is the lowest.

Therefore, as can be seen from the results in FIG. 2(a), the film thickness d of the n-type GaAs layer 5a is thicker from 100 to 1500 than the conventionally used thickness of 400 to 600. This can reduce the resistance value Rs(d), and this can also be inferred for the resistance value between the drain electrode 8 and the gate electrode 6.

In the 2DEGFET shown in FIG. 1, the n-type GaAs layer 5
The film thickness d of a is 400 to 6 in the conventional 2DEGFET.
The depth and lateral spread of the recess groove 9 are also larger due to the thicker thickness compared to the n-type GaAs layer 5a.
As mentioned above, there is a concern that increasing the thickness of the source electrode 7 or drain electrode 8 may increase the contact resistance value of the source electrode 7 or drain electrode 8 to the 2DEG layer 3. This can be prevented by etching the n-type GaAs layer 5a in the region where the electrode 8 is to be formed to a desired thickness.

In the above embodiment, the bottom of the recess groove 9 is of n-type AJ2G.
The case where it is in the aAs layer 4 is shown, but this is an n-type Aj2
It can be freely changed by changing the thickness of the GaAs layer 4, and it is also possible to manufacture a structure in which the bottom of the recess groove 9 is within the n-type GaAs layer 5a, as shown in the embodiment of FIG.

Also in this case, the n-type GaA in the part without the recess groove 9
The thickness d of the S layer 5a is 1000 to 1500.

〔Effect of the invention〕

As explained above, in this invention, the thickness of the third semiconductor layer for low resistance is set to 1,000 to 1,500 layers, and only the region where the source electrode and the drain electrode are formed is thinly formed. Another advantage is that the resistance value between the drain electrode and the gate electrode can be sufficiently reduced compared to conventional elements.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structure of an embodiment of the 2DEGFET of the present invention, FIG. 2 is a diagram for explaining the resistance value between the source electrode and the gate electrode, and FIG. 3 is the diagram of the 2DEGFET of the present invention.
FIG. 4 is a diagram showing the structure of another embodiment of the conventional 2DE
FIG. 2 is a diagram showing an example of a structure of a GFET. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs layer, 3 is a ZDEG layer, and 4 is an n-type AJ2GaA
s layer, 5a is an n-type GaAs layer, 6 is a gate electrode, 7 is a source electrode, 8 is a drain electrode, and 9 is a recess groove. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1! :I:Slot groove Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] A two-dimensional electron gas layer formed at a heterojunction interface between an undoped first semiconductor layer and a second semiconductor layer doped with impurities and having a larger band gap than the undoped semiconductor layer is used as a channel region; A field effect transistor comprising a third semiconductor layer for lowering resistance on the second semiconductor layer, and a gate electrode formed in a recess groove from which part or all of the third semiconductor layer is removed,
A field effect transistor characterized in that the third semiconductor layer has a thickness of 1000 to 1500 Å, and only the regions where the source electrode and the drain electrode are formed are thin.