JPS58130560A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the highly integrated IC wherein a threshold voltage value can be precisely controlled, by providing a reverse conductive layer under an active layer and attaching an electrode in an FET having as FF for driving a memory cell. CONSTITUTION:On the surface of a semiinsulating GaAs substrate 8, N<+> source and drain 9 and 10 and an N type active layer 3 are provided. A P layer 11 is embedded under the N layer 3 by ion implantation and annealing, and a back gate electrode 12 for controlling said layer 11 is provided. When a load voltage is gradually applied to the electrode 12 with a source electrode 6 as a reference, the threshold voltage value is continuously and gradually moved from the negative value (depression type) to the positive value (enhancement type). In this constitution, the FET, which is a constituent element of the FF applied memory cell, can be formed without additional major engineering requirements on the conventional processes, and the threshold voltage value can be precisely controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated device that can easily realize high-density integration of elements on a semiconductor substrate.

2. Description of the Related Art Integrated devices in which elements such as field effect transistors, diodes, resistors, and capacitors are densely integrated on a semiconductor substrate are being actively manufactured. However, the current situation is that field effect transistors, which play a central role among these elements, have to face restrictions in terms of integration because it is difficult to precisely control their characteristics. Below, the problems of conventional integrated devices will be specifically explained in E/Da memory circuits, which are typical memory circuits.

The main part of the memory is made up of periodic repetitions of memory cells. As shown in FIG. 1, a memory cell with an E/D configuration includes driving field effect transistors Tri and Tr.
2 (hereinafter abbreviated as drive FET), load field effect transistor '1'r3°Tr4 (hereinafter referred to as load FET)
Abbreviated as. ) and switch field effect transistor Tr5.
It is composed of a total of six field effect transistors (hereinafter abbreviated as FET), including Tr6 (hereinafter abbreviated as switch FET). Load PET Tr3. Tr4 is a depletion mFET (a FET that allows current to flow even when the gate voltage is zero), and a drive FET Tri.

Tr2 and switch FET Tr5. Tr6 is an enhancement mFET (an FET through which no current flows when the gate voltage is zero). In such a memory cell configuration, the operating margin of the threshold voltage value of the enhancement type FET is small, and for the enhancement type PET, precise control technology is required to keep the threshold voltage value exactly within that margin. required.

FETs that are often used in conventional GaAs integrated circuits are W
Schottky gate nl with the section 1ili# structure shown in J2 figure (a)! It is a field effect transistor (MESFET). Conventionally, the following two methods have been used to control the threshold voltage value in the MESFET having this structure.

(b) QaA8 of the gate electrode part before forming the gate electrode 1
A method in which the surface of the active layer 3 is etched by an appropriate thickness 2 to control the thickness 4 of the active layer 3 (FIG. 2(b)).

(b) A method of controlling the thickness 4 of the active layer 3 by optimizing the conditions of the ion implantation 5 for forming the active layer 3 (FIG. 2(C)).

However, with method 0), variations in the threshold voltage value occur between wafers or within a wafer due to instability of etching wrinkle control, and with method (b), G
a A 8 Due to variations in characteristics between wafers and within a wafer, such as impurity concentration and defects in the substrate crystal, variations in the threshold voltage value occur, so some MESFETs within the wafer
The threshold voltage value of E/
This results in a reduction in the operational yield of the D-configuration memory. here,
Although the explanation has been made using E/D configuration memory9 as an example, this is not the only example, but in memory circuits with a small operating margin of the threshold voltage value, as long as the conventional threshold voltage value control method is used9, the yield will decrease. is inevitable.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated device that satisfies the above-mentioned requirement for precise control of threshold voltage values and facilitates the realization of highly integrated circuits.

The conventional method of controlling the threshold voltage value can be viewed as a step in the process of manufacturing an integrated device. That is, in order to satisfy the requirement for precise control of the threshold voltage value, it is necessary to improve the process technology.

However, the present invention attempts to achieve the above object by adopting a new structure for the integrated device without imposing excessive technical demands on process technology.

That is, as the FET which is a constituent element of the integrated device, an FET having an electrode whose threshold voltage value can be controlled to an arbitrary value is used, and the threshold voltage value is closely controlled.

As the above-mentioned FET, it is preferable to use an FET that has a semiconductor layer of a conductivity type opposite to that of the active layer provided below the active layer and an electrode for controlling the semiconductor layer of the opposite conductivity type. This FET
(Hereinafter, this will be referred to as P-PET) A planar structure is shown in FIG. 3(a), and a cross-sectional structure along AA' is shown in FIG. 3(b).

The P-FET is similar to the conventional FET shown in FIG. 2(a) (the numbers in the figure below are common to FIGS. 2 and 3), with a source electrode 6. A semi-insulating GaA1 substrate 80 having three electrodes, a drain electrode 7 and a gate electrode 1.
It has a structure having n0 type source/drain regions 9, 10 and an n-deactive layer 3 in the surface layer. The characteristic structure of the P-FET is a p-type buried layer 11 provided under the active layer 3 and a back gate electrode 12 that controls this layer. This bank gate electrode 12 controls the threshold voltage value of the 1t) P-FET. That is, as a negative voltage is gradually applied to the bank gate electrode 12 with reference to the source electrode 6,
The threshold voltage value gradually and continuously shifts from negative (state of degression type F E 'r) to positive (state of enforcement type FET).

A PETTrl for driving a memory cell is shown in FIG. 1, in which a P-FET having the above-described structure and function is used.

Tr2 and switch FET Tr5. 'rr6 (7)
A circuit example of a memory cell used instead is shown in FIG. 4(a). Tr 1, 2, 5.6 (P-
The meaning of the symbol FET) is as shown in FIG. 4 φ). As shown in Fig. 4(a), all the gate electrodes of the P-FET are connected, and an appropriate negative voltage is applied thereto to form a P-11'ET (Tr 1.2.5°6). It becomes possible to easily keep the threshold voltage value within the operating range of the memory.Thereby, it is possible to improve the operating yield of the memory.

Although the PET active layer 3 is of n-type and the buried layer 11 is of p-type above, it goes without saying that the conductivity types may be reversed. Furthermore, although a memory cell with an E/D configuration is used as a circuit example, it is possible to apply the present invention to any memory integrated circuit that requires control of the threshold voltage value.

Specific examples are shown in FIGS. 5(a), Φ), (C), and (d).

FIG. 5(a) is a modification of the circuit in FIG. 4(a), and FIG. 4(a)(7) is a memory cell using load resistors R1 and R2 in place of load FETs Tr3 and Tr4. It is a circuit. Drive FET Tr 1. Tr 2 and switch FET Tr5. P-PET is used for Tr6.

Fig. 5 Φ) is also a driving FETTrl, Tf2 is P-F.
This is a memory cell circuit using ET.

Figures 5(C) and (d) are memory cells using diodes in place of the switching transistors in Figure 4(!I), 1, (C) is a resistor in the load, and (d) is in the load. It uses transistors. Drive PET Tri, P to Tr2
- Use PET.

The manufacturing process of the present invention will be explained below. Figure 6(a)-(
C) shows the manufacturing procedure of a memory cell configured with a P-FET and a conventional FET. FIG. 6 is a top view of the device, showing the basic parts.

First, as shown in FIG. 6(a), n+ layers 14, 15, 1 are added to the surface of the semi-insulating GaAl substrate 130 by selective ion implantation to impurity *<S (or S, etc.) as donors.
6. Then implant the active layer 17,18. Next, annealing is performed at a temperature of 5ooc or higher to form the NO layers 14 and 15.
．． 16 and active no. 17.18. Ion implantation is 150KeV, lXl0"m-" for 09 No.
, In the case of active nono, 125Ke■, 5X10"m-
Next, as shown in Figure 6(b), impurities (Be, Mg, etc.) that will serve as acceptors are selectively ion-implanted (191), and then annealed at a temperature of 600C or higher. Form p/11120°21.9 layers 20.2
50 to 150 keys to form 1, 1 x 1011 to 5 x
The conditions are about 1011cWI-1 (9 layers 20.21
Although not shown in the figure, they are connected in a different cross section. ). Then, zn was heated to a high concentration (I
Cl is diffused to form an open contact region 22 of the p layer. Finally, as shown in FIG. 6(C), after the AUGe alloy is deposited on the entire surface, it is processed using photolithography technology to form the back gate electrode 23. Source or drain electrodes 24, 25, and 26 are formed. Thereafter, a gate metal (Ti, Cr, At, etc.) is deposited on the entire surface and processed using photolithography technology to form a gate electrode 27.
, 28.

In Figure 6(C), area A is a P-FET, and area B is a normal FET.
The area of ET is shown. Note that 23 is an electrode for controlling the potential of the buried layer 20 of the P-FET and controlling the threshold voltage value of the P-FBT. The circuit configuration is as shown in FIG. 4 (or FIGS. 5(a) to 5(d)).

It goes without saying that the same manufacturing method may be used for circuits using PET of the opposite conductivity type.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional E/Dm memory cell, Fig. 2(a) is a cross-sectional view of a conventional FET, Fig. 2(b),
(C) is a cross-sectional view showing the gate part and the active layer directly below it;
Figure 3 (a) is a plan view of the P-FET, (b) is A-A
4(a) is a cross-sectional view of the E/D according to the present invention.
5(a) to 5(d) are circuit diagrams of another E/Dll memory of the present invention, Figure 6(a)-(C
) is a sectional view showing a manufacturing procedure of a memory integrated device according to the present invention. 1.27...Gate electrode, 3,17.18...Active layer, 6.7,24,25.26...Source drain #
L pole, 8.13... Semi-insulating QaA11 substrate, 9,1
0.14°15.16...source/drain region, 1
1,20°21... pfli buried layer, 12.23...
・Back gate or\] 1 Figure'\3 z Eup (Kyu) 'yfJ3 Figure (Dragon) (b) 1 4 days (b, 1 Source wealth 5 Figure (Ku) (b) %s Figure<C)

Claims (1)

[Claims] In a static memory cell having cross-connected flip-flops, a semiconductor node of a conductivity type opposite to that of the active layer is provided below the active layer as at least a driving transistor thereof, and an electrode for controlling the semiconductor layer is provided. A semiconductor memory integrated device characterized in that it uses a field effect transistor.